JPH06276734A - Overcurrent protective circuit - Google Patents

Abstract

PURPOSE:To supply load with pulse-shaped current at a specified level within a fixed time without limiting the pulse-shaped current, and to conduct positive protection from overcurrents at a level lower than the specified level within a time longer than the fixed time regarding an overcurrent protective circuit having two-stage constitution. CONSTITUTION:A current supply section 2 is controlled when detecting current by a current detecting section 3 exceed a first set value, and a first overcurrent protective section 4 limiting current fed to load 1 to the first set value or less and the current supply section 2 at working speed slower than working speed controlling the current supply section 2 by the first overcurrent protective circuit 4 when the detecting currents by the current detecting section 3 exceed a second set value smaller than the first set value are controlled. A second over current protective section 5 limiting current fed to the load 2 to the second set value or less is further provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overcurrent protection circuit having a two-stage structure for overcurrent protection. When a stabilized DC voltage is applied from a power supply such as a switching power supply to a load of various electronic devices, the current supplied to the load is detected, and when the current exceeds a preset current ,
An overcurrent protection circuit is used that controls the current by dropping the output voltage or cuts off the current. In such an overcurrent protection circuit, it is desired to enable optimum overcurrent protection corresponding to the characteristics of the load.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a conventional example, in which 41 is a load of various electronic equipments, 42 is a current supply section composed of a switching power supply, 43 is a current detection section composed of a current transformer, and 44 is an overcurrent A protection unit, 45 is a comparator, 46 is a main transformer, 47 is a switching transistor, 48 is a pulse width control circuit, and 49 is a reference voltage.

A direct current (not shown) is intermittently supplied to the primary winding of the main transformer 46 via a switching transistor 47, and the induced voltage in the secondary winding of the main transformer 46 is a diode. Is rectified and smoothed by a rectifying / smoothing circuit including a choke coil and a capacitor. The DC output voltage is load 4
1 is applied. This DC output voltage is applied to the input terminal IN of the pulse width control circuit 48, and the output terminal O of the pulse width control circuit 48 is set so that this DC output voltage becomes a set value.
The switching transistor 47 is controlled by the UT.
Thereby, the stabilized DC output voltage can be applied to the load 41.

The current supplied to the load 41 is detected by the current detector 43 and the comparator 45 of the overcurrent protector 44.
Added to. The current detection unit 43 shows a case where a voltage proportional to the current flowing in the primary winding of the current transformer is induced in the secondary winding and rectifies and smoothes it to obtain a detected value of the current. It is also possible to adopt a configuration in which the current is detected as a voltage drop.

Further, the overcurrent protection unit 44 compares the detected current value by the current detection unit 43 and the set value of the current for the overcurrent protection by the reference voltage 49 with the comparator 45, and the detected current value is the set value. The comparison output signal when the pulse width is exceeded is added to the dead time control terminal DT of the pulse width control circuit 48, and the dead time of the pulse width control circuit 48 is extended. That is,
The off time of the switching transistor 47 is controlled to be long, the output voltage droops, and the current supplied to the load 41 is limited.

FIG. 5 is an explanatory diagram of the pulse width control circuit.
51 is an oscillator, 52 and 53 are comparators, 54 and 55 are error amplifiers, 56 is a flip-flop, 57 is an OR circuit, 5
Reference numerals 8 and 59 are NOR circuits, 60 is an inverter, 61 and 62 are AND circuits, 63 and 64 are output transistors, 65 is a bias voltage, and 66 is a diode.

RT is a terminal for connecting a resistor R, CT is a terminal for connecting a capacitor C, DT is a dead time control terminal, and + IN and -IN correspond to the input terminal IN of FIG. Input terminal for applying divided voltage, FB for feedback terminal, OC for output control terminal,
C1, C2, E1, E2 are output transistors 63, 64
Is an output terminal connected to the collector and emitter of
These output terminals correspond to the output terminal OUT in FIG.

This pulse width control circuit shows a case where two output transistors 63 and 64 are provided so that the pulse width control circuit can be used for both the one-stone type and the two-stone type. When the output control terminal OC is set to "0", the output signals of the AND circuits 61 and 62 become "0", and the output transistors 63 and 64 are on / off controlled in phase according to the output signal of the OR circuit 57. Therefore, in the case of the one-stone type shown in FIG. 4, either one of the output transistors 63 and 64 is connected so as to drive the switching transistor 47 directly or via a driver.

When the output control terminal OC is set to "1", the AND circuit 6 operates according to the output signal of the flip-flop 56.
Since 1 and 62 are alternately "1" and "0", the output transistors 63 and 64 correspond to the inverting operation of the flip-flop 56 and are controlled to be turned on and off in reverse phase according to the output signal of the OR circuit 57. It Therefore, it is possible to drive the two-transistor switching transistor.

Further, the oscillator 51, for example, charges the capacitor C with a constant current and, when the terminal voltage of the capacitor C rises to a set value, rapidly discharges it to generate a sawtooth wave signal. , CT connected to the resistor R [kΩ] and the capacitor C [μF], the oscillation frequency f can be expressed as f≈1.2 / (RC) [kHz].

The comparator 53 has an inverted sawtooth wave signal and
The output signals of the error amplifiers 54 and 55 are compared, and the comparison output signal is added to the bases of the output transistors 63 and 64 via the OR circuit 57 and the NOR circuits 58 and 59. When the output transistors 63 and 64 are turned on, the switching transistor 47 shown in FIG. 4 is turned on and a direct current flows through the primary winding of the main transformer 46.

Even when no control signal is applied to the dead time control terminal DT, the bias voltage 65 is applied to the comparator 52 via the diode 66 and compared with the inverted sawtooth wave signal from the oscillator 51. . As a result, the ON / OFF duty of the output transistors 63 and 64 is not 100%.

In the overcurrent state, when the comparison output signal of the comparator 45 of the overcurrent protection unit 44 is applied to the dead time control terminal DT, there is almost no level difference from the inverted sawtooth wave signal, or The level of the comparison output signal becomes higher, and the output signal of the comparator 52 has a longer "1" period. As a result, the OFF period of the output transistors 63 and 64 becomes longer, and the OFF period of the switching transistor 47 becomes longer, so that the DC output voltage droops. That is,
The current supplied to the load 41 is limited or cut off.

[0014]

The overcurrent protection unit 44 of the conventional example should be protected by comparing the detected current value and the reference voltage 49 with the comparator 45 and setting the voltage value of the reference voltage 49. The overcurrent value can be determined. Therefore, when the current consumed by the load 41 has a relatively small fluctuation, the overcurrent value according to the maximum load current of the load 41 can be determined. However, if the load 41 has a characteristic of consuming a pulsed current and the peak value of the pulsed current becomes a large value compared to the steady load current of the load 41, the overcurrent value should be determined. Will not be easy.

For example, as shown in FIG. 6, the overcurrent value is OA1 for the pulse load currents a and b and the abnormal currents c and d.
According to the above, the shaded portions of the currents a, b, c, d are limited, and abnormal currents such as load short circuits indicated by c, d can be limited, but the pulse load currents indicated by a, b are also limited. As a result, the load cannot be supplied with the necessary current for the load that consumes the pulsed current. Therefore, if the overcurrent value is set to OA2, the pulse load currents a and b are supplied,
The abnormal current c can be limited. However, setting the overcurrent value to OA2 means that the overcurrent value OA is always continuous.
Since the current up to 2 can be output, it is necessary to make the output capacity of the power supply much larger than when the overcurrent value is set to OA1. Must be configured to withstand currents up to OA2.

As described above, the load 41 and the current supply unit 4
Considering the capacity of 2, it is desirable to set the overcurrent value for a long time to OA1, but in that case, the pulse load current a,
b has the drawback that all the shaded parts are restricted. If the overcurrent value is set to OA2, pulse load currents a and b
Will be supplied to the load as it is, but the abnormal current c
However, since the abnormal current d is limited to the current of OA2 and the abnormal current d does not exceed OA2, overcurrent protection cannot be performed, and a very large current continues to flow.
2 to the load 41.

Further, the response of the overcurrent protection unit 44 is delayed, and for example, the overcurrent value is set to OA1, and the pulse load current a,
A configuration is conceivable in which the current exceeding the overcurrent value OA1 is limited after a delay time equal to or larger than the pulse width of b. However, there is a drawback that it is impossible to protect against a very large current that exceeds the overcurrent value OA2 within the delay time, for example, an abnormal current as indicated by c. The present invention supplies a pulsed current to a load without limiting, and
The purpose is to reliably protect an overcurrent flowing over a longer time than the pulsed current.

[0018]

The overcurrent protection circuit of the present invention will be described with reference to FIG. 1. When the current detected by the current detection section 3 exceeds a first set value, the current supply section 2 is turned on. A second setting in which a current that is controlled by the first overcurrent protection unit 4 that limits the current supplied to the load 1 to a first set value or less and a current detected by the current detection unit 3 is smaller than the first set value. When the value exceeds the value, the current supply unit 2 is operated at a slower operation speed than the operation speed at which the first overcurrent protection unit 4 controls the current supply unit 2.
And a second overcurrent protection unit 5 that limits the current supplied to the load 1 to a second set value or less.

[0019]

The first overcurrent protection unit 4 compares the detected current value from the current detection unit 3 with the first set value, and when the detected current value exceeds the set value, the current supply unit 2 loads the load. The current supplied to 1 is limited to the first set value or less. In addition, the second overcurrent protection unit 5 detects the value of the detected current from the current detection unit 3 and the second
When the detected current value exceeds the set value, the current supplied from the current supply unit 2 to the load 1 is limited to the second set value or less. The operation speed of the overcurrent protection unit 5 of 2 is slowed down. Therefore, a pulse current having a peak value that does not exceed the first set value is supplied to the load 1 without limitation, and an excessive current that exceeds the first set value is immediately below the first set value. Is limited to. When the current is less than the first set value but exceeds the second set value, the current is limited with a slower response than when the current exceeds the first set value.

[0020]

EXAMPLE FIG. 2 is an explanatory view of an example of the present invention.
Is a load of various electronic devices, 12 is a current supply unit such as a switching power supply, 13 is a current detection unit, 14 and 15 are first and second overcurrent protection units, 16 is a main transformer, 17
Is a switching transistor, 18 is a pulse width control circuit, 19 and 20 are diodes, 21 is a choke coil,
22 is a capacitor, 23 is a current transformer, 24 is a resistor, 25 is a diode, 26 is a capacitor, 28, 31
Is a comparator, 29 and 32 are reference voltages, 30 and 35 are diodes, 33 is a resistor, and 34 is a capacitor.

The current supply unit 12 and the current detection unit 13 have the same configuration as the conventional switching power supply and current transformer. The DC output voltage applied to the load 11 or a voltage obtained by dividing the DC output voltage has a pulse width. Control circuit 18
In addition to the input terminal IN, the ON period of the switching transistor 17 is controlled according to the comparison result, and the DC output voltage is stabilized. It should be noted that the current supply unit 12 can adopt various configurations. The current detector 13 may be a resistor, or may be configured to detect the current flowing through the primary winding of the main transformer 16.

The first overcurrent protection unit 14 has a reference voltage 29 for applying the first set value to the negative terminal of the comparator 28, and the comparison output signal of the comparator 28 is pulse width controlled via the diode 30. It is applied to the dead time control terminal DT of the circuit 18. Further, the second overcurrent protection unit 15 has a reference voltage 32 for applying the second set value to the negative terminal of the comparator 31, and the output signal of the comparator 31 is an integral signal composed of a resistor 33 and a capacitor 34. It is applied to the dead time control terminal DT of the pulse width control circuit 18 via the circuit and the diode 35.

The pulse width control circuit 18 has, for example, the configuration shown in FIG. 5, and the comparison output signal is added to the dead time control terminal DT from the first overcurrent protection unit 14 or the second overcurrent protection unit 15. Then, the dead time is extended, and the off period of the switching transistor 17 is extended. Thereby, the DC output voltage droops, so that the current supplied to the load 11 can be limited.

FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention. When the current shown by the dotted line in FIG. 3A is about to flow into the load, the reference voltage 29 in the first overcurrent protection unit 14 is used. The first set value is L1, the second set value by the reference voltage 32 in the second overcurrent protection unit 15 is L2 (<L1), the operating speed of the first overcurrent protection unit 14 is t1, The operating speed of the second overcurrent protection unit 15 is t2 (<t1).
The operating speed t2 of the second overcurrent protection unit 15 corresponds to the time constant composed of the resistor 33 and the capacitor 34 of the second overcurrent protection unit 15. This slow operation speed t2 can be realized by other means. The operating speed t1 of the first overcurrent protection unit 14 includes the operating speed of the comparator 28 and the like, but is higher than the operating speed t2 of the second overcurrent protection unit 15.

Therefore, the first overcurrent protection unit 14 does not operate until the current flowing through the load 11 exceeds the first set value L1, and the current in the portion exceeding the first set value L1 is It is limited to be equal to or less than the first set value L1.
The operation time t2 is exceeded after the second set value L2 is exceeded.
After that, the second overcurrent protection unit 15 operates,
As a result, the current flowing through the load 11 is limited to the second set value L2 or less. That is, when the current shown by the dotted line is about to flow into the load, the limited current shown by the solid line flows into the load, and the current in the range shown by the diagonal line is limited. Therefore, the load 11 is not affected by a short-time overcurrent that exceeds the first set value L1.
Also, the current supply unit 12 can be reliably protected. Further, the load 11 and the current supply unit 12 can be protected against an overcurrent that flows for a relatively long time that exceeds the second set value L2.

The operating time t2 shown by the dotted line in FIG.
When a pulsed current having a shorter width is about to flow through the load 11, the hatched portion is limited for the current exceeding the first set value L1. However, the current that does not exceed the first set value L1 is supplied to the load 11 without being limited as long as the pulse width is the operation time t2 or less. Therefore, when the current indicated by the dotted line is about to flow into the load 11, the current indicated by the solid line is supplied to the load 11.
That is, even if the second set value L2 is exceeded, if the pulse width is the operation time t2 or less, the current can be supplied to the load 11 without being limited. When the second set value L2 is continuously exceeded by the operation time t2 or more, the second set value L2 is set.
The current supplied to the load 11 is limited so as to be 2 or less.

Therefore, according to the characteristics of the load 11, the first
By adjusting the reference voltage 29 of the overcurrent protection unit 14 and the reference voltage 32 of the second overcurrent protection unit 15.
Set value L1 and second set value L2 of the load 11 are stably supplied to the load 11 at a predetermined level, and the continuous overcurrent below the predetermined level is surely limited, so that the load 11 Also, the current supply unit 12 can be protected. It should be noted that the present invention is not limited to the above-described embodiment, but various additions and modifications can be made.

[0028]

As described above, according to the present invention, when the first set value L1 is exceeded, the current supplied to the load 1 is controlled to be limited to the first set value L1 or less. Of the overcurrent protection unit 4 and the second set value L2 (<L1), the current supplied to the load 1 is lower than the second set value L2 and slower than the first overcurrent protection unit 4. It has a two-stage configuration including a second overcurrent protection unit 5 which is controlled so as to limit the operating speed, and when the excessive current exceeds the first set value L1, the first Is set to be equal to or less than the set value L1 of the above, and for a current that exceeds the second set value L2 and is equal to or less than the first set value L1, the current is limited in the case of a pulse shape of the operation time t2 or less. For the current that is supplied to the load 1 without exceeding the second set value L2 and continues for the operation time t2 or more, It can be limited to a second set value L2 following. That is, even for a load that randomly consumes a pulsed current, the current is stably supplied from the current supply unit 2 including a switching power supply and the overcurrent in an abnormal state is surely protected. There is an advantage that can be.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of an example of the present invention.

FIG. 3 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of a conventional example.

FIG. 5 is an explanatory diagram of a pulse width control circuit.

FIG. 6 is an explanatory diagram of an overcurrent protection operation of a conventional example.

[Explanation of symbols]

 1 Load 2 Current Supply Section 3 Current Detection Section 4 First Overcurrent Protection Section 5 Second Overcurrent Protection Section

Claims (1)

[Claims] 1. A current detection unit (3) detects a current supplied from a current supply unit (2) to a load (1), and when the current detected by the current detection unit (3) exceeds a set value, In an overcurrent protection circuit that limits the current supplied from the current supply unit (2) to the load (1), when the current detected by the current detection unit (3) exceeds a first set value, the current A first overcurrent protection unit (4) for controlling the supply unit (2) to limit the current supplied to the load (1) to the first set value or less; and the current detection unit (3). When the detected current exceeds a second set value that is smaller than the first set value, it is compared with an operating speed at which the current supply section (2) is controlled by the first overcurrent protection section (4). The current supply unit (2) is controlled at a slow operation speed, and the current supplied to the load (1) is supplied to the second setting unit. Second over-current protection unit that limits a value below (5)
And an overcurrent protection circuit.