JPH0964206A - Semiconductor memory device - Google Patents

Semiconductor memory device

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Publication number
JPH0964206A
JPH0964206A JP7214728A JP21472895A JPH0964206A JP H0964206 A JPH0964206 A JP H0964206A JP 7214728 A JP7214728 A JP 7214728A JP 21472895 A JP21472895 A JP 21472895A JP H0964206 A JPH0964206 A JP H0964206A
Authority
JP
Japan
Prior art keywords
thin film
film
ferroelectric
semiconductor memory
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7214728A
Other languages
Japanese (ja)
Other versions
JP3746815B2 (en
Inventor
Masahiko Hirai
匡彦 平井
Yasuo Tarui
康夫 垂井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Asahi Chemical Industry Co Ltd
Original Assignee
Asahi Chemical Industry Co Ltd
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Filing date
Publication date
Application filed by Asahi Chemical Industry Co Ltd filed Critical Asahi Chemical Industry Co Ltd
Priority to JP21472895A priority Critical patent/JP3746815B2/en
Publication of JPH0964206A publication Critical patent/JPH0964206A/en
Application granted granted Critical
Publication of JP3746815B2 publication Critical patent/JP3746815B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device having a nonvolatile memory which operates at a high speed with little fatigue of the ferroelectric and is suited to reduction of the area, superior in the reproducibility and stability of the gate characteristic, with no carrier injected into the ferroelectric, and superior in the production yield. SOLUTION: On an Si single crystal substrate 1 having a source region 2 and drain region 3, an Si oxide film 4, oriented CeO2 film 5 and oriented PbTiO3 film 6 are formed and conductive film 7 is formed on other part than the part covered with an insulation film 8. A transistor having a multilayer structure composed of the films 4-6 acting as a gate thereof. The film 4 acts as a carrier injection blocking layer.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体記憶素子に
関し、特に、トランジスタのゲート部分に強誘電体を用
いてソース−ドレイン間電流を直接制御することができ
る不揮発性メモリに係るものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile memory capable of directly controlling a source-drain current by using a ferroelectric material in a gate portion of a transistor.

【0002】[0002]

【従来の技術】半導体記憶素子には、電源を投入してい
る間のみ情報を記憶することができる揮発性メモリと、
電源を断たれた状態においても情報を記憶することがで
きる不揮発性メモリとがある。揮発性メモリとしては、
DRAM(Dynamic Random Acces
s Memory)、SRAM(Static Ran
dom Access Memory)があり、不揮発
性メモリとしては、マスクROM(Mask Read
Only Memory)、PROM(Progra
mmable Read Only Memory)、
EPROM(Erasable Programmab
le Read Only Memory)、EEPR
OM(Electrically Erasable
Programmable Read Only Me
mory)等がある。
2. Description of the Related Art A volatile memory capable of storing information only while a power is turned on is provided in a semiconductor memory element.
There is a nonvolatile memory that can store information even when the power is turned off. As volatile memory,
DRAM (Dynamic Random Acces)
s Memory), SRAM (Static Ran)
Dom Access Memory), and a non-volatile memory is a mask ROM (Mask Read).
Only Memory), PROM (Program
mmable Read Only Memory),
EPROM (Erasable Programmab
le Read Only Memory), EEPR
OM (Electrically Erasable)
Programmable Read Only Me
memory).

【0003】これらの不揮発性メモリの中でもEPRO
M、EEPROMはRAMのように記憶内容を書き換え
ることができるROMで、コントロールゲートとチャネ
ルとの間にフローティングゲートを持つMOS−FET
(MOS型電界効果トランジスタ)構造をとるものが一
般的である。EPROMは、紫外線を照射することによ
りフローティングゲート内のキャリアを放出させて消去
動作をさせ、コントロールゲートとドレインの間に高電
圧を加えた際に生じるホットエレクトロンがフローティ
ングゲート内に残留することを利用して、書き込み動作
をさせる。EEPROMでは、紫外線を照射することな
く消去動作をさせることができる。
Among these non-volatile memories, EPRO
M and EEPROM are ROMs whose contents can be rewritten like RAMs, and are MOS-FETs having a floating gate between a control gate and a channel.
A device having a (MOS type field effect transistor) structure is generally used. EPROM uses the fact that hot electrons generated when a high voltage is applied between the control gate and the drain remain in the floating gate by radiating carriers in the floating gate by irradiating ultraviolet rays to perform an erase operation. Then, write operation is performed. In the EEPROM, the erasing operation can be performed without irradiating the ultraviolet rays.

【0004】[0004]

【発明が解決しようとする課題】しかし、上述したフロ
ーティングゲート型のMOS−FETは、書き込み、消
去動作には、ミリ秒(msec.)オーダーの時間と1
7 V/cmオーダーの高電界を必要とする。このた
め、EEPROMでは、通常のDRAMのように同一サ
イクルでの書き込み、消去動作を実現することができ
ず、また、電圧の高い電源も必要となる。
However, in the above-mentioned floating gate type MOS-FET, it takes a millisecond (msec.) Order and 1 time for writing and erasing operations.
A high electric field of the order of 0 7 V / cm is required. For this reason, the EEPROM cannot implement the write and erase operations in the same cycle as in a normal DRAM, and also requires a high voltage power supply.

【0005】また、最近開発が進められているFRAM
(Ferroelectric Random Acc
ess Memory)の多くはDRAMのキャパシタ
を強誘電体キャパシタに置き換えた構造をしており(特
開平2−113496号)、書き込み、消去、読み出し
動作いずれもが強誘電体の分極反転を伴うため、強誘電
体の疲労が問題となり、また、いずれの動作もキャパシ
タの充放電を伴うため、動作時間は100ナノ秒(ns
ec.)程度かかる。また、トランジスタとキャパシタ
を別々に設ける必要があり、面積縮小化に不利となる。
Further, an FRAM which has been recently developed
(Ferroelectric Random Acc
Ess Memory) has a structure in which a DRAM capacitor is replaced with a ferroelectric capacitor (Japanese Patent Laid-Open No. 2-113496), and all write, erase and read operations involve polarization reversal of the ferroelectric. Fatigue of the ferroelectric material poses a problem, and since every operation involves charging and discharging the capacitor, the operation time is 100 nanoseconds (ns).
ec. ) It takes a while. In addition, it is necessary to provide a transistor and a capacitor separately, which is disadvantageous for area reduction.

【0006】このような問題を解決するために、トラン
ジスタのゲート部分において、エピタキシャル酸化膜お
よび強誘電体薄膜を積層する構造を持つ半導体記憶素子
が提案されているが(特開平4−243232号)、高
速かつ、強誘電体の疲労が少なく、面積縮小化に適した
不揮発性メモリを提供する一方、トランジスタのゲート
特性に再現性、安定性の上で問題があり、生産上の収率
を高めることが難しかった。その原因として、Si基板
と強誘電体薄膜との界面制御が難しい上、Si基板から
強誘電体へキャリアが注入され強誘電体の分極が打ち消
されるなどが考えられる。
In order to solve such a problem, there has been proposed a semiconductor memory device having a structure in which an epitaxial oxide film and a ferroelectric thin film are laminated in a gate portion of a transistor (Japanese Patent Laid-Open No. 4-243232). While providing high-speed, non-volatile memory with less fatigue of ferroelectrics and suitable for area reduction, there is a problem in reproducibility and stability in the gate characteristics of transistors, which increases the yield in production. It was difficult. It is considered that this is because it is difficult to control the interface between the Si substrate and the ferroelectric thin film, and carriers are injected from the Si substrate into the ferroelectric to cancel the polarization of the ferroelectric.

【0007】本発明は、このような従来の技術が有する
未解決の課題を解決するべくなされたものであり、高速
かつ、強誘電体の疲労が少なく、面積縮小化に適し、特
に、ゲート特性において再現性、安定性に優れ、強誘電
体へのキャリア注入が無く、かつ生産上の収率向上に優
れた半導体記憶素子を提供することを目的としている。
The present invention has been made to solve the above-mentioned unsolved problems of the conventional techniques, and is suitable for reducing the area at high speed with less fatigue of the ferroelectric material, and particularly for the gate characteristics. It is an object of the present invention to provide a semiconductor memory device which is excellent in reproducibility and stability, has no carrier injection into the ferroelectric substance, and has an excellent yield improvement in production.

【0008】[0008]

【課題を解決するための手段】請求項1に記載の発明に
従う半導体記憶素子は、Si単結晶基板上に形成された
トランジスタを有する半導体記憶素子において、前記ト
ランジスタのゲート部分が、前記Si単結晶基板上に、
Si酸化膜からなるキャリア注入阻止層、配向したCe
2 薄膜、配向したPbTiO2 薄膜、導電体薄膜の積
層構造を持つことを特徴とする。
According to a first aspect of the present invention, there is provided a semiconductor memory device having a transistor formed on a Si single crystal substrate, wherein a gate portion of the transistor has the Si single crystal. On the board
Carrier injection blocking layer made of Si oxide film, oriented Ce
It is characterized by having a laminated structure of an O 2 thin film, an oriented PbTiO 2 thin film, and a conductor thin film.

【0009】請求項2に記載の発明に従う半導体記憶素
子は、請求項1に記載の半導体記憶素子において、前記
Si酸化膜の膜厚が20から100オングストロームで
あることを特徴とする。
A semiconductor memory element according to a second aspect of the present invention is the semiconductor memory element according to the first aspect, wherein the thickness of the Si oxide film is 20 to 100 angstroms.

【0010】請求項3に記載の発明に従う半導体記憶素
子は、請求項1に記載の半導体記憶素子において、前記
Si単結晶基板がSi(100)単結晶基板であること
を特徴とする。
A semiconductor memory element according to a third aspect of the present invention is the semiconductor memory element according to the first aspect, wherein the Si single crystal substrate is a Si (100) single crystal substrate.

【0011】[0011]

【発明の実施の形態】本発明において、配向したCeO
2 薄膜とは、常誘電体結晶の特定の結晶軸が基板面に対
し強く垂直に並んだCeO2 薄膜のことである。配向し
たPbTiO3薄膜とは、強誘電体結晶の特定の結晶軸
が基板面に対し強く垂直に並んだPbTiO3 薄膜のこ
とであり、特に分極を最も強く起こす結晶軸が基板に対
し強く垂直になることが好ましい。これらの結晶の配列
は、高速電子線回折、X線回折などにより確認すること
ができる。
BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, oriented CeO
The 2 thin film is a CeO 2 thin film in which specific crystal axes of paraelectric crystals are aligned strongly perpendicular to the substrate surface. The oriented PbTiO3 thin films, the specific crystal axis of a ferroelectric crystal is that of PbTiO 3 film vertically aligned strongly to the substrate surface, the crystal axis is perpendicular strongly to the substrate in particular allow polarization strongest It is preferable. The arrangement of these crystals can be confirmed by high-speed electron beam diffraction, X-ray diffraction and the like.

【0012】導電体薄膜としては、例えば、多結晶Si
に不純物を拡散し導電性を高めたもの、金属薄膜、導電
性酸化物薄膜等を用いることができる。
The conductor thin film is, for example, polycrystalline Si.
A metal thin film, a conductive oxide thin film, or the like in which impurities are diffused to improve conductivity can be used.

【0013】本発明の積層構造は、Si基板およびSi
基板に近い方から順にSi酸化膜、配向したCeO2
膜、配向したPbTiO3 薄膜、導電体薄膜からなる積
層構造であるが、必ずしも順に膜を積層してゆく必要は
ない。
The laminated structure of the present invention includes a Si substrate and a Si substrate.
The laminated structure is composed of a Si oxide film, an oriented CeO 2 thin film, an oriented PbTiO 3 thin film, and a conductor thin film in this order from the side closer to the substrate, but the films need not necessarily be laminated in order.

【0014】本発明において用いられる基板は、Siの
単結晶基板である。これは、CeO2 薄膜およびPbT
iO3 薄膜を配向させるために必要であり、PbTiO
3 薄膜の分極をより安定に発生させるためには、好まし
くは(100)もしくは(111)面に配向したものを
用いる。
The substrate used in the present invention is a Si single crystal substrate. This is a CeO 2 thin film and PbT
Necessary for orienting the iO 3 thin film, PbTiO 3
3 In order to more stably generate the polarization of the thin film, it is preferable to use one oriented in the (100) or (111) plane.

【0015】また、これらの常誘電性酸化物薄膜は、例
えば真空蒸着、レーザアブレーション法などによって形
成することができる。
Further, these paraelectric oxide thin films can be formed by, for example, vacuum deposition or laser ablation method.

【0016】Si単結晶基板とPbTiO3 薄膜との間
に設ける配向したCeO2 薄膜は、Si単結晶基板と配
向したPbTiO3 薄膜とが相互拡散して強誘電体が劣
化するのを防ぐために必要である。
[0016] Si CeO 2 thin film oriented provided between the single crystal substrate and PbTiO 3 film is required to prevent the ferroelectric and PbTiO 3 film oriented with the Si single crystal substrate by interdiffusion deteriorates Is.

【0017】キャリア注入阻止層としてのSi酸化膜
は、Si基板よりキャリアが注入され、強誘電性薄膜の
分極を打ち消してしまうのを防ぐ意味で重要であるばか
りでなく、ソース−ドレイン間電流を安定にオン・オフ
し、かつ製造上の歩留まり、収率の向上、素子の安定動
作のために不可欠である。また、このSi酸化膜からな
るキャリア注入阻止層の膜厚は、20から100オング
ストロームの間の値を持つものが特に好ましい。これ
は、界面の良好な電気特性を発揮し、Si単結晶基板と
配向した強誘電体薄膜との間でキャリアが移動して強誘
電体の分極が低下するのを防ぎ、かつ素子の動作電圧を
低く維持するために好ましい条件である。このSi酸化
膜は、配向した常誘電性酸化物薄膜を形成した後に酸化
雰囲気中において加熱処理する、あるいは配向した強誘
電体薄膜を形成する際に長時間酸化雰囲気にさらすこと
等によって形成することができる。
The Si oxide film as the carrier injection blocking layer is important not only for preventing carriers from being injected from the Si substrate and canceling the polarization of the ferroelectric thin film, but also for suppressing the source-drain current. It is indispensable for stable on / off, production yield, yield improvement, and stable device operation. Further, it is particularly preferable that the carrier injection blocking layer made of the Si oxide film has a film thickness of 20 to 100 angstroms. This exhibits good electrical characteristics of the interface, prevents carriers from moving between the Si single crystal substrate and the oriented ferroelectric thin film, and lowers the polarization of the ferroelectric. Is a preferable condition for maintaining low. This Si oxide film should be formed by heat treatment in an oxidizing atmosphere after forming an oriented paraelectric oxide thin film, or by exposing it to an oxidizing atmosphere for a long time when forming an oriented ferroelectric thin film. You can

【0018】本発明によるゲート電極を用い、強誘電体
の自発分極を反転させることによって、ソース−ドレイ
ン間電流をオン・オフすることができる。強誘電体の自
発分極を反転させるためには、基板−ゲート間、もしく
はドレイン−ゲート間、もしくはソース−ゲート間に電
圧を印加する必要がある。強誘電体の自発分極の反転速
度は極めて速く、DRAM以上の書き換え、消去の動作
速度を得ることができる。また、トランジスタの他にキ
ャパシタを設ける必要がないので、面積縮小化に有利と
なる。
By using the gate electrode according to the present invention and reversing the spontaneous polarization of the ferroelectric substance, the source-drain current can be turned on / off. In order to invert the spontaneous polarization of the ferroelectric substance, it is necessary to apply a voltage between the substrate and the gate, between the drain and the gate, or between the source and the gate. The reversal speed of the spontaneous polarization of the ferroelectric substance is extremely high, and the rewriting and erasing operation speeds higher than those of the DRAM can be obtained. Further, since it is not necessary to provide a capacitor in addition to the transistor, it is advantageous in reducing the area.

【0019】[0019]

【実施例】以下、本発明の実施例を図面に基づいて説明
する。
Embodiments of the present invention will be described below with reference to the drawings.

【0020】図1は本発明の半導体記憶素子を示す模式
的断面図である。図1において、1はSi単結晶基板、
2はSi単結晶基板1上に形成されたトランジスタのソ
ース、3は該トランジスタのドレイン、4はSi単結晶
基板1上に形成されたキャリア注入阻止層としてのSi
酸化膜、5はSi酸化膜4上に形成された常誘電性酸化
物薄膜としてのCeO2 薄膜、6はCeO2 薄膜5上に
形成された強誘電体薄膜としてのPbTiO3 薄膜、7
はPbTiO3 薄膜6に接続するアルミニウム電極であ
る。8は絶縁膜である。
FIG. 1 is a schematic sectional view showing a semiconductor memory element of the present invention. In FIG. 1, 1 is a Si single crystal substrate,
Reference numeral 2 is a source of a transistor formed on the Si single crystal substrate 1, 3 is a drain of the transistor, and 4 is Si as a carrier injection blocking layer formed on the Si single crystal substrate 1.
An oxide film, 5 is a CeO 2 thin film as a paraelectric oxide thin film formed on the Si oxide film 4, 6 is a PbTiO 3 thin film as a ferroelectric thin film formed on the CeO 2 thin film 5, 7
Is an aluminum electrode connected to the PbTiO 3 thin film 6. Reference numeral 8 is an insulating film.

【0021】まず、基板1として、抵抗率2Ωcmのn
型Si(100)単結晶基板を用い、この基板1を1×
10-6Torrの真空中において、約900℃に加熱し
た上で、CeO2 タブレットを電子ビーム加熱し、膜厚
約150オングストロームのCeO2 薄膜5をSi基板
1上に真空蒸着により成膜した。このCeO2 薄膜をR
HEED(反射高速電子線回折)により表面観察したと
ころ、いくつかのドットパターンを観測することがで
き、(110)配向のほぼエピタキシャル膜が成長して
いることが確認できた。
First, as the substrate 1, n having a resistivity of 2 Ωcm is used.
Type Si (100) single crystal substrate is used, and this substrate 1 is
After heating to about 900 ° C. in a vacuum of 10 −6 Torr, the CeO 2 tablet was subjected to electron beam heating to form a CeO 2 thin film 5 having a film thickness of about 150 angstrom on the Si substrate 1 by vacuum evaporation. This CeO 2 thin film is
When the surface was observed by HEED (reflection high-energy electron diffraction), some dot patterns could be observed, and it was confirmed that an approximately epitaxial film with a (110) orientation was grown.

【0022】次に、1気圧乾燥酸素雰囲気中で900℃
で5分間加熱し、Si基板1とCeO2 薄膜5の界面に
約40オングストロームのSiO2 キャリア注入阻止層
としてのSi酸化膜4を形成した。CeO2 薄膜の表面
に、導電体薄膜としてのアルミニウム(Al)電極7を
真空蒸着法により形成し、この電極を用いて静電容量−
電圧(C−V)特性を測定した。その結果、図2に示す
ように、印加電圧が1V程度までは実線で示すように、
静電容量(キャパシタンス)が印加電圧に対して直線的
に増加し、約2.2Vで飽和し、逆に印加電圧が低下す
るにつれて点線で示すように、ほぼ同じ経路を逆に辿っ
て低下し、負電圧の印加に対しては静電容量は実質的に
変化しない。このように、極めて良好なC−V特性が得
られ、CeO2 薄膜がゲート酸化膜として利用可能であ
ることが証明できた。この特性は、図3に示すように、
上述の酸化操作を行った場合は、上述の酸化操作を行わ
ない場合に比べて、界面準位が1013/cm2 ・eVか
ら1011/cm2 ・eVに改善している。界面準位は、
ゲート下部界面の結晶性の乱れを電気的に評価する手法
であり、C−V特性の傾斜から見積もることができる。
1011/cm2 ・eVオーダ以下の値であれば、良好な
界面と解釈することができる。
Next, 900 ° C. in a dry oxygen atmosphere of 1 atm.
And heated for 5 minutes to form a Si oxide film 4 as an SiO 2 carrier injection blocking layer of about 40 Å on the interface between the Si substrate 1 and the CeO 2 thin film 5. An aluminum (Al) electrode 7 as a conductor thin film is formed on the surface of the CeO 2 thin film by a vacuum vapor deposition method, and this electrode is used to set a capacitance-
The voltage (C-V) characteristic was measured. As a result, as shown in FIG. 2, when the applied voltage is up to about 1 V, as shown by the solid line,
The capacitance increases linearly with respect to the applied voltage and saturates at about 2.2V, and conversely, as the applied voltage decreases, as shown by the dotted line, it decreases in almost the same path in reverse. The capacitance does not substantially change with the application of a negative voltage. Thus, extremely good CV characteristics were obtained, and it was proved that the CeO 2 thin film can be used as a gate oxide film. This characteristic is as shown in FIG.
When the above-mentioned oxidation operation is performed, the interface state is improved from 10 13 / cm 2 · eV to 10 11 / cm 2 · eV as compared with the case where the above-mentioned oxidation operation is not performed. The interface state is
This is a method for electrically evaluating the disorder of the crystallinity at the interface under the gate, and can be estimated from the slope of the CV characteristic.
A value of 10 11 / cm 2 · eV or less can be interpreted as a good interface.

【0023】さらに、CeO2 /SiO2 /Si(10
0)上に、MOCVD法によりPbTiO3 薄膜6を成
膜した。すなわち、Pb(C254 、Ti(i−O
374 を材料とし、それぞれ0℃、30℃の温度
に保ち、それぞれ7cc/分、4.5cc/分のキャリ
アN2 ガスで材料を運び、30cc/分のO2 とともに
基板温度540℃のCeO2 /SiO2 /Si(10
0)基板からなる構造体に吹き付け、PbTiO3 薄膜
6を成膜した。雰囲気圧力は、約1Torrであった。
また、膜厚は、約1000オングストロームであった。
この薄膜をX線回折装置を用いて分析を行ったところ、
PbTiO3 (100)、(001)面に強く配向して
いることが確認できた(図4)。
Further, CeO 2 / SiO 2 / Si (10
0), a PbTiO 3 thin film 6 was formed by MOCVD. That, Pb (C 2 H 5) 4, Ti (i-O
C 3 H 7 ) 4 is used as the material, the temperature is maintained at 0 ° C. and 30 ° C., respectively, and the material is carried by carrier N 2 gas at 7 cc / min and 4.5 cc / min, respectively, and the substrate temperature together with O 2 at 30 cc / min CeO 2 / SiO 2 / Si (10
0) The PbTiO 3 thin film 6 was formed by spraying on the structure consisting of the substrate. The ambient pressure was about 1 Torr.
The film thickness was about 1000 Å.
When this thin film was analyzed using an X-ray diffractometer,
It was confirmed that PbTiO 3 (100) and (001) planes were strongly oriented (FIG. 4).

【0024】このサンプルの断面を透過電子顕微鏡(T
EM)を用いて観察したところ、図5に模式的に示すよ
うに、PbTiO3 /CeO2 /SiO2 /Si(10
0)積層構造体が形成されていることを確認した。詳し
くは、この積層構造体は、Si(100)基板1、Si
酸化薄膜(SiO2 薄膜)4、CeOx 膜5a、CeO
2 薄膜5、PbTiO3 薄膜6がこの順に積層されてお
り、Si基板とCeO2 薄膜の間にSiO2 薄膜が形成
されていることを確認した。
A cross section of this sample was taken with a transmission electron microscope (T
When observed using EM), as shown schematically in FIG. 5, PbTiO 3 / CeO 2 / SiO 2 / Si (10
0) It was confirmed that a laminated structure was formed. Specifically, this laminated structure is composed of a Si (100) substrate 1, Si
Oxide thin film (SiO 2 thin film) 4, CeO x film 5a, CeO
It was confirmed that the 2 thin film 5 and the PbTiO 3 thin film 6 were laminated in this order, and the SiO 2 thin film was formed between the Si substrate and the CeO 2 thin film.

【0025】さらに、このサンプル表面にアルミニウム
電極7を真空蒸着にて形成し、静電容量−電圧(C−
V)特性を測定した。その結果、図6に示すような掃引
方向によるヒステリシス特性を示し(メモリ−ウィンド
ウ幅2.3V)、記憶動作を確認した。ここで、いった
ん−3Vから+3Vまでバイアス電圧を掃引した後、メ
モリ−ウィンドウ中央部における静電容量を測定し、そ
の時間変化を観察した。この操作により、このサンプル
の記憶保持時間を測定することができる。その結果、キ
ャリア注入阻止層を特に形成しなかったものは、約27
時間で静電容量が20パーセント以上低下したのに対
し、上記のようにキャリア注入阻止層を形成したもの
は、1カ月経っても静電容量の低下は観察されなかっ
た。
Further, an aluminum electrode 7 is formed on the surface of this sample by vacuum evaporation, and the capacitance-voltage (C-
V) The characteristics were measured. As a result, a hysteresis characteristic depending on the sweep direction as shown in FIG. 6 was shown (memory-window width 2.3 V), and the storage operation was confirmed. Here, after the bias voltage was once swept from -3V to + 3V, the capacitance in the central portion of the memory-window was measured, and the change with time was observed. By this operation, the storage retention time of this sample can be measured. As a result, in the case where the carrier injection blocking layer was not particularly formed, about 27
While the electrostatic capacity decreased by 20% or more with time, in the case where the carrier injection blocking layer was formed as described above, the decrease in the electrostatic capacity was not observed even after one month.

【0026】さらに、ソース、ドレイン間に上記PbT
iO3 /CeO2 /SiO2 を形成し、Al電極を設け
てソース−ドレイン間電流のオン、オフをPbTiO3
の自己分極を用いて制御する試みを行い、その現象を確
認した。
Further, the PbT is provided between the source and the drain.
io 3 / CeO 2 / SiO 2 is formed, and an Al electrode is provided to turn on / off the current between the source and the drain with PbTiO 3
An attempt was made to control it by using the self-polarization of, and the phenomenon was confirmed.

【0027】[0027]

【発明の効果】以上の説明のように、本発明によれば、
Si基板上に配向成長したCeO2 (常誘電体)薄膜を
形成した後、酸化雰囲気中において加熱することによっ
てSi基板とCeO2 薄膜との界面にSi酸化膜からな
るキャリア注入層を形成し、この層を介して、高配向P
bTiO3 (強誘電体)薄膜を形成することにより、S
i基板から強誘電体にキャリアが注入されるのを防ぐば
かりでなく、極めて安定に強誘電体の自己分極により直
接ソース−ドレイン間の電流をオン、オフすることがで
きる。現在研究が進められているFRAMに比較して、
読み出し動作では自発分極の反転を伴わないため、強誘
電体の膜疲労が極めて少なく、また、トランジスタ以外
の領域にキャパシタを設ける必要がないため、面積縮小
化に適した不揮発性メモリを提供できる。さらに、従来
困難とされてきた界面の制御を、界面にSi酸化膜から
なるキャリア注入阻止層をCeO2 形成後に加熱して形
成することによって達成し、基板から強誘電体へのキャ
リア注入を阻止し、さらにゲート特性を向上させること
ができる。このように、多くの優位性を有した不揮発性
メモリを提供できるなどの効果がある。
As described above, according to the present invention,
After forming the oriented growth CeO 2 (paraelectric) thin film on the Si substrate, by heating in an oxidizing atmosphere to form a carrier injection layer made of a Si oxide film at the interface between the Si substrate and the CeO 2 thin film, Highly oriented P through this layer
By forming a bTiO 3 (ferroelectric) thin film, S
Not only can carriers be prevented from being injected into the ferroelectric substance from the i-substrate, but also the current between the source and the drain can be directly turned on and off very stably due to the self-polarization of the ferroelectric substance. Compared to FRAM, which is currently being researched,
Since the reading operation does not involve the reversal of spontaneous polarization, the film fatigue of the ferroelectric is extremely small, and since it is not necessary to provide a capacitor in a region other than the transistor, a nonvolatile memory suitable for area reduction can be provided. Furthermore, the interface control, which has been considered difficult in the past, was achieved by forming a carrier injection blocking layer consisting of a Si oxide film on the interface by heating after forming CeO 2, and blocking carrier injection from the substrate to the ferroelectric substance. In addition, the gate characteristics can be further improved. Thus, there is an effect that a nonvolatile memory having many advantages can be provided.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例に従う半導体記憶素子の基本
構造を示す模式的断面図である。
FIG. 1 is a schematic cross-sectional view showing a basic structure of a semiconductor memory element according to an embodiment of the present invention.

【図2】Si(100)基板上にCeO2 を真空蒸着
し、酸化雰囲気で加熱処理を行ったものに、Al電極を
蒸着し、静電容量−電圧(C−V)特性を測定した結果
を示す特性図である。
FIG. 2 is a result of measuring capacitance-voltage (C-V) characteristics by vapor-depositing CeO 2 on a Si (100) substrate and performing heat treatment in an oxidizing atmosphere, then depositing an Al electrode. FIG.

【図3】Si(100)基板上にCeO2 を真空蒸着し
たものに、Al電極を蒸着し、静電容量−電圧(C−
V)特性を測定した結果を示す特性図である。
FIG. 3 shows a vacuum deposition of CeO 2 on a Si (100) substrate on which an Al electrode is deposited and a capacitance-voltage (C-
V) is a characteristic diagram showing a result of measuring characteristics.

【図4】Si(100)基板上にCeO2 を真空蒸着し
たものにさらにPbTiO3 をCVD法により成膜し、
その試料をX線回折装置を用いて分析を行った結果を示
す特性図である。
FIG. 4 is a diagram in which CeO 2 is vacuum-deposited on a Si (100) substrate and PbTiO 3 is further deposited by a CVD method,
It is a characteristic view which shows the result of having analyzed the sample using the X-ray-diffraction apparatus.

【図5】PbTiO3 /CeO2 /SiO2 /Si(1
00)試料の断面構造を透過電子顕微鏡により観察した
結果を模式的に表す断面図である。
FIG. 5: PbTiO 3 / CeO 2 / SiO 2 / Si (1
00) is a cross-sectional view schematically showing the result of observing the cross-sectional structure of the sample with a transmission electron microscope.

【図6】図5に示す試料の表面にAl電極を真空蒸着に
より形成した後、静電容量−電圧(C−V)特性を測定
した結果を示す特性図である。
6 is a characteristic diagram showing a result of measuring an electrostatic capacity-voltage (CV) characteristic after forming an Al electrode on the surface of the sample shown in FIG. 5 by vacuum vapor deposition.

【符号の説明】[Explanation of symbols]

1 Si単結晶基板 2 ソース 3 ドレイン 4 Si酸化膜 5 常誘電性酸化物薄膜としてのCeO2 薄膜 6 強誘電体薄膜としてのPbTiO3 薄膜 7 アルミニウム(Al)電極 8 絶縁膜1 Si Single Crystal Substrate 2 Source 3 Drain 4 Si Oxide Film 5 CeO 2 Thin Film as Paraelectric Oxide Thin Film 6 PbTiO 3 Thin Film as Ferroelectric Thin Film 7 Aluminum (Al) Electrode 8 Insulating Film

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 27/108 21/8242 Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI technical display area H01L 27/108 21/8242

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】 Si単結晶基板上に形成されたトランジ
スタを有する半導体記憶素子において、前記トランジス
タのゲート部分が、前記Si単結晶基板上に、Si酸化
膜からなるキャリア注入阻止層、配向したCeO2
膜、配向したPbTiO2 薄膜、導電体薄膜の積層構造
を持つことを特徴とする半導体記憶素子。
1. A semiconductor memory device having a transistor formed on a Si single crystal substrate, wherein a gate portion of the transistor has a carrier injection blocking layer made of a Si oxide film and oriented CeO on the Si single crystal substrate. A semiconductor memory device having a laminated structure of two thin films, oriented PbTiO 2 thin films, and conductor thin films.
【請求項2】 前記Si酸化膜の膜厚が20から100
オングストロームであることを特徴とする請求項1に記
載の半導体記憶素子。
2. The thickness of the Si oxide film is 20 to 100.
The semiconductor memory element according to claim 1, wherein the semiconductor memory element is Angstrom.
【請求項3】 前記Si単結晶基板がSi(100)単
結晶基板であることを特徴とする請求項1に記載の半導
体記憶素子。
3. The semiconductor memory device according to claim 1, wherein the Si single crystal substrate is a Si (100) single crystal substrate.
JP21472895A 1995-08-23 1995-08-23 Semiconductor memory device Expired - Fee Related JP3746815B2 (en)

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JP21472895A JP3746815B2 (en) 1995-08-23 1995-08-23 Semiconductor memory device

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Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010007164A (en) * 2008-06-30 2010-01-14 Furukawa Electric Co Ltd:The Method for forming thin film of oxide

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010007164A (en) * 2008-06-30 2010-01-14 Furukawa Electric Co Ltd:The Method for forming thin film of oxide

Also Published As

Publication number Publication date
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