JPH0964045A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a layer having lower polishing velocity than chemical and mechanical polishing velocities selectively only on a part having low step and to suppress the process cost. SOLUTION: An insulating film 4 having higher polishing velocity than chemical and mechanical polishing velocities and an insulating film 5 having lower polishing velocity than them on the film 4 are formed to cover a metal interconnection 3, and a P-type photoresist 6 is formed on the film 5. A light for photosensing the resist 6 is emitted without using a mask, and the resist 6 is exposed by utilizing the reflection from the interconnection 3. With the resist pattern formed via a developing step used as a mask the film 5 is etched by dry etching, selectively removed, and the film 5 selectively remains at the bottom of the surface step of the film 4. After the resist is removed, the surface of the film 4 is polished by chemical and mechanical polishing to be flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor integrated circuit device having multi-layer metal wiring, and more particularly to a method characterized by a step of flattening a surface of an interlayer insulating film between metal wirings.

[0002]

2. Description of the Related Art In a multilayer wiring of a semiconductor integrated circuit device, a lower layer and an upper layer of metal wiring are connected through a through hole (also called a via hole) formed in an interlayer insulating film between the metal wirings. As the density of semiconductor integrated circuit devices is increased and the density is increased, the elements are miniaturized and the wiring is also miniaturized. In order to form a fine metal wiring on the interlayer insulating film, a fine resist pattern must be formed on the wiring metal film by lithography, but if there is a large step in the interlayer insulating film, the lithography process can be performed. It becomes difficult to form a fine resist pattern. Therefore, in order to flatten the surface of the interlayer insulating film, the surface of the insulating film is chemically / mechanically polished (CMP).

Several improvements have been proposed as a method of planarizing the surface of an insulating film by using chemical / mechanical polishing. First
The method is a method of forming a diamond layer or a diamond-like carbon layer having a hardness higher than that of the interlayer insulating film on the interlayer insulating film as a stop layer for chemical / mechanical polishing by the CVD method, and then performing the chemical / mechanical polishing ( Japanese Patent Laid-Open No. 5-218
No. 000).

A second method is a method in which CMP is performed after forming silicon nitride or the like as a hard cap layer on the interlayer insulating film in order to flatten the groove portion (Japanese Patent Laid-Open No. Hei 5 (1999) -53119).
-259135). The third method is a method of forming a hard film such as a silicon nitride film on a portion of the interlayer insulating film having a low step using a photolithography technique, and then performing chemical / mechanical polishing (monthly Semiconducto
r Wlrld 1992.10, pp.43-44).

[0005]

[Problem to be Solved by the Invention] First, a layer having a high hardness is provided on the uppermost part of an insulating film to be subjected to chemical / mechanical polishing.
The method 2 and the second method are capable of global planarization (overall planarization) as compared with chemical / mechanical polishing without providing such a layer having high hardness, but the method 3 There is a drawback in that global flatness is inferior to the method in which a high hardness film is selectively provided only in a portion having a low step.

The third method is excellent in global flatness, but it requires a photolithography step using a mask, which requires a mask for photography, and also increases the number of steps, resulting in process cost. Will increase. Therefore, an object of the present invention is to selectively form a layer having a low polishing rate for chemical / mechanical polishing only in a portion having a low step portion as in the third method and to suppress the process cost thereof. Is.

[0007]

The present invention has the following steps (A):
To (D), the surface of the interlayer insulating film on the metal wiring is flattened. (A) A step of forming an insulating film, which will be an interlayer insulating film between the metal wiring formed later on the base on which the metal wiring is formed, and (B) a positive photo film on the insulating film. After applying the resist, a lithography process of exposing the photoresist by utilizing reflection from the metal wiring under the insulating film without using a mask and developing it to selectively remove the photoresist on the metal wiring, ( C) a step of etching the insulating film thereunder in a part of its thickness direction using the photoresist patterned by the lithography step as a mask, (D) removing the photoresist, and then performing chemical / mechanical polishing A step of flattening the surface of the insulating film. In a preferred embodiment, the insulating film serving as the interlayer insulating film has a two-layer structure, the polishing rate of the upper insulating film is lower than the polishing rate of the lower insulating film in chemical / mechanical polishing, and the step (C) It is the upper insulating film that is etched in.

In another preferred embodiment, when forming the metal wiring on the base, an antireflection film for the exposure wavelength for forming the metal wiring resist pattern is formed on the metal film for the metal wiring, and the metal wiring is formed. After formation, the antireflection film is removed. In still another preferred embodiment, when a metal wiring is formed on a base, a film having a wavelength dependency of reflectance is formed on the metal film for the metal wiring, and a metal wiring resist pattern is formed by lithography. In the process, exposure is performed at a wavelength at which the reflectance of the film becomes small, and the film is left on the metal wiring,
An insulating film to be an interlayer insulating film is formed on the metal wiring,
In the step of applying a photoresist on it and exposing the photoresist by utilizing the reflection from the metal wiring,
A wavelength that increases the reflectance of the film is used. A TiN film can be used as the film having the wavelength dependence of the reflectance, and the N / Ti composition ratio of the TiN film is preferably less than 1 in terms of molar ratio.

When there is a substance having a high reflectance under the resist layer, incident light at the time of exposure is reflected by the underlayer, and the exposure sensitivity of the photoresist above it is increased. FIG. 1 shows the relationship between the reflectance of the underlying layer and the resist sensitivity. As a resist, a positive type ip2800 (a product of Tokyo Ohka Co., Ltd.) is formed to a thickness of 1 μm, and an exposure wavelength of 36 is used.
This is the case when the i line of 5 nm is used. The resist sensitivity is represented by the time required for proper exposure, and the resist sensitivity increases as the background reflectance increases.

As miniaturization of the semiconductor integrated circuit device progresses, there is a problem that the image formed on the resist is blurred due to reflection from the underlayer and the exposure sensitivity is changed. An antireflection film is generally formed on the metal film for wiring in order to suppress it.
However, the present invention utilizes reflection from the substrate to expose the photoresist.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 2 shows one embodiment of the present invention. (A) The lower insulating film 2 covers the silicon substrate 1 on which the semiconductor element is formed, and the metal wiring 3 is formed thereon. The metal wiring 3 and the substrate 1 are connected via a contact hole provided in the insulating film 2. Two layers of insulating films 4 and 5 which cover the metal wiring 3 and serve as interlayer insulating films are formed. The lower insulating film 4 is an insulating film having a high polishing rate against chemical / mechanical polishing, and the upper insulating film is formed. The film 5 is an insulating film having a polishing rate lower than that of the lower insulating film 4 in chemical / mechanical polishing. The insulating film 4 is a silicon oxide film or a silicon oxide film-based insulating film containing phosphorus or boron. The insulating film 5 is a silicon nitride film, a diamond film, a diamond-like carbon film, or the like, which is also described in the above cited document. A positive photoresist 6 is applied on the insulating film 5 and baked to form it.

The resist 6 is exposed, but in the present invention, the resist 6 is exposed by irradiating it with light that does not use a mask. A feature of the present invention is that a mask is not used, and it is preferable that the irradiation light has a wavelength having a high reflectance with respect to the underlying metal wiring 3. By properly setting the exposure time, the resist 6 in a portion where the metal wiring occupies a large proportion in macroscopic sense is exposed, and the other resists 6 are not exposed.

(B) After that, through a developing process, the resist 6 on the exposed portion is removed. (C) The insulating film 5 is etched by dry etching using the resist pattern formed on the insulating film 5 as a mask to selectively remove it. The insulating film 5 selectively remains at the bottom of the stepped portion of the surface of the insulating film 4. After that, the resist is removed.

(D) The surface of the insulating film 4 is polished by chemical / mechanical polishing to flatten it. Macroscopically, the level difference on the surface of the insulating film 4 in the portion where the underlying metal wiring 3 occupies a large amount is high, and the level difference in the portion where the underlying metal wiring 3 does not exist is low and the polishing rate is low. Remains, and in chemical / mechanical polishing, a portion with a large step is an insulating film with a high polishing rate, so that global planarization is realized as introduced in the third conventional method.

The advantage of the method of performing the exposure only by the reflection from the metal wiring without using a mask is as follows.
There are two points. (1) Since no mask is used, no mask cost is required, resulting in low cost. (2) When exposure is performed, it is not necessary to focus like a stepper, and a uniform light source is sufficient. Therefore, an inexpensive light source can be used, which is economical, and focusing and positioning are performed. There is no need, and the operating rate of the device is high. (3) Since the reflection from the base is used, there is no microscopic resolution, and the macroscopic reflectance of the base is reflected. Therefore, macro planarization (that is, global planarization), which is currently a problem in chemical / mechanical polishing, is realized.

FIG. 3 shows a second embodiment of the present invention. In FIG. 2, the interlayer insulating film has a two-layer structure, whereas in FIG. 3, the conventional one-layer interlayer insulating film 4 is formed. (A) Positive photoresist 6 on one layer of interlayer insulating film 4
2, the photoresist 6 is exposed by utilizing the reflection from the lower metal wiring 3 as in FIG. 2, and the resist 6 is selectively removed through a developing process. In this state, as in FIG. 2B, the resist 6 remains only in the lower portion of the step portion of the insulating film.

(B) The resist 6 is used as a mask to dry-etch the exposed portion of the insulating film 4 by a predetermined amount. Since the portion of the insulating film 4 exposed from the resist 6 has a high level difference, the dry etching causes a level difference on a microscopic scale, but a macroscopically uniform surface state is formed. After that, the resist 6 is removed.

(C) After that, the surface of the insulating film 4 is flattened by chemical / mechanical polishing. According to this method, in the step (b), a local step is formed at the boundary between the presence and absence of the resist, but chemical / mechanical polishing has excellent polishing flatness against the local step. Global flatness similar to that of the embodiment can be obtained.

A third embodiment will be described. During lithography, if there is reflection from the base, the resolution will decrease, so a material with low reflection is required as the wiring material.
On the other hand, in the present invention, since the photoresist is exposed by utilizing the reflection from the base, it is required that the reflection is large.
In order to satisfy these two contradictory conditions, the following two methods are adopted.

In the first method, an antireflection film is formed on the metal wiring in a lithography step for forming a resist pattern for forming the metal wiring, and the wiring metal layer is etched and patterned. This is a method of removing the antireflection film. As the antireflection film, an antireflection coating resist, a SiC film, and the like are known.

In the second method, a layer whose reflectance has wavelength dependency is formed on a metal layer for metal wiring, and the reflectance of the layer is changed in a lithography process for forming a resist pattern for metal wiring. In the process of exposing the photoresist on the interlayer insulating film by using the smaller wavelength and utilizing the reflection from the metal wiring, on the contrary, the wavelength of the higher reflectance is used.

Ti is used as a film whose reflectance has wavelength dependence.
There is an N film. FIG. 4 shows the wavelength dependence of the reflectance when the composition ratio (molar ratio) of the TiN film is changed.
In a TiN film having an N / Ti composition ratio of less than 1, for example, 0.5, the reflectance increases as the wavelength becomes longer, and in lithography for patterning, light on the short wavelength side with low reflectance is irradiated to reflect. On the contrary, in the step of exposing the resist to light, light on the long wavelength side where the reflectance becomes large is irradiated.

[0023]

【Example】

(Embodiment 1) A first embodiment will be described in detail with reference to FIG. (A) 6 having <100> orientation and a specific resistance of 20 Ωcm
A silicon oxide film 2 having a thickness of 1 μm was formed as a lower insulating film on the inch P-type silicon wafer 1 by using a plasma CVD method. On top of that, use the sputtering method
l-Si-Cu film (98.5% Al, 1% Si, C
(0.5% u) was deposited to a thickness of 600 nm. An undercoat resist for antireflection (a product of Japan Synthetic Rubber Co., Ltd.) is applied on top of this to a thickness of 100 nm, and then P is applied on top of it.
Mold photoresist ip2800 (product of Tokyo Ohka Co., Ltd.) was applied to a thickness of 1 μm. Then, using an i-line stepper, exposure for forming a photoresist pattern for forming metal wiring is performed using a mask for an exposure time of 350
It was done in milliseconds. After developing the photoresist to form a resist pattern, the metal film was patterned by a dry etching apparatus of RIE (reactive ion etching) system, and then the resist and the undercoat resist were removed.

A silicon oxide film 4 having a film thickness of 2 μm and a silicon nitride film 5 having a film thickness of 2000 Å were sequentially formed on the metal wiring 3 thus formed by the plasma CVD method. Next, a P-type photoresist i is formed on the silicon nitride film 5.
p2800 was applied to a thickness of 1 μm, and this time exposure was performed without using a mask. The exposure time at this time was 280 milliseconds.

(B) The resist 6 was developed to form a pattern of the resist 6. (C) Using the pattern of the resist 6 as a mask, RI
The silicon nitride film 5 was selectively removed by an E-type dry etching apparatus. (D) After removing the resist 6, the silicon oxide film 4 was flattened by a chemical / mechanical polishing apparatus. For chemical / mechanical polishing, a CMP apparatus manufactured by Westec Co. was used, and a KOH solution in which SiO ₂ fine particles were dispersed was used as a slurry. The flatness of the insulating film in the wafer surface after polishing for 1 minute at a polishing pressure of 5 PSI was evaluated by a film thickness meter. Table 1 shows the results.

[0026]

[Table 1]

As the insulating film having a low polishing rate, a diamond film or a diamond-like carbon film may be used in addition to the silicon nitride film 5.

(Second Embodiment) A second embodiment will be described in detail with reference to FIG. The same process as in Example 1 was performed except that the insulating film on the metal wiring 3 in Example 1 was one layer of the silicon oxide film 4, and after the resist 6 was developed, the silicon oxide film 4 was removed by a dry etching apparatus of the RIE system. Selectively 600
Etched to a thickness of nm. After that, the 6 resist was removed, and the silicon oxide film 4 was flattened by a CMP apparatus. The conditions of chemical / mechanical polishing were the same as in Example 1. Table 1 also shows the result of the flatness in the wafer surface of Example 2.

(Example 3) A TiN film was continuously formed in vacuum on the Al-Si-Cu film for metal wiring in Example 1. A reactive sputtering method using Ti as a sputtering target was used for forming the TiN film. The film forming conditions are a gas pressure of 3 mTorr and an Ar flow rate of 10
0 sccm, N ₂ flow rate 10 sccm, RF power 500
W. The N / Ti composition ratio of the film formed under these conditions was 0.5 in terms of molar ratio, and the wavelength dependence of the reflectance shown by the broken line in FIG. 4 was shown.

Next, lithography for forming a resist pattern for metal wiring was performed using an i-line stepper. As the resist, ip2800 was applied to a thickness of 1 μm, and the exposure time was 310 milliseconds.
After forming the resist pattern, the metal film was etched with the RIE dry etching apparatus using the resist pattern as a mask to form metal wiring. Then, with the TiN film left on the metal film, a silicon oxide film and a silicon nitride film were sequentially formed to a thickness of 2 μm and 2000 Å, respectively, by the plasma CVD method as in the embodiment of FIG.

Next, P-type OFPR-800 (a product of Tokyo Ohka Co., Ltd.) was applied to a thickness of 1 μm as a resist sensitive to g-line (436 nm), and exposed using a aligner without using a mask. Was done. Exposure time is 10
Seconds After development and baking, only the silicon nitride film was selectively etched by dry etching under the same conditions as in Example 1. The subsequent steps were the same as in Example 1. The flatness results of Example 3 are also shown in Table 1.

(Comparative Example) After forming the insulating films 4 and 5 on the metal wiring 3 in Example 1 using FIG. 2, the steps of forming the resist 6 and exposing the same are omitted and chemical / mechanical polishing is performed. It was The other conditions were the same as in Example 1. Table 1 also shows the results of the flatness of the comparative example. As can be seen from the results shown in Table 1, in Examples 1 to 3, good flatness can be obtained as compared with the comparative example.

[0033]

According to the present invention, a positive photoresist is applied on an insulating film which will be an interlayer insulating film, and then the photoresist is exposed by utilizing reflection from metal wiring under the insulating film without using a mask. After development, the photoresist on the metal wiring is selectively removed, the insulating film is partially etched in the thickness direction using the resist pattern as a mask, and then chemical / mechanical polishing is performed to planarize the insulating film surface. Since this is done, it is possible to realize global flattening at low cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a relationship between a base reflectance and a resist sensitivity.

FIG. 2 is a process cross-sectional view showing a first embodiment and a first example.

FIG. 3 is a process sectional view showing a second embodiment and a second example.

FIG. 4 Ti in the third embodiment and the third example.
It is a figure which shows the wavelength dependence of the reflectance of N film.

[Explanation of symbols]

 1 Silicon Substrate 2 Base Insulating Film 3 Metal Wiring 4 Insulating Film with High Polishing Rate 5 Insulating Film with Low Polishing Rate 6 Photoresist

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/90 M

Claims (6)

[Claims] 1. A method of manufacturing a semiconductor device, which comprises the following steps (A) to (D) to flatten a surface of an interlayer insulating film on a metal wiring. (A) A step of forming an insulating film, which will be an interlayer insulating film between the metal wiring formed later on the base on which the metal wiring is formed, and (B) a positive photo film on the insulating film. After applying the resist, a lithography process of exposing the photoresist by utilizing reflection from the metal wiring under the insulating film without using a mask and developing it to selectively remove the photoresist on the metal wiring, ( C) a step of etching the insulating film in a part of its thickness direction using the photoresist patterned by the lithography process as a mask; (D) removing the photoresist and then performing chemical / mechanical polishing to perform the insulating film Step of flattening the surface. 2. The insulating film has a two-layer structure, the polishing rate of the upper insulating film is lower than the polishing rate of the lower insulating film with respect to chemical / mechanical polishing, and etching is performed in the step (C). 2. The method for manufacturing a semiconductor device according to claim 1, wherein is an upper insulating film. 3. When forming a metal wiring on a base, an antireflection film for an exposure wavelength for forming a metal wiring resist pattern is formed on the metal film for the metal wiring, and the reflection is performed after the metal wiring is formed. The method for manufacturing a semiconductor device according to claim 1, wherein the prevention film is removed. 4. When a metal wiring is formed on a base, a film having a wavelength dependence of reflectance is formed on the metal film for the metal wiring, and a metal wiring resist pattern is formed in a lithography process. Exposure is performed at a wavelength at which the reflectance of the film becomes small, the film is left on the metal wiring, an insulating film is formed on the metal wiring, a photoresist is applied on the insulating film, and the photoresist is applied. The method of manufacturing a semiconductor device according to claim 1, wherein a wavelength at which the reflectance of the film is increased is used in the step of exposing by utilizing the reflection from the metal wiring. 5. The method of manufacturing a semiconductor device according to claim 4, wherein the film is a TiN film. 6. The N / Ti composition ratio of the TiN film is 1 in molar ratio.
The method for manufacturing a semiconductor device according to claim 5, wherein