JPH0964041A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the coverage of a conductor film in a connecting hole for connecting between conductor layers. SOLUTION: When a connecting hole 9A is opened at an interlayer insulating film covering first layer interconnection 3, the hole 9A3 of the degree reaching a second insulating film 6 by dry etching is formed, a slope is formed at the side of the hole 9A3 by wet etching, further the second insulating film 6 and the first insulating film 4 of the bottom of the hole 9Ac are removed by dry etching to form the hole 9A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for manufacturing a semiconductor integrated circuit device, and more particularly to a technique effectively applied to a method of forming a connection hole in a semiconductor integrated circuit device having a multilayer wiring structure.

[0002]

2. Description of the Related Art A multilayer wiring technique in a semiconductor integrated circuit device is constructed by laminating wiring for an integrated circuit in a thickness direction of a semiconductor substrate with an interlayer insulating film interposed therebetween, and it is possible to freely connect elements on the semiconductor substrate. This is an important technique as a method capable of reducing the signal delay time between elements and improving the element integration density.

The wiring layers in the multi-layer wiring structure are electrically connected to each other through connection holes formed in the interlayer insulating film between the wiring layers. Regarding the method of forming this connection hole, for example, there are the following two conventional techniques.

The first prior art is the US patent (United Sta.
tes Patent) 5180689, which discloses the following method. In this document,
The case where a connection hole is formed in an interlayer insulating film that covers wiring formed on an insulating film on a semiconductor substrate is described.

The interlayer insulating film in this case is formed by plasma CVD.
First insulating film made of silicon dioxide (SiO ₂ ) formed by a CVD method, a second insulating film made of SiO ₂ by a SOG (Spin On Glass) method for planarization, and SiO formed by a plasma CVD method. _A third insulating film made of ₂ is formed by being sequentially stacked from the lower layer.

First, after forming a photoresist pattern on the third insulating film by a photolithography technique so that only the connection hole forming region in the third insulating film is exposed,
For example, an etching solution containing hydrofluoric acid is used to etch away a predetermined depth above the third insulating film exposed from the photoresist pattern.

Then, using the photoresist pattern as it is as an etching mask, the third insulating film, the second insulating film and the first insulating film left by the dry etching method are left.
The insulating film is sequentially removed by etching.

After removing the photoresist pattern, a predetermined conductor film for upper layer wiring is deposited on the semiconductor substrate.

The second conventional technique is disclosed in Japanese Patent Laid-Open No. 59-1.
This is the technique described in Japanese Patent No. 47447, and the following method is disclosed. In this case, the interlayer insulating film is formed by sequentially stacking a first insulating film made of silicon nitride formed by plasma CVD method and a second insulating film made of SiO ₂ formed by sputtering method from the lower layer.

First, after forming a photoresist pattern on the second insulating film by a photolithography technique so as to expose only the connection hole forming region in the second insulating film,
For example, the second insulating film exposed from the photoresist pattern is removed by etching with an etching solution containing hydrofluoric acid. At this time, in this technique, the first insulating film below the second insulating film functions as an etching stopper.

Then, using the photoresist pattern as it is as an etching mask, the first insulating film is removed by etching by a dry etching method, the photoresist pattern is removed, and a predetermined wiring for upper wiring is formed on the semiconductor substrate. Deposit a conductor film.

[0012]

However, the present inventor has found that the above-mentioned first and second conventional techniques have the following problems, respectively.

In the above-mentioned first prior art, there is a problem that the coverage of the conductor film for the upper layer wiring on the inner side surface of the connection hole cannot be said to be sufficient and a disconnection defect is likely to occur at that portion. That is, this is for the following reason, for example.

In order to increase the coverage of the conductor film in the connection hole, the diameter of the upper part of the connection hole of the third insulating film is made larger than the hole diameter of the photoresist pattern so that the upper side surface of the connection hole can be inclined. Good.

However, in the above first prior art,
Since the third insulating film is removed by the wet etching method, if the diameter of the upper portion of the connection hole is increased, the etching amount in the depth direction of the connection hole is also increased, and the etching solution is formed by the SOG method. 2 reaches the insulating film.

Then, the second insulating film is the first insulating film or the third insulating film.
Because the film quality is lower than the insulating film and the etching rate is faster,
As a result of being removed by etching faster than the first insulating film and the third insulating film, the diameter of the connection hole in the second insulating film portion is
The diameter is larger than the diameter of the connection hole in the first insulating film or the third insulating film portion, and the connection hole portion in the second insulating film portion is in a constricted state.

For this reason, in the first prior art described above, a good inclination is formed on the side surface of the connection hole above the third insulation film during the etching removal treatment of the third insulation film for forming the connection hole. However, it is impossible to perform the etching treatment necessary to form a connection hole having a sufficient diameter.

In the second prior art, since the first insulating film that functions as an etching stopper is provided, the problem of the constriction formed in the connection hole as in the first prior art does not occur. However, there is a problem that the photoresist pattern for forming the connection hole is peeled off during the formation of the connection hole. That is, this is for the following reason, for example.

In order to increase the coverage of the conductor film for the upper wiring in the connection hole, it is not effective to increase the diameter of the upper part of the connection hole of the second insulating film of the uppermost layer. It is necessary to reduce the ratio between the diameter of the lower portion and the depth of the vertical connection hole portion formed by dry etching.

However, if the diameter of the opening formed in the photoresist pattern is small, the etching solution enters the interface between the photoresist pattern and the uppermost second insulating film. However, the etching amount in the radial direction of the connection hole is larger.

Therefore, if the etching amount in the depth direction of the uppermost second insulating film is increased during the wet etching process in order to reduce the distance of the connection hole forming portion during the dry etching process, As a result of the large amount of etching in the radial direction of the connection hole, the photoresist pattern peels off.

An object of the present invention is to provide a technique capable of forming a connection hole without causing a constriction in the connection hole connecting the conductor layers.

An object of the present invention is to provide a technique capable of forming a connection hole without peeling a mask pattern for forming the connection hole when forming a connection hole for connecting conductor layers.

An object of the present invention is to provide a technique capable of improving the coverage of a conductor film in a connection hole that connects conductor layers.

The above and other objects and novel features of the present invention will be apparent from the description of the specification and the accompanying drawings.

[0026]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the following steps are performed when a connecting hole is formed in the interlayer insulating film covering the conductor layer so that a part of the conductor layer is exposed. I have.

(A) After depositing a first insulating film covering the conductor layer, a second insulating film having an etching rate different from that of the first insulating film is deposited on the first insulating film, and further, the first insulating film is deposited. A step of forming the interlayer insulating film by sequentially depositing a third insulating film having an etching rate different from that of the second insulating film on the second insulating film.

(B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed.

(C) The third mask exposed from the mask pattern using the mask pattern as an etching mask
A step of forming an upper portion of the connection hole by removing a middle portion of the insulating film or a middle portion of the second insulating film by a dry etching process.

(D) Using the mask pattern as an etching mask, removing the third insulating film on the upper side surface of the connection hole by wet etching so that a slope is formed on the upper side surface of the connection hole. .

(E) The second mask exposed from the mask pattern using the mask pattern as an etching mask
A step of forming a lower portion of the connection hole by removing the insulating film and the first insulating film by a dry etching process to expose a part of the conductor layer.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, a connection hole that exposes a part of the electrode wiring is formed in the interlayer insulating film that covers the electrode wiring provided on the semiconductor substrate. At that time, it has the following steps.

(A) A first insulating film covering the electrode wiring is deposited on the semiconductor substrate, a flat insulating film is deposited on the first insulating film, and then the upper portion of the flat insulating film is removed. The first insulating film portion on the electrode wiring is removed until it is exposed, and then the second insulating film and the third insulating film are sequentially deposited on the remaining flat insulating film and first insulating film. A step of forming an interlayer insulating film.

(B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed.

(C) Using the mask pattern as an etching mask, the third mask exposed from the mask pattern
A step of forming an upper portion of the connection hole by removing a middle portion of the insulating film or a middle portion of the second insulating film by a dry etching process.

(D) Using the mask pattern as an etching mask, removing the third insulating film on the upper side surface of the connection hole by wet etching so that an inclination is formed on the upper side surface of the connection hole. .

(E) The second mask exposed from the mask pattern using the mask pattern as an etching mask
A lower portion of the connection hole is formed by removing the insulating film and the first insulating film by a dry etching process,
A step of exposing a part of the electrode wiring.

Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, a connection hole is formed in the interlayer insulating film covering the electrode wiring provided on the semiconductor substrate so that a part of the electrode wiring is exposed. At that time, it has the following steps.

(A) A first insulating film covering the electrode wiring is deposited on the semiconductor substrate, a flat insulating film is deposited on the first insulating film, and then the upper portion of the flat insulating film is The upper surface of the electrode wiring is removed until it is exposed, and then the second insulating layer is left on the remaining flat insulating film, the first insulating film, and the electrode wiring.
Forming an interlayer insulating film by sequentially depositing an insulating film and the third insulating film.

(B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed.

(C) Using the mask pattern as an etching mask, the third portion exposed from the mask pattern
A step of forming an upper portion of the connection hole by removing a middle portion of the insulating film or a middle portion of the second insulating film by a dry etching process.

(D) Using the mask pattern as an etching mask, a step of removing the third insulating film on the upper side surface of the connection hole by wet etching so that a slope is formed on the upper side surface of the connection hole. .

(E) The second mask exposed from the mask pattern using the mask pattern as an etching mask
A step of forming a lower portion of the connection hole by removing the insulating film by a dry etching process and exposing a part of the first electrode wiring.

Further, in the method for manufacturing a semiconductor integrated circuit device according to the present invention, the thickness of the second insulating film is smaller than the thickness of the first insulating film and the third insulating film.

[0046]

According to the method of manufacturing a semiconductor integrated circuit device of the present invention described above, when the connection hole exposing the conductor layer is formed in the interlayer insulating film, the connection hole is formed to a predetermined depth by dry etching. After that, a predetermined amount of inclination is formed on the side surface of the connection hole formed up to the middle position by a wet etching process, and the remaining insulating film is removed by a dry etching process to form a connection hole in which the conductor layer is exposed. As a result, it becomes possible to perform the etching process with the conditions set by paying attention only to forming a good inclination on the side surface of the upper part of the connection hole during the wet etching process, so that the hole diameter at the upper part of the connection hole is too large. It becomes possible to form a favorable inclination on the side surface thereof. That is, it is possible to form a connection hole having a good inclination in the upper portion without peeling off the mask pattern for forming the connection hole.

Further, when forming a connection hole in which the conductor layer is exposed in the interlayer insulating film, after the connection hole is formed to a predetermined depth by a dry etching process, the side surface of the connection hole formed to an intermediate position is formed. A predetermined amount of inclination is formed by the wet etching process, and the remaining insulating film is removed by the dry etching process to form a connection hole in which the conductor layer is exposed, so that the second dry etching process is performed. Since the upper part of the insulating film is slightly removed by etching, the diameter of the connection hole can be gradually increased.

Further, the second insulating film having a different etching rate from the first insulating film and the third insulating film is provided between the first insulating film and the third insulating film, so that the second insulating film is used in the wet etching process for forming the upper portion of the connection hole. Serves as an etching stopper, and even if there is a low-quality insulating film between the second insulating film and the first insulating film, the insulating film will not be etched. As a result, it is possible to prevent the problem that a part of the insulating film in the connection hole is constricted. That is, it becomes possible to form the connection hole without causing a constriction in the connection hole connecting the conductor layers.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after depositing the flat insulating film on the first insulating film, the flat insulating film is formed until the upper part of the first insulating film is exposed. By removing it, it becomes possible to improve the flatness of the upper surface of the interlayer insulating film.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, after depositing the flat insulating film on the first insulating film, the flat insulating film is removed until the upper surface of the electrode wiring is exposed. As a result, since the first insulating film does not exist on the electrode wiring, it is possible to omit the step of etching and removing the first insulating film in the second dry etching process.

According to the method of manufacturing a semiconductor integrated circuit device of the present invention, for example, when the first insulating film and the third insulating film are made of silicon oxide and the second insulating film is made of silicon nitride,
By suppressing the thickness of the second insulating film having a higher dielectric constant than the first insulating film and the third insulating film from the thickness of the first insulating film and the third insulating film, it is possible to suppress an increase in parasitic capacitance. Is possible.

[0052]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a sectional view of a main part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS.
FIG. 6 is a cross-sectional view of a main part of the semiconductor integrated circuit device during the manufacturing process, and FIG. 6 is a cross-sectional view showing a scanning electron micrograph of a connection hole portion on a semiconductor substrate to show the effect of this embodiment.

As shown in FIG. 1, the semiconductor substrate 1 constituting the semiconductor integrated circuit device of the first embodiment is made of, for example, p-type silicon (Si) single crystal, and its main surface is not shown. , Eg DRAM (Dynamic RAM) and SRAM
A predetermined semiconductor integrated circuit element forming a semiconductor memory circuit such as (Static RAM) or a logic circuit such as a microcomputer is formed.

On the main surface of the semiconductor substrate 1, for example, S
insulating film 2 made of iO ₂ is deposited. On the insulating film 2, for example, aluminum (Al) or Al-Si-
First layer wiring (conductor layer) 3 made of a copper (Cu) alloy or the like is formed.

The first layer wiring 3 is formed by depositing a conductor film made of, for example, Al on the insulating film 2 by a sputtering method or a vapor deposition method and then patterning the conductor film by a photolithography technique. There is.

On the insulating film 2, for example, a thickness of 200
First insulating film 4 made of SiO ₂ or the like having a thickness of about nm to 300 nm
However, for example, plasma CVD (Chemical Vapor Depositio)
n; chemical vapor deposition) method, and the first-layer wiring 3 is covered thereby.

An insulating film (flat insulating film) 5 made of, for example, SiO ₂ is formed on the first insulating film 4. The insulating film 5 is an insulating film provided for flattening,
It is formed thin on the upper surface of the first layer wiring 3 and thick on the first insulating film 4. The insulating film 5 is, for example, SO
It is formed by the G method and is, for example, 400 ° C to 450 ° C.
It is solidified by heat treatment at about ℃.

On the insulating film 5, a second insulating film 6 made of, for example, silicon nitride and having a thickness of about 100 nm is formed by, for example, a plasma CVD method. On the second insulating film 6, for example, a third insulating film 7 made of SiO ₂ and having a thickness of about 300 nm to 600 nm is formed by, for example, the plasma CVD method.

However, the method for forming the first insulating film 4, the second insulating film 6 and the third insulating film 7 is the plasma CVD method.
The method is not limited to the above, and various changes can be made. For example, the low temperature CVD method or the sputtering method may be used.

The reason why the thickness of the second insulating film 6 is smaller than that of the first insulating film 4 and the third insulating film 7 as described above is as follows.

First, since the relative dielectric constant of silicon nitride forming the second insulating film 6 is larger than the relative dielectric constants of the first insulating film 4 and the third insulating film 7, the second insulating film 6 is made too thick. This is because the parasitic capacitance increases if too much is added. Second
In addition, the second insulating film 6 has only to act as an etching stopper in the wet etching process and does not need to be thickened.

At predetermined positions of the first insulating film 4, the insulating film 5, the second insulating film 6 and the third insulating film 7, a connection hole 9A is formed so that a part of the first layer wiring 3 is exposed. The first layer wiring 3 and the second layer wiring (second layer conductor) 10 are electrically connected to each other through the connection hole 9A.

The connection holes 9A are the connection holes 9A1 formed in the first insulating film 4 and the insulating film 5, the connection holes 9A2 formed in the second insulating film 6, and the connection holes formed in the third insulating film 7. It is composed of holes 9A3. In the first embodiment, the diameters of the connection holes 9A1, 9A2, 9A3 are gradually increased in this order. This makes it possible to improve the coverage of the second layer wiring 10 in the connection hole 9A.

The second layer wiring 10 is made of, for example, Al or Al.
It is made of —Si—Cu alloy or the like and is formed similarly to the first layer wiring 3. In addition, the second-layer wiring 10 includes the third insulating film 7
It is covered with the surface protection film 11 formed on the top. The surface protective film 11 is formed by depositing an insulating film made of, for example, SiO ₂ and an insulating film made of, for example, silicon nitride in order from the lower layer.

Next, a method of manufacturing the semiconductor integrated circuit device according to the first embodiment will be described with reference to FIGS. 1 and 2 to 5.

First, from the Si single crystal shown in FIG. 2 on which a predetermined semiconductor integrated circuit element (not shown) forming a semiconductor memory circuit such as DRAM or SRAM or a logic circuit such as a microcomputer is formed. An insulating film 2 made of, for example, SiO ₂ is formed on the main surface of the semiconductor substrate 1 by the CVD method.

Subsequently, a conductor film made of, for example, Al or Al-Si-Cu alloy is deposited on the insulating film 2 by a sputtering method or a vapor deposition method, and then the conductor film is patterned by a photolithography technique. Thus, the first-layer wiring 3 is formed.

After that, a film having a thickness of, for example, 200 is formed on the insulating film 2.
First insulating film 4 made of SiO ₂ or the like having a thickness of about nm to 300 nm
Are deposited by, for example, a plasma CVD method to cover the first layer wiring 3.

Next, for example, SiO 2 is formed on the first insulating film 4.
_The planarizing insulating film 5 made of ₂ is deposited by the SOG method or the like. In the step of depositing the insulating film 5, the insulating film 5
In order to solidify, the heat treatment is performed at, for example, about 400 ° C to 450 ° C. The insulating film 5 is formed thin on the upper surface of the first layer wiring 3 and thick on the first insulating film 4.

Then, a film having a thickness of, for example, 100 is formed on the insulating film 5.
After the second insulating film 6 made of silicon nitride having a thickness of about nm is formed by, for example, the plasma CVD method, the second insulating film 6 is covered with SiO ₂ having a thickness of, for example, about 300 nm to 600 nm.
The third insulating film 7 made of is formed by, for example, the plasma CVD method.

However, the method for forming the first insulating film 4, the second insulating film 6 and the third insulating film 7 is the plasma CVD method.
The method is not limited to the above, and various changes can be made. For example, the low temperature CVD method or the sputtering method may be used.

After that, as shown in FIG. 3, a photoresist pattern (mask pattern) 8 exposing only the connection hole forming region is formed on the third insulating film 7 of the semiconductor substrate 1 by the photolithography technique. Form.

Then, using the photoresist pattern 8 as an etching mask, the semiconductor substrate 1 is subjected to dry etching, for example, to etch away the portion of the third insulating film 7 exposed from the photoresist pattern 8 to remove the third insulating film. A connecting hole 9A3 having a substantially vertical shape is drilled in 7. However, at the time of this etching process, at least the second insulating film 6 is left.

Then, using the photoresist pattern 8 used in the previous step as an etching mask again, the semiconductor substrate 1 is wet-etched with an etching solution containing hydrofluoric acid, for example.

As a result, as shown in FIG. 4, without increasing the diameter of the connection hole 9A3 of the third insulating film 7 too much, the second layer wiring 10 (in the connection hole) is formed on the side surface of the connection hole 9A3. It is possible to form a taper that can improve the coverage (see FIG. 1). This is for the following reason.

That is, in this wet etching process, the depth of the connection hole 9A3 has already been formed to a desired value by the dry etching process described above, and it is not necessary to perform the etching process in the depth direction. When the etching process is performed in the depth direction by the etching process, the etching also progresses in the lateral direction of the connection hole 9A3, and the diameter of the connection hole 9A3 does not become larger than necessary. This is because it is possible to perform the etching process with the conditions set only by forming a good taper on the side surface of the.

Further, in this wet etching process, it is possible to prevent the occurrence of constriction in the portion of the insulating film 5 in the connection hole 9A (see FIG. 1). This is for the following reason.

That is, as the lower layer of the third insulating film 7, for example, the second insulating film 6 made of silicon nitride or the like which is not etched and removed by an etching solution containing hydrofluoric acid.
This is because the insulating film 5 under the second insulating film 6 is not removed by etching during the wet etching process.

Then, as shown in FIG. 5, the second insulating film 6 exposed from the photoresist pattern 8 is subjected to dry etching, for example, using the photoresist pattern 8 used in the previous step as an etching mask again. The insulating film 5 and the first insulating film 4 are removed by etching, a substantially vertical connecting hole 9A2 is formed in the second insulating film 6, and an almost vertical connecting hole 9A1 is formed in the insulating film 5 and the first insulating film 4. Pierce. Then, by this, a connection hole 9A is formed so that a part of the upper surface of the first layer wiring 3 is exposed.

At this time, in the dry etching process, since there is no difference in etching rate between the first insulating film 4, the insulating film 5 formed by the SOG method and the second insulating film 6, the insulation of the connection hole 9A1 is prevented. Narrowing does not occur in the membrane 5 portion.

Since the second insulating film 6 in the connection hole 9A2 is also partially removed by the dry etching process at this time, the hole diameter at that portion is the same as that of the connection hole 9A1 in the lower first insulating film 4. It is larger than the diameter.

Subsequently, the photoresist pattern 8 is removed by ashing treatment or the like, and then, on the semiconductor substrate 1.
For example, a conductor film made of Al or Al-Si-Cu alloy is deposited by a sputtering method or the like, and then the conductor film is patterned by a photolithography technique to form the second layer wiring 10 shown in FIG.

In the first embodiment, since the side surface of the connection hole 9A3 and the upper part of the connection hole 9A2 are tapered, the coverage of the second layer wiring 10 in the connection hole 9A can be greatly improved. It is possible.

FIG. 6 is a photograph of a cross section of a connection hole portion on a semiconductor substrate taken by a scanning electron microscope to show the effect of the first embodiment. FIG. 6 (a) is based on the present invention, and FIG. 6 (b) is based on the first prior art. In the first embodiment, the coverage of the second layer wiring 10 is 50%, and the coverage of the second layer wiring of the conventional technique is 24%.
It is about twice as much.

Thereafter, as shown in FIG. 1, an insulating film made of, for example, SiO ₂ and an insulating film made of, for example, silicon nitride are deposited on the semiconductor substrate 1 in order from the lower layer by the CVD method or the like to protect the surface. The film 11 is formed.

As described above, according to the first embodiment, the following effects can be obtained.

(1). Dry etching is performed when the connection hole 9A exposing the first layer wiring 3 is formed in the interlayer insulating film composed of the first insulating film 4, the second insulating film 6, the third insulating film 7 and the like. After the depth of the connection hole 9A3 is set by the process, the inclination of the side surface of the connection hole 9A3 is set by the wet etching process, and further, the connection holes 9A2, 9A1 in which the first layer wiring 3 is exposed are formed by the dry etching process. As a result, during the wet etching process, the connection hole 9A3
Since it is possible to perform the etching treatment with the conditions set only by forming a good inclination on the side surface of the connection hole, it is necessary to form a good inclination on the side surface without making the diameter of the connection hole 9A3 too large. Is possible.

(2). Dry etching is performed when the connection hole 9A exposing the first layer wiring 3 is formed in the interlayer insulating film including the first insulating film 4, the second insulating film 6 and the third insulating film 7. After the depth of the connection hole 9A3 is set by the process, the inclination of the side surface of the connection hole 9A3 is set by the wet etching process, and further, the connection holes 9A2, 9A1 in which the first layer wiring 3 is exposed are formed by the dry etching process. This allows the second insulating film 6 to be removed during the second dry etching process.
Since the upper part of the connection is slightly etched away, the connection hole 9A1
It is possible to gradually increase the hole diameter of ~ 9A3 in this order.

(3). When the connection hole 9A3 is formed by providing the second insulating film 6 made of silicon nitride or the like between the first insulating film 4 and the third insulating film 7 made of SiO ₂ or the like. The second insulating film 6 serves as an etching stopper during the wet etching process described above, and even if the insulating film 5 formed by the SOG method or the like exists between the second insulating film 6 and the first insulating film 4, the insulating film is etched. Since it does not occur, it is possible to prevent the problem that the insulating film 5 portion in the connection hole 9A is constricted due to over-etching.

(4). By the above (1), (2) or (3), the coverage of the second layer wiring 10 in the connection hole 9A is significantly improved (about twice as much as the first prior art). It becomes possible. Therefore, the second layer wiring 10 in the connection hole 9A
Since it is possible to greatly reduce the connection failure and the disconnection failure, it is possible to significantly improve the yield and reliability of the semiconductor integrated circuit device.

(Embodiment 2) FIGS. 7 to 13 are cross-sectional views of essential parts in a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

In the second embodiment, as shown in FIG. 7, first, the insulating film 5 is deposited on the first insulating film 4 by the SOG method or the like so that its upper surface is substantially flat, and then, for example, etched. Back method or CMP (Chemical Mechanica)
By removing the upper portion of the insulating film 5 to the extent that the convex upper surface of the lower first insulating film 4 is exposed by the l polishing method or the like, the upper surface of the semiconductor substrate 1 is made flat as shown in FIG.

The subsequent steps are the same as in the first embodiment.
That is, as shown in FIG. 9, on this semiconductor substrate 1,
For example, after the second insulating film 6 made of silicon nitride having a thickness of about 100 nm is formed by, for example, the plasma CVD method, the second insulating film 6 has a thickness of, for example, 300 nm to 60 nm.
The third insulating film 7 made of SiO ₂ and having a thickness of about 0 nm is formed by, for example, the plasma CVD method.

Here, the reason why the thickness of the second insulating film 6 is smaller than the thickness of the first insulating film 4 and the third insulating film 7 is the same as in the first embodiment.

After that, a photoresist pattern 8 is formed by photolithography on the third insulating film 7 of the semiconductor substrate 1 so that only the connection hole forming region is exposed.

Then, using the photoresist pattern 8 as an etching mask, the semiconductor substrate 1 is subjected to, for example, dry etching to remove the third insulating film 7 portion exposed from the photoresist pattern 8 by etching, as shown in FIG. As described above, a substantially vertical connection hole 9A3 is formed in the third insulating film 7. However, at the time of this etching process, at least the second insulating film 6 is left.

Then, using the photoresist pattern 8 used in the previous step as an etching mask again, the semiconductor substrate 1 is wet-etched with an etching solution containing hydrofluoric acid, for example.

As a result, as shown in FIG. 11, without increasing the diameter of the connection hole 9A3 of the third insulating film 7 too much,
On the side surface of the connection hole 9A3, the second
It is possible to form a taper that can improve the coverage of the layer wiring 10 (see FIG. 1). The reason for this is the same as in the first embodiment.

Further, in the second embodiment, since the insulating film 5 is scarcely left on the first insulating film 4 on the first layer wiring 3, the insulating film in the connection hole 9A is not formed in this wet etching process. There will be no constriction in the area of 5. Further, even if the insulating film 5 is left on the first insulating film 4 on the first layer wiring 3, no constriction occurs in the portion of the insulating film 5 in the connection hole for the same reason as in the first embodiment. .

Then, as shown in FIG. 12, by using the photoresist pattern 8 used in the previous step as an etching mask again, for example, a dry etching process is performed to expose the second insulating film 6 exposed from the photoresist pattern 8. The portion of the first insulating film 4 is removed by etching, a substantially vertical connecting hole 9A2 is formed in the second insulating film 6, and a substantially vertical connecting hole 9A1 is formed in the first insulating film 4. Then, by this, a connection hole 9A is formed so that a part of the upper surface of the first layer wiring 3 is exposed.

At this time, even in the second embodiment, even if the insulating film 5 formed by the SOG method is left between the first insulating film 4 and the second insulating film 6, etching is performed in the dry etching process. Since there is no difference in speed, no constriction occurs in the insulating film 5 portion of the connection hole 9A1.

Since the second insulating film 6 in the connection hole 9A2 is also partially removed by the dry etching process at this time, the hole diameter at that portion is the same as that of the connection hole 9A1 in the lower first insulating film 4. It is larger than the diameter.

Subsequently, the photoresist pattern 8 is removed by ashing treatment or the like, and then, on the semiconductor substrate 1.
For example, after depositing a conductor film made of Al or Al-Si-Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique to form the second-layer wiring 10 as shown in FIG. .

In the second embodiment, since the side surface of the connection hole 9A3 and the upper portion of the connection hole 9A2 are tapered, the coverage of the second layer wiring 10 in the connection hole 9A is the same as in the first embodiment. It is possible to greatly improve.

Then, for example, SiO 2 is formed on the semiconductor substrate 1.
_The surface protective film 11 is formed by sequentially depositing an insulating film made of _{2 and the} like and an insulating film made of silicon nitride and the like from the lower layers by the CVD method or the like.

As described above, in the second embodiment, in addition to the effect obtained in the first embodiment, the flatness of the semiconductor substrate 1 is improved by flattening the upper surface of the insulating film 5 after the insulating film 5 is deposited. It becomes possible to improve. Therefore, it is possible to reduce wire disconnection defects and the like, so that it is possible to further improve the yield and reliability of the semiconductor integrated circuit device.

(Embodiment 3) FIGS. 14 to 20 are cross-sectional views of essential parts in a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

In the third embodiment, as shown in FIG. 14, first, the insulating film 5 is deposited on the first insulating film 4 by the SOG method or the like so that its upper surface is substantially flat, and then, for example, etched. By removing the upper portion of the insulating film 5 to the extent that the upper surface of the lower first-layer wiring 3 is exposed by the back method or the CMP method, as shown in FIG.
Flatten the top surface of. That is, in Example 3, neither the first insulating film 4 nor the insulating film 5 was deposited on the first layer wiring 3.

The subsequent steps are the same as in the first and second embodiments. That is, as shown in FIG.
A second insulating film 6 made of, for example, silicon nitride having a thickness of about 100 nm is formed thereon by, for example, a plasma CVD method, and then the second insulating film 6 is provided with a thickness of, for example, 300 nm to
The third insulating film 7 made of SiO ₂ and having a thickness of about 600 nm is formed by, for example, the plasma CVD method.

In the third embodiment, the reason why the thickness of the second insulating film 6 is smaller than the thickness of the first insulating film 4 and the third insulating film 7 is the same as in the first embodiment.

After that, a photoresist pattern 8 is formed on the third insulating film 7 of the semiconductor substrate 1 by the photolithography technique so that only the connection hole forming region is exposed.

Then, by using the photoresist pattern 8 as an etching mask, the semiconductor substrate 1 is subjected to, for example, dry etching to remove the third insulating film 7 portion exposed from the photoresist pattern 8 by etching, as shown in FIG. As described above, a substantially vertical connection hole 9A3 is formed in the third insulating film 7. However, at the time of this etching process, at least the second insulating film 6 is left.

Then, using the photoresist pattern 8 used in the previous step as an etching mask again, a wet etching process is performed on the semiconductor substrate 1 with an etching solution containing hydrofluoric acid, for example.

As a result, as shown in FIG. 18, without increasing the diameter of the connection hole 9A3 of the third insulating film 7 too much,
On the side surface of the connection hole 9A3, the second
It is possible to form a taper that can improve the coverage of the layer wiring 10 (see FIG. 1). The reason for this is the same as in the first embodiment.

In the third embodiment, since the insulating film 5 is not left on the first-layer wiring 3, the wet etching process may cause a constriction in the insulating film 5 in the connection hole. Absent.

Then, as shown in FIG. 19, using the photoresist pattern 8 used in the previous step as an etching mask again, for example, a dry etching process is performed to expose the second insulating film 6 and the second insulating film 6 exposed from the photoresist pattern 8. The first insulating film 4 portion is removed by etching, and a substantially vertical connection hole 9A2 is formed in the second insulating film 6. Then, by this, a connection hole 9A is formed so that a part of the upper surface of the first layer wiring 3 is exposed.

By the dry etching process at this time, the second insulating film 6 in the connection hole 9A2 is also partially removed by etching. In the third embodiment, the second
Since the first insulating film and the insulating film formed by the SOG method or the like are not present in the lower layer of the insulating film 6, it is possible to omit the dry etching step for that portion.

Subsequently, the photoresist pattern 8 is removed by ashing treatment or the like, and then, on the semiconductor substrate 1.
After depositing a conductor film made of, for example, Al or Al-Si-Cu alloy by a sputtering method or the like, the conductor film is patterned by a photolithography technique to form a second layer wiring 10 as shown in FIG. .

Also in the third embodiment, since the side surface of the connection hole 9A3 and the upper portion of the connection hole 9A2 are tapered, the coverage of the second layer wiring 10 in the connection hole 9A is the same as in the first embodiment. It is possible to greatly improve.

After that, for example, SiO 2 is formed on the semiconductor substrate 1.
_The surface protective film 11 is formed by sequentially depositing an insulating film made of _{2 and the} like and an insulating film made of silicon nitride and the like from the lower layers by the CVD method or the like.

As described above, in the third embodiment, the following effects can be obtained.

(1). Connection hole 9A in which the first layer wiring 3 is exposed in the interlayer insulating film composed of the second insulating film 6 and the third insulating film 7 etc.
At the time of drilling, the depth of the connection hole 9A3 is set by dry etching, then the inclination of the side surface of the connection hole 9A3 is set by wet etching, and the first layer wiring 3 is exposed by dry etching. By drilling the connection hole 9A2, it is possible to perform the etching process with the condition set by paying attention only to forming a good slope on the side surface of the connection hole 9A3 in the wet etching process. It is possible to form a good inclination on the side surface without making it too large.

(2). Connection hole 9A for exposing the first-layer wiring 3 in the interlayer insulating film composed of the second insulating film 6 and the third insulating film 7 etc.
At the time of drilling, the depth of the connection hole 9A3 is set by dry etching, then the inclination of the side surface of the connection hole 9A3 is set by wet etching, and the first layer wiring 3 is exposed by dry etching. Since the upper part of the second insulating film 6 is slightly etched and removed in the second dry etching process by forming the connection holes 9A2, the diameters of the connection holes 9A2, 9A3 can be gradually increased in this order. It will be possible.

(3). By removing the first insulating film 4 on the first wiring layer 3 and the insulating film formed by the SOG method by etching back or the like, a second time for forming the connection hole 9A is obtained. It is possible to reduce the step of etching and removing the first insulating film 4 and the insulating film by the SOG method in the dry etching process.

(4). The first insulating film 4 on the first wiring layer 3 and the insulating film formed by the SOG method are removed by etching back or the like, so that wet etching is performed at the time of forming the connection hole 9A3. It is possible to prevent the problem that the insulating film portion in the connection hole 9A due to the SOG method is constricted due to excessive processing.

(5). According to the above (1), (2), (3) or (4),
It is possible to significantly improve the coverage of the second layer wiring 10 in the connection hole 9A (about twice the coverage of the first conventional technique). Therefore, the connection failure and disconnection failure of the second layer wiring 10 in the connection hole 9A can be significantly reduced, so that the yield and reliability of the semiconductor integrated circuit device can be significantly improved.

(Embodiment 4) FIG. 21 is a sectional view showing the principal part of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIGS.
FIG. 22 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG.

As shown in FIG. 21, the semiconductor substrate 1 constituting the semiconductor integrated circuit device of the fourth embodiment is made of, for example, p-type Si single crystal, and the n well 12n and the p well 12p are formed on the upper part thereof. Has been formed. n well 12n
For example, phosphorus or arsenic (As), which is an n-type impurity, is introduced therein. Boron, which is a p-type impurity, is introduced into the p-well 12p.

On the main surface of the semiconductor substrate 1, for example, SiO 2
_A field insulating film 13 made of ₂ is formed. In the element formation region surrounded by the field insulating film 13,
The p-well 12p has, for example, an n-channel MOS / FE
A T (hereinafter referred to as nMOS) 14n is formed.

The nMOS 14n is a pair of semiconductor regions (conductor layers) 14n1 and 14n formed on the semiconductor substrate 1.
2 and the gate insulating film 14n formed on the semiconductor substrate 1
3 and a gate electrode 14n4 formed on the gate insulating film 14n3.

In the semiconductor regions 14n1 and 14n2, for example, n-type impurity phosphorus or As is introduced. The gate insulating film 14n3 is made of SiO ₂ , for example. The gate electrode 14n4 is made of, for example, low resistance polysilicon.

On the other hand, in the element formation region surrounded by the field insulating film 13, the n-well 12n has, for example, a p-channel type MOS.FET (hereinafter referred to as nMOS) 14
p is formed.

The pMOS 14p is composed of a pair of semiconductor regions (not shown) formed on the semiconductor substrate 1, a gate insulating film 14p1 formed on the semiconductor substrate 1, and a gate formed on the gate insulating film 14p1. Electrode (conductor layer) 14
p2.

For example, p-type impurity boron is introduced into the semiconductor region. The gate insulating film 14p1 is made of SiO ₂ , for example. The gate electrode 14p2 is made of, for example, low resistance polysilicon.

A channel stopper 15 formed by introducing, for example, p-type impurity boron is formed above the p well 12p below the field insulating film 13.

A thickness of, for example, 10 is formed on the semiconductor substrate 1.
First insulating film 4a made of SiO ₂ having a thickness of about 0 nm to 200 nm
Are deposited by the CVD method or the like. First insulating film 4a
A second insulating film 6a made of, for example, Si ₃ N ₄ having a thickness of about 50 nm is deposited on the top by, for example, the CVD method. On the second insulating film 6a, for example, a thickness of 300 nm-60
The third insulating film 7a made of SiO ₂ and having a thickness of about 0 nm is deposited by, for example, the CVD method.

However, the method of depositing the first insulating film 4a, the second insulating film 6a, and the third insulating film 7a is not limited to the CVD method, and various modifications can be made. Is also good.

At predetermined positions of the first insulating film 4a, the second insulating film 6a and the third insulating film 7a, the semiconductor region 14n1 of the nMOS 14n and the gate electrode 14 of the pMOS 14p are formed.
Connection holes 9B and 9C are formed so that a predetermined region of p2 is exposed. Then, through the connection holes 9B and 9C, the first layer wiring 3, the semiconductor region 14n1 and the gate electrode 1 are formed.
4p2 is electrically connected, and the semiconductor region 14n1 and the gate electrode 14p2 are electrically connected through the first layer wiring 3.

The connection holes 9B and 9C are formed in the first insulating film 4a, the connection holes 9B1 and 9C1 are formed in the second insulating film 6a, and the connection holes 9B2 and 9C2 are formed in the third insulating film 7a. And connecting holes 9B3 and 9C3. In the fourth embodiment, the diameters of the connection holes 9B1-9B3, 9C1-9C3 gradually increase in this order. This makes it possible to improve the coverage of the first layer wiring 3 in the connection holes 9B and 9C.

The first layer wiring 3 is made of, for example, Al or A.
It is formed by depositing a conductor film made of 1-Si-Cu alloy or the like on the third insulating film 7a by a sputtering method, an evaporation method or the like, and then patterning the conductor film by a photolithography technique.

On the third insulating film 7a, a first insulating film 4b made of, for example, SiO ₂ and having a thickness of about 200 nm to 300 nm is deposited by, for example, the plasma CVD method, whereby the first layer wiring is formed. 3 is coated.

An insulating film 5 made of, for example, SiO ₂ is formed on the first insulating film 4. The insulating film 5 is an insulating film provided for flattening, and is formed thin on the upper surface of the first layer wiring 3 and thick on the first insulating film 4. The insulating film 5 is formed by, for example, the SOG method, and is solidified by a heat treatment at about 400 ° C. to 450 ° C., for example.

On the insulating film 5, a second insulating film 6b made of, for example, Si ₃ N _{4 having} a thickness of about 100 nm is formed by, for example, the plasma CVD method. On the second insulating film 6b, for example, a third insulating film 7b made of SiO ₂ and having a thickness of about 300 nm to 600 nm is formed by, for example, a plasma CVD method.

However, the method for forming the first insulating film 4b, the second insulating film 6b, and the third insulating film 7b described above is not limited to the plasma CVD method, and various modifications can be made. It may be formed by a sputtering method.

First insulating film 4b, insulating film 5, second insulating film 6
b and a third insulating film 7b are provided at predetermined positions with a connection hole 9A so that a part of the first layer wiring 3 is exposed. Through this connection hole 9b, the first layer wiring 3 and the second layer 3 are formed. The wiring 10 is electrically connected.

The connection hole 9A includes a connection hole 9A1 formed in the first insulating film 4b and the insulating film 5, a connection hole 9A2 formed in the second insulating film 6b, and a connection hole formed in the third insulating film 7. It is composed of holes 9A3. Then, the fourth embodiment
In, the diameters of the connection holes 9A1, 9A2, 9A3 are gradually increased in this order. As a result, the connection hole 9A
It is possible to improve the coverage of the second layer wiring 10 inside.

The second layer wiring 10 is made of, for example, Al or Al.
It is made of —Si—Cu alloy or the like and is formed similarly to the first layer wiring 3. In addition, the second-layer wiring 10 includes the third insulating film 7
It is covered with the surface protection film 11 formed on the top. The surface protection film 11 is formed by sequentially depositing an insulating film made of, for example, SiO ₂ and an insulating film made of, for example, Si ₃ N ₄ from the lower layer.

Next, a method of manufacturing the semiconductor integrated circuit device according to the fourth embodiment will be described with reference to FIGS. 21 and 22 to 27.

First, as shown in FIG. 22, for example, p-type S
An n-well 12n and a p-well 12p are formed on the semiconductor substrate 1 made of i single crystal according to a normal well forming method.
To form

Subsequently, for example, boron, which is a p-type impurity for forming a channel stopper, is introduced into the end portion of the p well 12p by an ion implantation method, and then the field insulating film 13 is formed in the element isolation region on the main surface of the semiconductor substrate 1. LOCOS (Lo
It is formed by the cal oxidization of silicon) method. By the heat treatment at this time, the channel stopper 15 is simultaneously formed on the p well 12p.

After that, the gate insulating films 14n3 and 14p1 are formed on the semiconductor substrate 1 in the element formation region surrounded by the field insulating film 13 by a thermal oxidation method or the like.

Then, a conductor film made of, for example, low resistance polysilicon is deposited on the field insulating film 13 and the gate insulating films 14n3 and 14p1 by the CVD method or the like, and then the conductor film is patterned by the photolithography technique. , Gate electrodes 14n4, 14p2
To form

Subsequently, after forming a photoresist pattern (not shown) on the semiconductor substrate 1 so that only the nMOS formation region is exposed, using the photoresist pattern and the gate electrode 14n4 as a mask, for example, an n-type impurity is used. Phosphorus or As is added to the p-well 14p of the semiconductor substrate 1.
By introducing into the upper portion, a pair of semiconductor regions 14n1 and 14n2 are formed on both sides of the gate electrode 14n4 in a self-aligned manner to form an nMOS 14n.

Similarly, after forming a photoresist pattern (not shown) on the semiconductor substrate 1 so that only the pMOS forming region is exposed, the photoresist pattern and the gate electrode 14p2 are used as a mask, for example, n.
By introducing a boron-type impurity into the upper portion of the n-well 14n of the semiconductor substrate 1, a pair of semiconductor regions (not shown) are formed on both sides of the gate electrode 14p2 in a self-aligned manner.
The MOS 14p is formed.

Then, on the semiconductor substrate 1, for example, a layer having a thickness of 1 is formed.
First insulating film 4 made of SiO ₂ having a thickness of about 00 nm to 200 nm
After a is deposited by the CVD method, the second insulating film 6a made of, for example, silicon nitride and having a thickness of about 50 nm
Is deposited by the CVD method or the like, and the third insulating film 7a made of SiO ₂ and having a thickness of about 300 nm to 600 nm is further deposited on the upper surface thereof by the CVD method or the like.

Then, a photoresist pattern 8a is formed on the third insulating film 7a so that only the connection hole forming region is exposed.
Are formed by a photolithography technique.

Then, as shown in FIG. 23, using the photoresist pattern 8a as an etching mask, for example, a dry etching process is applied to the semiconductor substrate 1, and the third insulating film 7a portion exposed from the photoresist pattern 8a is removed by etching. By doing so, substantially vertical connection holes 9B3 and 9C3 are formed in the third insulating film 7a. However,
At the time of this etching process, at least the second insulating film 6a is left.

Then, using the photoresist pattern 8a used in the previous step as an etching mask again, the semiconductor substrate 1 is wet-etched with an etching solution containing hydrofluoric acid, for example.

As a result, as shown in FIG. 24, the diameter of the connection holes 9B3, 9C3 of the third insulating film 7a is not increased too much, and the first side portion of the connection holes 9B3, 9C3 in the connection holes 9B3, 9C3 is formed. It is possible to form a taper that can improve the coverage of the layer wiring 3 (see FIG. 21). The reason is the same as in the first embodiment.

Then, as shown in FIG. 25, using the photoresist pattern 8a used in the previous step as an etching mask again, for example, a dry etching process is performed to expose the second insulating film 6a and the second insulating film 6a exposed from the photoresist pattern 8a. The first insulating film 4a is removed by etching, and the connection holes 9B2 and 9C2 which are substantially vertical to the second insulating film 6a are formed.
And a connection hole 9B having a shape substantially vertical to the first insulating film 4a.
Drill 1,9C1. As a result, the nMOS1
4n semiconductor region 14n1 and connection holes 9B, 9 such that part of gate electrode 14p2 of pMOS 14p is exposed
Form C.

Since the second insulating film 6a of the connection holes 9B2 and 9C2 is also partially removed by the dry etching process at this time, the hole diameter at that portion is smaller than that of the lower first insulating film 4a.
The diameter is larger than the diameter of the connection holes 9B1 and 9C1 of a.

Then, after removing the photoresist pattern 8a by ashing or the like, a conductor film made of, for example, Al or Al--Si--Cu alloy is deposited on the semiconductor substrate 1 by a sputtering method or a vapor deposition method. By patterning the conductor film by photolithography, as shown in FIG.
The layer wiring 3 is formed.

Here, in the fourth embodiment, the connection hole 9
Since the taper is formed on the side surfaces of B3, 9C3 and the upper portions of the connection holes 9B2, 9C2, the first holes in the connection holes 9B, 9C are formed.
It is possible to significantly improve the coverage of the layer wiring 3.

Thereafter, as shown in FIG. 27, for example, SiO 2 having a thickness of about 200 nm to 300 nm is formed on the third insulating film 7a.
The first insulating film 4b made of ₂ etc. is formed, for example, by plasma CVD
The first-layer wiring 3 is covered by being deposited by the method.

Then, for example, Si is formed on the first insulating film 4b.
The planarizing insulating film 5 made of O ₂ is deposited by the SOG method or the like. In the step of depositing the insulating film 5, heat treatment at, for example, about 400 ° C. to 450 ° C. is performed in order to solidify the insulating film 5. The insulating film 5 is formed thin on the upper surface of the first-layer wiring 3 and thick on the first insulating film 4b.

Then, a film having a thickness of, for example, 100 is formed on the insulating film 5.
After the second insulating film 6b made of Si ₃ N _{4 having} a thickness of about nm is formed by, for example, the plasma CVD method, the SiO 2 having a thickness of, for example, about 300 nm to 600 nm is formed on the second insulating film 6b.
The third insulating film 7b made of ₂ is formed by, for example, the plasma CVD method.

However, the method of forming the first insulating film 4b, the second insulating film 6b, and the third insulating film 7b described above is not limited to the plasma CVD method, and various modifications can be made. It may be formed by a sputtering method.

Also in the fourth embodiment, the second insulating film 6 is used.
The reason why the thicknesses of a and 6b are smaller than those of the first insulating films 4a and 4b and the third insulating films 7a and 7b is the same as in the first embodiment.

After that, the first insulating film 4b, the insulating film 5 and the second insulating film 4b
In the insulating film 6b and the third insulating film 7b, the connection hole 9A shown in FIG. 21 in which a part of the upper surface of the first layer wiring 3 is exposed is formed in the same manner as in the first embodiment.

Subsequently, a conductor film made of, for example, Al or Al--Si--Cu alloy is deposited on the semiconductor substrate 1 by a sputtering method or a vapor deposition method, and then the conductor film is patterned by a photolithography technique. The second layer wiring 10 is formed.

In the fourth embodiment, since the side surface of the connection hole 9A3 and the upper portion of the connection hole 9A2 are tapered, the coverage of the second layer wiring 10 in the connection hole 9A can be greatly improved. It is possible.

Then, as shown in FIG. 21, on the semiconductor substrate 1, an insulating film made of, for example, SiO ₂ and Si and
_The surface protection film 11 is formed by sequentially depositing an insulating film made of ₃ N ₄ or the like from the lower layer by a CVD method or the like.

As described above, in the fourth embodiment, the following effects can be obtained in addition to the effects obtained in the first embodiment.

That is, in the fourth embodiment, the first layer in the connection hole 9B connecting the first layer wiring 3 and the semiconductor region 14n1 and the connection hole 9C connecting the first layer wiring 3 and the gate electrode 14p2 is formed. The coverage of the wiring 3 can also be improved.

Therefore, the first layer wiring 3 in the connection holes 9B and 9C and the second layer wiring 1 in the connection hole 9A.
Since it is possible to reduce connection failure and disconnection failure of 0, it is possible to further improve the yield and reliability of the semiconductor integrated circuit device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned first to fourth embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, the material forming the interlayer insulating film is not limited to the constituent materials of Examples 1 to 4 described above, and various changes can be made. The third insulating film may be wet-etchable. The second insulating film may not be etched by the wet etching. For example, the first
The insulating film and the third insulating film may be SiO ₂ , the second insulating film may be alumina or polyimide, the first insulating film may be silicon nitride, the second insulating film may be alumina or polyimide, and the third insulating film may be SiO _2. Also good. Also, the third
S having an insulating film containing at least one of boron and phosphorus
It may be an insulating film made of iO _2.

In the first to fourth embodiments, the case where the interlayer insulating film is composed of four layers of insulating films has been described, but the present invention is not limited to this, and various modifications are possible. May be composed of four or more layers of insulating films. In this case, when the uppermost insulating film is wet-etched, the second insulating film serving as an etching stopper may be present below the uppermost insulating film.

In addition, in the above-mentioned first to fourth embodiments, the case where the wiring layer has two layers has been described, but the present invention is not limited to this, and various modifications are possible. For example, even if the wiring layer has two or more layers. good.

Further, although the case where the present invention is applied to the semiconductor integrated circuit device having the MOS.FET has been described in the fourth embodiment, the present invention is not limited to this and various applications are possible, for example, a semiconductor having a bipolar transistor. It is also possible to apply to an integrated circuit device or a semiconductor integrated circuit device having another element such as a diode or a resistance element.

[0182]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, when a connection hole in which the conductor layer is exposed is formed in the interlayer insulating film, a dry etching process is performed up to a predetermined depth of the connection hole. After formation, a predetermined amount of inclination is formed on the side surface of the connection hole formed up to the middle position by wet etching, and the remaining insulating film is removed by dry etching to form a connection hole where the conductor layer is exposed. By drilling, it becomes possible to perform the etching process with the conditions set by paying attention only to forming a good inclination on the side surface of the upper part of the connection hole during the wet etching process. It is possible to form a good slope on the side surface without overdoing. That is, it is possible to form a connection hole having a good inclination in the upper portion without peeling off the mask pattern for forming the connection hole.

(2). When forming a connection hole in which the conductor layer is exposed in the interlayer insulating film, after the connection hole is formed to a predetermined depth by dry etching, the connection hole formed up to the middle position is formed. A predetermined amount of inclination is formed on the side surface by the wet etching process, and the remaining insulating film is removed by the dry etching process to form a connection hole exposing the conductor layer, so that the second dry etching process is performed. Since the upper part of the second insulating film is slightly removed by etching, the diameter of the connection hole can be gradually increased.

(3). Between the first insulating film and the third insulating film,
By providing the second insulating film having an etching rate different from these, the second insulating film serves as an etching stopper during the wet etching process for forming the upper portion of the connection hole, and the second insulating film serves as an etching stopper between the second insulating film and the first insulating film. Even if there is an insulating film of low film quality, it will not be etched, so it is possible to prevent the problem that a part of the insulating film inside the connection hole becomes constricted due to over-etching. Is possible. That is, it becomes possible to form the connection hole without causing a constriction in the connection hole connecting the conductor layers.

(4). By the above (1), (2) or (3), it is possible to significantly improve the coverage of the conductor film in the connection hole. Therefore, it is possible to significantly reduce connection failure and disconnection failure of the conductor film in the connection hole.
It is possible to greatly improve the yield and reliability of the semiconductor integrated circuit device.

(5) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, after depositing the flat insulating film on the first insulating film, the flat insulating film is exposed at the upper part of the first insulating film. It is possible to improve the flatness of the upper surface of the interlayer insulating film by removing it until the process. Therefore, it is possible to reduce disconnection failure of the wiring on the interlayer insulating film, so that the yield and reliability of the semiconductor integrated circuit device can be improved.

(6) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, after depositing the flat insulating film on the first insulating film, the flat insulating film is formed until the upper surface of the electrode wiring is exposed. By removing it, the first insulating film does not exist on the electrode wiring, so that it is possible to omit the step of etching and removing the first insulating film in the second dry etching process.

(7). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, when the first insulating film and the third insulating film are made of silicon oxide and the second insulating film is made of silicon nitride, the first insulating film is formed. By making the thickness of the second insulating film having a higher dielectric constant than the film and the third insulating film smaller than the thickness of the first insulating film and the third insulating film, it is possible to suppress an increase in parasitic capacitance. Become.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor integrated circuit device that is an embodiment of the present invention.

2 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step thereof;

3 is a main-portion cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during the manufacturing process following that of FIG. 2;

FIG. 4 is a cross-sectional view of essential parts in the manufacturing process of the semiconductor integrated circuit device of FIG. 1 subsequent to FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 1 during a manufacturing step following that of FIG. 4;

6 (a) and 6 (b) are cross-sectional views copying a scanning electron micrograph of a connection hole in the present invention and the prior art, respectively.

FIG. 7 is a cross-sectional view of essential parts in a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

9 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 8;

10 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 9;

11 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 10;

FIG. 12 is a fragmentary cross-sectional view during a manufacturing step of the semiconductor integrated circuit device, following FIG. 11;

FIG. 13 is a main-portion cross-sectional view of the semiconductor integrated circuit device during the manufacturing process thereof, which is subsequent to FIG. 12;

FIG. 14 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device which is another embodiment of the present invention.

FIG. 15 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 14;

16 is a cross-sectional view of essential parts in the process of manufacturing a semiconductor integrated circuit device, following FIG.

FIG. 17 is a main-portion cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 16;

FIG. 18 is a fragmentary cross-sectional view during a manufacturing step of the semiconductor integrated circuit device, following FIG. 17;

19 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 18;

20 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 19;

FIG. 21 is a cross-sectional view of essential parts of a semiconductor integrated circuit device which is an embodiment of the present invention.

22 is a cross-sectional view of essential parts in the process of manufacturing the semiconductor integrated circuit device of FIG.

23 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 20 during a manufacturing step following that of FIG. 22;

24 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 20 during a manufacturing step following that of FIG. 23;

25 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 20 during a manufacturing step following that of FIG. 24;

26 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 20 during a manufacturing step following that of FIG. 25;

27 is a fragmentary cross-sectional view of the semiconductor integrated circuit device of FIG. 20 during a manufacturing step following that of FIG. 26;

[Explanation of symbols]

1 Semiconductor Substrate 2 Insulating Film 3 First Layer Wiring (Conductor Layer) 4 First Insulating Film 5 Insulating Film (Flatness Insulating Film) 6 Second Insulating Film 7 Third Insulating Film 8 and 8a Photoresist Pattern (Mask Pattern) 9A , 9A1 to 9A3, 9B, 9B1 to 9B3, 9C, 9C
1 to 9 C3 connection hole 10 second layer wiring (conductor layer) 11 surface protection film 12n n well 12p p well 13 field insulating film 14n n channel type MOS / FET 14n1, 14n2 semiconductor region (conductor layer) 14n3 gate insulating film 14n4 gate Electrode 14p p-channel type MOS / FET 14p1 gate insulating film 14p2 gate electrode (conductor layer) 15 channel stopper

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Osamu Otani 5-22-1, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd. (72) Masamichi Komuro 5-chome, Kamimizuhoncho, Kodaira-shi, Tokyo 22-1 No. 1 in Hitachi Microcomputer System Co., Ltd. (72) Inventor Masanobu Hijimura 5-22-1 No. 22, Kamimizuhonmachi, Kodaira-shi, Tokyo Inside Hitachi Microcomputer System Co., Ltd.

Claims (8)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps when a connection hole is formed in an interlayer insulating film covering a conductor layer so that a part of the conductor layer is exposed. Method. (A) after depositing a first insulating film covering the conductor layer,
A second insulating film having an etching rate different from that of the first insulating film is deposited on the first insulating film, and a third insulating film having an etching rate different from that of the second insulating film is sequentially formed on the second insulating film. Forming the interlayer insulating film by depositing. (B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed. (C) With the mask pattern as an etching mask,
A step of forming an upper part of the connection hole by removing a middle part of the third insulating film or a middle part of the second insulating film exposed from the mask pattern by a dry etching process. (D) Using the mask pattern as an etching mask,
A step of removing the third insulating film on the upper side surface of the connection hole by wet etching so that the upper side surface of the connection hole is inclined. (E) With the mask pattern as an etching mask,
A step of forming a lower portion of the connection hole by removing the second insulating film and the first insulating film exposed from the mask pattern by a dry etching process to expose a part of the conductor layer. 2. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductor layer is an electrode wiring or a predetermined semiconductor region formed on a semiconductor substrate. . 3. An interlayer insulating film covering an electrode wiring provided on a semiconductor substrate is provided with the following steps when forming a connection hole such that a part of the electrode wiring is exposed. Method for manufacturing semiconductor integrated circuit device. (A) First for covering the electrode wiring on the semiconductor substrate
After depositing an insulating film, a flat insulating film is deposited on the first insulating film, and a second insulating film having an etching rate different from that of the first insulating film is deposited on the flat insulating film. A step of forming the interlayer insulating film on the second insulating film by sequentially depositing a third insulating film having an etching rate different from that of the second insulating film. (B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed. (C) With the mask pattern as an etching mask,
A step of forming an upper part of the connection hole by removing a middle part of the third insulating film or a middle part of the second insulating film exposed from the mask pattern by a dry etching process. (D) Using the mask pattern as an etching mask,
A step of removing the third insulating film on the upper side surface of the connection hole by wet etching so that the upper side surface of the connection hole is inclined. (E) With the mask pattern as an etching mask,
The second insulating film, the flat insulating film, and the first insulating film exposed from the mask pattern are removed by dry etching to form a lower portion of the connection hole and expose a part of the electrode wiring. Process. 4. The method according to claim 1, further comprising the step of forming a connection hole that exposes a part of the electrode wiring in an interlayer insulating film covering the electrode wiring provided on the semiconductor substrate. Method for manufacturing semiconductor integrated circuit device. (A) First for covering the electrode wiring on the semiconductor substrate
After depositing an insulating film, depositing a flat insulating film on the first insulating film, and removing the upper portion of the flat insulating film until the first insulating film portion on the electrode wiring is exposed, Forming the interlayer insulating film by sequentially depositing the second insulating film and the third insulating film on the formed flat insulating film and first insulating film. (B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed. (C) With the mask pattern as an etching mask,
A step of forming an upper part of the connection hole by removing a middle part of the third insulating film or a middle part of the second insulating film exposed from the mask pattern by a dry etching process. (D) Using the mask pattern as an etching mask,
A step of removing the third insulating film on the upper side surface of the connection hole by wet etching so that the upper side surface of the connection hole is inclined. (E) With the mask pattern as an etching mask,
Removing the second insulating film and the first insulating film exposed from the mask pattern by a dry etching process to form a lower portion of the connection hole and expose a part of the electrode wiring. 5. An interlayer insulating film covering an electrode wiring provided on a semiconductor substrate is provided with the following steps when forming a connection hole such that a part of the electrode wiring is exposed. Method for manufacturing semiconductor integrated circuit device. (A) First for covering the electrode wiring on the semiconductor substrate
After depositing an insulating film, depositing a flat insulating film on the first insulating film, and removing the upper portion of the flat insulating film until the upper surface of the electrode wiring is exposed, the remaining flat insulating film Forming the interlayer insulating film by sequentially depositing the second insulating film and the third insulating film on the film, the first insulating film, and the electrode wiring. (B) A step of forming a mask pattern on the third insulating film so that the formation region of the connection hole is exposed. (C) With the mask pattern as an etching mask,
A step of forming an upper part of the connection hole by removing a middle part of the third insulating film or a middle part of the second insulating film exposed from the mask pattern by a dry etching process. (D) Using the mask pattern as an etching mask,
A step of removing the third insulating film on the upper side surface of the connection hole by wet etching so that the upper side surface of the connection hole is inclined. (E) With the mask pattern as an etching mask,
A step of forming a lower part of the connection hole by removing the second insulating film exposed from the mask pattern by a dry etching process, and exposing a part of the first electrode wiring. 6. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein a thickness of the second insulating film is smaller than a thickness of the first insulating film and the third insulating film. And a semiconductor integrated circuit device manufacturing method. 7. The method for manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film, the second insulating film, and the third insulating film are chemically vapor-deposited. A method of manufacturing a semiconductor integrated circuit device, characterized by being formed by a method. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the first insulating film and the third insulating film are silicon oxide films, and the second insulating film. Is a silicon nitride film, and the etching solution used for the wet etching treatment contains hydrofluoric acid.