JPH0963269A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage collectively selecting all word lines with an N channel MOS transistor and performing wafer burn-in by providing an NMOS circuit and a wafer burn-in circuit in a word line driver. SOLUTION: When potential VBI for wafer burn-in is supplied to the word line driver 203, an N channel transistor T4 in a wafer burn-in potential supply circuit 102 is made an on state, and the N channel transistor T3 in an NMOS circuit 101 is made an off state. Further, an N channel MOS transistor T2 connected with a selected potential supply line FXO in the drain is made the off state also. Then, the potential VBI is supplied to respective wafer burn-in supply circuits 102 answering to the word lines WL0-WLn, and the potential VBI is supplied to all word lines WL0-WLn simultaneously. Thus, the potential VBI is supplied to all word lines WL0-WLn simultaneously, and a wafer burn-in processing time is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which connects a selection potential to an word line by an N-channel type MOS transistor.

[0002]

2. Description of the Related Art Usually, screening is performed to detect an initial failure of a semiconductor memory device. Screening methods include internal visual inspection, application of thermal and mechanical stress,
There are high-temperature operation, high-temperature storage, wafer burn-in performed in a wafer state or a chip state before packaging, and the like, and the screening method most suitable for the semiconductor memory device to be screened is selected in consideration of screening effectiveness and cost. In particular, wafer burn-in can be used for screening for checking initial malfunction. In the wafer burn-in, a device chip to be checked is subjected to an operation environment (high temperature, high humidity, high potential, etc.) that is stricter than the rating, and an operation test is performed for a fixed time. In the screening of the semiconductor memory device, in order to confirm the formation state of the gate-source oxide film of the memory cell,
Wafer burn-in that supplies a high potential to the word line is effective. For example, in order to reduce the on-resistance of the selection transistor of the memory cell, a relatively high selection potential for boosting the power supply voltage is applied to the word line of DRAM, SRAM and the like. Therefore, the wafer burn-in of the select terminal of the memory cell is performed separately from the wafer burn-in of the peripheral circuit that uses the power supply voltage as it is.

[0003]

The wafer burn-in targeting the select terminal of the memory cell can improve the processing efficiency if the word lines can be collectively selected. Specifically, when the word line is driven by a CMOS inverter, the source of the selection potential of the word line and the source of the wafer burn-in potential are CM.
It is possible to increase the processing efficiency by connecting all the word lines together as a power source of the OS inverter and selecting all the word lines at the time of wafer burn-in to perform the wafer burn-in at the same time. On the other hand, when the supply of the selection potential to the word line is controlled by the ON / OFF operation of the N-channel MOS transistor, the N-channel MOS transistor that can supply the selection potential to the word line and the non-selection to the word line. N-channel MO that can supply electric potential
Since it is different from the S transistor, each N channel type M
It is necessary to control the OS transistor.
No means has been found for easily selecting and selecting all word lines at once like an inverter. In such a wafer burn-in targeting the select terminal of the memory cell of the semiconductor memory device, the word line must be sequentially accessed to perform the wafer burn-in. In this case, it takes an enormous amount of time to detect the initial defect related to the select terminal of the memory cell. Therefore, the present inventors have found the necessity of means for simultaneously selecting all the word lines at the same time using N-channel MOS transistors to perform wafer burn-in.

An object of the present invention is to provide a technique for improving wafer burn-in processing efficiency in a semiconductor memory device which supplies a selection potential to a word line by an N-channel MOS transistor.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, in a semiconductor memory device having a memory cell array in which select terminals of a plurality of memory cells arranged in a matrix are connected to word lines and data terminals are connected to bit lines, an address signal is decoded. An address decoder for forming a word line selection signal,
A first N-channel transistor for supplying a selection potential to the word line according to the word line selection signal of the address decoder, and a word line GND according to the word line selection signal.
A word line driver including a second N-channel type transistor for setting the level, a third N-channel type transistor for supplying a wafer burn-in potential to the word line, and a selection potential supply circuit, and a wafer burn-in potential are supplied. As a result, a semiconductor memory device is provided with a wafer burn-in circuit that supplies a wafer burn-in potential to all word lines. In a semiconductor memory device including a memory cell array in which select terminals of a plurality of memory cells arranged in a matrix are connected to sub word lines of a hierarchical word line system and data terminals are connected to bit lines, a first address A first address decoder for decoding the signal to form a main word line selection signal, and driving the main word line to a selection level according to the main word line selection signal, decoding the second address signal to select the sub word line A second address decoder for forming a signal, a first N-channel type transistor for supplying a selection potential to a sub-word line according to a main word line selection signal, and a second N-channel type transistor for setting a word line to a GND level according to the main word line selection signal The N-channel type transistor and the sub word line are supplied with the wafer burn-in potential. A word line driver and a third N-channel transistor to constitute a semiconductor memory device and a wafer burn-in circuit for supplying a wafer burn-in for potential at the wafer burn-in mode to full word line. The selection potential of the sub-word line supplied by the second address decoder is supplied to the drain of the first N-channel type transistor and can be set to the selection potential of the sub-word line. The memory cell may be a dynamic memory cell including a selection transistor and a storage capacitor.

[Action]

According to the above means, the word line is set to the selection level by driving the word line driver according to the supplied address signal. A common wafer burn-in potential supply path is provided for all word line drivers, and this path is connected to a word line. By supplying the wafer burn-in potential to this supply path, all the word lines are provided as the wafer burn-in potential supply path. Thus, the wafer burn-in can be simultaneously performed on the selection terminals of all the memory cells. According to another means, in a hierarchical word type semiconductor memory device,
The sub-word line is set to the selection level by being selected by the second address signal among the sub-word lines which can be driven by the sub-word line driver designated by the main word line selected by the first address signal. A common wafer burn-in potential supply path is provided via a sub-word line driver for all sub-word lines. By the wafer burn-in mode signal, the supply path for the wafer burn-in potential is set to all the sub-word lines. At that time, the wafer burn-in potential is supplied to this supply path, so that the wafer burn-in potential is supplied to the selection terminals of all the memory cells. To be done. Thus, the wafer burn-in can be simultaneously performed on the selection terminals of all the memory cells. The selection potential of the sub-word line is the first N-channel MOS
It is supplied to the sub-word line through the drain-source of the transistor and can be used as the selection potential of the sub-word line. As the memory cells, one-transistor type, three-transistor type, and four-transistor type dynamic memory cells can be applied.

[0009]

FIG. 2 shows a semiconductor memory device DR of the present invention.
An example block diagram of an AM (Dynamic Random Access Memory) is shown. According to the figure, the DRAM 2
00 is a memory cell array 20 in which, for example, one-transistor dynamic memory cells are arranged in a matrix.
1, a row address decoder 202 that decodes the row address signal XADR to select a word line, and a word line driver 20 that supplies a selection potential to the selected word line.
3, a Y decoder 204 that decodes the column address signal YADR to select a column selection signal for designating a data line, a column selection switch circuit 205 that selects a data line using the selected column selection signal, Sense amplifier 206 that amplifies the potential supplied to the data line from the memory cell selected by the word line and the data line
And a control circuit 207 which supplies various control signals necessary for memory access. Read / write data is input / output to / from the column switch circuit via the input / output terminals Di / Do. The word line driver 20
3 is composed of an NMOS circuit, for example, a wafer burn-in potential V from the outside via a bonding pad BP.
BI is made available. Although not particularly limited, the bonding pad BP is provided for wafer burn-in and is provided on the semiconductor chip, but is not connected to the external lead of the semiconductor memory device when the semiconductor chip is packaged. In other words, the bonding pad BP can be used for burn-in or screening in a wafer state or a chip state. The semiconductor memory device 200 has a row address strobe signal RAS * (hereinafter, * means a row enable signal) and a column address strobe signal CAS *.
And a control circuit 20 to which the write instruction signal WE * and the like are supplied
The memory access operation is executed in accordance with various control signals output by 7.

FIG. 1 is a circuit diagram showing an example of the word line driver 203. According to the figure, the word line driver 203 has a complementary row address decode signal X0, supplied as a complementary signal from the row address decoder 202.
NM provided for each complementary signal of X0B, to Xn, XnB
It is composed of an OS circuit 101 and a wafer burn-in potential supply circuit 102 capable of inputting a wafer burn-in potential VBI. In the same figure, a circuit corresponding to the word line WL0 is shown. The NMOS circuit 101 is composed of, for example, three N-channel type MOS transistors T1 to T3. The N-channel MOS transistor T1 is
The row address decode signal X0 is received at the drain,
The source output is adjusted by the boost potential VPP supplied to the gate. N-channel MOS transistor T
Reference numeral 2 is connected to the selection potential supply line FX0 by a drain, is on / off controlled according to the adjusted row address decode signal X0 supplied to the gate, and the source is connected to the word line WL0. A driver that supplies a selection potential in synchronization with the row address strobe signal RAS * is connected to the selection potential supply line FX0. The N-channel type transistor T3 receives at its gate the output of an AND circuit having two inputs of the row address decode signal X0B and the inverted potential of the wafer burn-in potential VBI, its source is connected to GND, and its drain is connected to the word line WL0. To be done. The word line WL0 is a row address decode signal X
0 is set to high level, and low address decode signal X0
A selection potential is supplied to the word line WL0 which is selected when B is set to the low level and corresponds to the row address decode signal. Wafer burn-in potential supply circuit 1
Reference numeral 02 is composed of, for example, an N-channel type transistor T4, and a wafer burn-in potential VBI can be commonly supplied to the drain and gate, and the source is the word line WL0
Connected to. In the normal memory access operation, 0 V is applied to the drain of the transistor T4, and the wafer burn-in potential VBI is supplied through the bonding pad BP at the time of wafer burn-in. At the time of wafer burn-in, the output of the AND circuit is fixed to the low level, so that the wafer burn-in potential VBI supplied to the word line WL0 is prevented from being pulled to GND. The portions corresponding to the other word lines WLn have the same circuit configuration.

FIG. 3A shows a time chart of the word line selecting operation in the word line driver 203. According to (A) of the same figure, the selection of the word line WLn is performed by synchronizing with the low edge of the row address strobe signal RAS *, the row address decode signal signal Xn is set to the high level state, and the transistor T2 is turned on. This is performed by supplying the selection potential from the potential supply line FXn. At that time, the transistors T3 and T4 are turned off. By completing the access operation to the selected memory cell, the row address strobe signal RA
S * is set to high level, and the decode signal X
n is set to the low level, and the supply of the selection potential to the selected word line WLn is stopped. Unselected word line W
In Ln, the transistor T2 is turned off and the transistor T3 is turned on, so that the word line WLn is connected to GND.

Next, the wafer burn-in will be described. First, a semiconductor wafer in which element wirings capable of forming a plurality of semiconductor chips are completed is prepared by a known semiconductor integrated circuit device manufacturing technique. Next, power is supplied for wafer burn-in, that is, burn-in to the semiconductor chips formed from the wafer. Although not particularly limited, the power supply for wafer burn-in to the semiconductor chip is performed by contacting the wafer burn-in pad electrode of the semiconductor chip with a contact needle similar to a wafer prober. In order to enable efficient wafer burn-in, instead of supplying power for burn-in to one semiconductor chip at a time, by using a power supply body with an increased number of contact needles, a plurality of power supplies can be connected at one time. It is also possible to supply power to the semiconductor chip for burn-in.

FIG. 3B shows a time chart at the time of wafer burn-in in the word line driver 203. According to FIG. 6B, the wafer burn-in potential VBI is supplied from the bonding pad BP.
By supplying the wafer burn-in potential VBI, the transistor T4 is turned on and, conversely, the transistor T3 is turned off. During wafer burn-in,
Since the word line WLn is in the non-selected state, the transistor T2 is also in the off state. Wafer burn-in potential VBI is supplied to each wafer burn-in potential supply circuit 102 corresponding to word line WLn and all word lines WL0.
To WLn simultaneously for wafer burn-in potential VBI
Can be supplied. Therefore, the wafer burn-in processing time is reduced.

FIG. 4 is a block diagram showing another example of the DRAM which is the semiconductor memory device of the present invention. According to the figure, the DRAM 400 has a main word line driver 401 instead of the word line driver 203 of the DRAM 200.
A hierarchical word method using the sub word line driver 402 is applied. The hierarchical word method is a method of dividing a word line into a main word line and a sub-word line and arranging them so as to avoid a high-density arrangement partially in order to ease the high-density arrangement of word lines. The DRAM 400 serves as a decoder for the row address signal XADR, and selects, for example, the main word line by using the upper bits of the row address signal X.
An M decoder 404 and an XS decoder 405 that selects a sub word line using the lower bits of the row address signal are provided. A plurality of sub-word line drivers 402 are provided corresponding to the respective main word lines, and the sub-word line driver 402 has a selection potential VPP according to the decode signal supplied from the XS decoder 405 and the main word lines.
Is provided to the sub word line. The sub-word line driver 402 is a switch circuit that controls the sub-word line to the selection potential VPP or GND by the switching operation of the N-channel type MOS transistor. Further, a bonding pad BP for supplying the wafer burn-in potential VBI to the sub word line via the sub word line driver 402 is provided. DR above
The AM 400 has a memory access mode and a wafer burn-in mode, and the wafer burn-in mode signal BI is supplied to the main word line driver 401 and the FX driver 406 via the bonding pad BP2. When the wafer burn-in mode is selected (when the wafer burn-in mode signal BI is at a high level), all the word lines are deselected in the main word line driver 401, and the FX driver 406 selects the sub word line. The supply of the selection potential is stopped.

FIG. 5 shows the main word line driver 4 described above.
01, FX driver 406, and sub word line driver 40
2 shows an example of the connection configuration with 2. The main word line driver 401 has a NAND circuit 501 which receives an inversion signal of the wafer burn-in mode signal BI and a main word line decode signal XM0 supplied from the X decoder as two inputs.
And a CMOS whose gate receives the output of the NAND circuit 501
Inverter A and C using the main word line decode signal XM0B having a complementary relationship between the inputs of the CMOS inverter A and the main word line decode signal XM0
The MOS inverter B is used as a basic unit. The output of the CMOS inverter A is the main word line MWL.
0, and the output of the CMOS inverter B is complementary to the main word line MWL0.
0B. A complementary signal of one main word line MWL0 is formed by one basic unit, and a plurality of corresponding sub word line drivers 402 can be selected. The FX driver 406 includes a NAND circuit 502 having two inputs of the inverted signal of the wafer burn-in mode signal BI and a sub word line decode signal XS0 supplied from the XS decoder, and a CMOS inverter C receiving the output of the NAND circuit 502 at its gate. Composed. When the wafer burn-in mode signal is in the enabled state (high level), the output of the CMOS inverter C is connected to GND. In the figure, a circuit corresponding to the main word line MWL0 is shown, but circuits corresponding to other main word lines MWLn are similarly configured.

The sub-word line driver 402 is constructed, for example, with a circuit consisting of four N-channel type MOS transistors N1 to N4 corresponding to one sub-word line SWLi as a basic unit. The N-channel MOS transistor N1 receives the main word line MWL0 which is the output of the main word line driver at the drain, and adjusts the source output by the potential VPP supplied to the gate. N
The channel-type MOS transistor N2 is connected to the selection potential supply line FX0, which is the output of the FX driver 406, by the drain, is on / off controlled according to the adjusted main word line MWL0 supplied to the gate, and the source is the subword. Connected to line SWL0. N channel type M
The OS transistor N3 receives the main word line MWL0B at its gate, its source is connected to GND, and its drain is connected to the sub word line SWL0. Sub word line SW
L0 is selected by setting the main word line decode signal XM0 to the high level and the sub word line decode signal XS0 to the high level, and supplying the selection potential VPP. N
The channel-type MOS transistor N4 can be supplied with the wafer burn-in potential VBI in common to its drain and gate, and its source is connected to the sub-word line SWL0.
In a normal memory access operation, the transistor N
Normally, 0V is applied to the drain of No. 4, and at the time of wafer burn-in, the wafer burn-in potential VBI is supplied via the bonding pad BP. The wafer burn-in mode signal BI is supplied to all the main word line drivers 401 and all the FX drivers 406, and the wafer burn-in potential VBI is all the sub word lines SWL0 to SWLi.
Made available.

According to the above embodiment, the following operational effects can be obtained. (1) In the DRAM 200, the wafer burn-in is the wafer burn-in potential VB from the bonding pad BP.
By supplying I. Wafer burn-in potential VBI is simultaneously supplied to all word lines WL0 to WLn via word line driver 203. Therefore, the wafer burn-in in which the wafer burn-in potential VBI is simultaneously supplied to all the gates of all the memory cells becomes possible. (2) In the DRAM 400, the wafer burn-in enables the wafer burn-in mode signal BI,
Bonding pad BP to wafer burn-in potential V
This is done by supplying BI. By supplying the wafer burn-in mode signal BI in the enabled state, all the sub-word lines SWL0 to SWLi are connected to the bonding pad BP. By supplying the wafer burn-in potential VBI to the bonding pad BP, the wafer burn-in potential VBI is supplied to all the sub word lines SWL0 to SWLi via the sub word line driver 402.
Is supplied to. Therefore, all sub word lines SWL0 to SW
A potential for wafer burn-in can be supplied to Li. Therefore, the wafer burn-in in which the wafer burn-in potential VBI is simultaneously supplied to all the gates of all the memory cells becomes possible.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, in this embodiment, the wafer burn-in potential VBI of the hierarchical word system is supplied to all the sub word lines SWL0 to SWLn via the sub word line driver 402, but it is supplied to all the sub potential lines FX0 to FXi.
Wafer burn-in potential VBI can be supplied to all sub-word lines SWL0 to SWLi.

In the above description, the invention made by the present inventor is the field of application which is the background of the invention.
The case of application to M is shown, but EPROM and EEPRO
It is also possible to apply to M. The present invention can also be applied to a word shunt type semiconductor memory device.

The present invention can be applied to all semiconductor memory devices including a word line driver composed of at least an NMOS circuit.

[0022]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the wafer burn-in potential can be simultaneously supplied to all the word lines via the word line driver to improve the wafer burn-in efficiency for the gates of the memory cells. In the hierarchical word system semiconductor integrated circuit, the wafer burn-in mode signal is used to supply the wafer burn-in potential to all the sub-word lines at the same time through the sub-word line driver, thereby enhancing the wafer burn-in efficiency for the gates of the memory cells. be able to.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an example of a word line driver included in a semiconductor memory circuit of the present invention.

FIG. 2 is a block diagram showing an example of a semiconductor memory device of the present invention.

FIG. 3 is a time chart of a word line selection operation and wafer burn-in in the word line driver of this embodiment.

FIG. 4 is a block diagram of an example of another semiconductor memory device of the present invention.

FIG. 5 is a circuit diagram showing an example of a main word line driver and a sub word line driver included in another semiconductor memory circuit of the present invention.

[Explanation of symbols]

 101 NMOS circuit 102 Wafer burn-in potential supply circuit 203 Word line driver WLn Word line Xn, XnB Complementary decode signal

Front page continued (72) Inventor Yukie Hide Suzuki 2326 Imai, Ome, Tokyo Inside Hitachi Device Development Center (72) Inventor Shunichi Sukegawa 2350 Miura-mura Kihara, Inashiki-gun, Ibaraki Japan Texas Instruments Co., Ltd. 72) Inventor, Yoshitaka Saito, 2350 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture, Japan Nippon Textile Instruments Co., Ltd.

Claims (4)

[Claims] 1. A semiconductor memory device comprising a memory cell array in which select terminals of a plurality of memory cells arranged in a matrix are connected to word lines and data terminals are connected to bit lines, and an address signal is decoded. An address decoder for forming a word line selection signal, a first N-channel type transistor for supplying a selection potential to the word line according to the word line selection signal of the address decoder, and a word line to the GND level according to the word line selection signal. A second N-channel transistor, a third N-channel transistor for supplying a word line with a wafer burn-in potential, and a word line driver including a selection potential supply circuit; and a wafer burn-in potential. To supply the wafer burn-in potential to all word lines. The semiconductor memory device characterized by and a circuit. 2. A semiconductor memory device comprising a memory cell array in which select terminals of a plurality of memory cells arranged in a matrix are connected to sub word lines of a hierarchical word line system and data terminals are connected to bit lines. A first address decoder for decoding a first address signal to form a main word line selection signal, a second address decoder for decoding a second address signal to form a sub word line selection signal, and a main word A first N-channel type transistor for supplying a selection potential to the sub-word line according to the line selection signal, a second N-channel type transistor for setting the word line to the GND level according to the main word line selection signal, and a wafer burn-in for the sub-word line. Third N for supplying electric potential
A semiconductor memory device comprising: a word line driver including a channel type transistor; and a wafer burn-in circuit that supplies a wafer burn-in potential to all sub-word lines in a wafer burn-in mode. 3. The semiconductor memory device according to claim 2, wherein the selection potential of the sub-word line selection signal is supplied to the drain of the first N-channel type transistor to be the selection potential of the sub-word line. . 4. The semiconductor memory device according to claim 1, wherein the memory cell is a dynamic memory cell composed of a selection transistor and a storage capacitor.