JP2001118398A - Semiconductor memory and its test method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable to perform sufficiently screening of a memory cell, between word lines, between bit lines being adjacent each other, and of peripheral circuits, while shortening largely a screening time. SOLUTION: A row decoder 18 receiving a row address pre-decoding signal and generating a row address decoding signal is connected to a word line driver 15 driving plural word lines WL. A control circuit 19 for starting plural word lines to which a row address pre-decoding signal and plural word lines starting test mode switching signal AWL are inputted is connected to the row decoder 18. A word line drive signal generating circuit 22 to which a word line drive timing control signal WD and a row address pre-decoding signal are inputted is connected between a row pre-decoder 20 and the word line driver 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device comprising a dynamic random access memory (DRAM), and more particularly to a semiconductor memory device capable of efficiently screening for initial failures and a method of inspecting the same.

[0002]

2. Description of the Related Art In recent years, with the increase in density and integration of semiconductor memory devices, the time required for testing the devices and screening for initial failures such as burn-in have been increasing. On the other hand, with the spread of system LSIs and the advancement of functions and the complexity of functions, how to reduce or reduce the screening time and reduce the manufacturing cost has become a major issue. Above all, some studies have been made on the burn-in screening process to reduce or reduce the number of steps without reducing the quality of the product.

[0003] Burn-in screening in a semiconductor memory device such as a DRAM is performed under high temperature and high voltage conditions.
In general, a method of performing an ordinary read operation or a write operation on a device to apply stress to the device, particularly to a memory cell, to screen for an initial failure. That is, an address signal from the outside,
Each signal such as a data signal and a clock signal is input, a plurality of word lines are selected one by one, and stress is sequentially applied to the selected word lines.

[0004] One of the methods studied or adopted to increase the efficiency of stress application and to reduce the time is to start up all word lines in a storage device at the same time and to increase all memory cells. There is a method of applying stress all at once.

According to this method, all the word lines are simultaneously activated within one cycle regardless of an external address, and all the memory cell arrays are connected to the above-described method of sequentially applying a stress to one word line. At the same time, stress is applied. This method is attracting attention as a method to reduce the screening time, and is considered not only for burn-in inspection in the package state until now, but also for high-voltage stress tests at the time of burn-in or wafer inspection at the wafer level, etc. Has been made.

[0006]

However, the above-described conventional semiconductor memory device and its inspection method have the following problems.

That is, the first method in which stress is applied to each word line by sequentially selecting word lines while changing addresses as in the normal operation has a problem that the screening time becomes enormous. Needless to say.

On the other hand, the second method of applying stress by driving all the word lines at a time reduces the screening time, but (1) at the time of normal operation, one of the many word lines. By driving only the word line, the second method can be performed even though a stress is applied between one driven word line and another non-driven word line adjacent to the one word line. In, as a result of driving all the word lines, no stress is applied to the word lines adjacent to each other, so that the screening effect is reduced. (2) In the method of driving all the word lines at once, since the same read operation and write operation as in the normal operation are not performed, it is not sufficient to apply stress to bit lines adjacent to each other and further to the sense amplifier circuit. Not
Screening is also incomplete in this regard.

As described above, it is difficult to guarantee sufficient quality for a semiconductor memory device by the second method of starting up word lines all together.

The present invention solves the above-mentioned conventional problems and makes it possible to sufficiently screen memory cells, adjacent word lines, bit lines, and peripheral circuits while greatly reducing the screening time. The purpose is to:

[0011]

In order to achieve the above object, the present invention provides a semiconductor memory device in which a voltage stress equal to or higher than that in a normal operation is applied during a test such as a stress test.

More specifically, the first semiconductor memory device according to the present invention comprises a plurality of word lines and a number of bit line pairs crossing each other, and a matrix at each intersection of the many word lines and a number of bit line pairs. A memory cell array composed of a large number of memory cells provided in a shape, a word line driving circuit for receiving a row address signal and selectively driving a large number of word lines based on the received row address signal, and a large number of bit line pairs A sense amplifier circuit that amplifies the potential difference between each bit line pair, receives a column address signal, selects one of a number of bit line pairs based on the received column address signal, and A column selection circuit for inputting / outputting data, and a sensor for setting the amplitude of the amplified voltage for amplifying the potential difference between the bit line pair in the test mode to be larger than the amplitude of the amplified voltage in the normal mode. And a amplifier driving circuit.

According to the first semiconductor memory device, there is provided a sense amplifier driving circuit for setting the amplitude of the amplified voltage for amplifying the potential difference between the pair of bit lines in the test mode to be larger than the amplitude of the amplified voltage in the normal mode. Because
For example, in the case of a configuration using a boosted sense ground system to reduce the sub-threshold leakage current, a larger voltage stress can be applied to the bit lines and the memory cells in the test mode than in the normal mode. Efficiency can be improved.

In the first semiconductor memory device, in a test mode, a word line drive circuit selects word lines so that a plurality of word lines can be driven in a predetermined number of word lines and a plurality of word lines in one operation cycle. A test word line selecting means for selecting a plurality of bit line pairs in a plurality of bit line pairs in one operation cycle in a test mode, and inputting and outputting data to and from the selected plurality of bit line pairs. It is preferable to further include a bit line selecting means for inspection. In this case, since the word lines adjacent to each of the plurality of word lines driven in the test mode are not driven, the same stress between the selected word line and the unselected word line as in the normal operation is applied. Works. Further, since a plurality of word lines are selected in one cycle of a write cycle or a read cycle, the time required for screening all word lines can be reduced. Similarly,
The screening time for the previous bit line can also be reduced.

According to a second semiconductor memory device of the present invention, there are provided a plurality of word lines and a plurality of bit line pairs crossing each other,
A memory cell array consisting of a large number of memory cells provided in a matrix at each intersection of a large number of word lines and a large number of bit lines, a row address signal, and a large number of word lines based on the received row address signal. A word line driving circuit for selectively driving, a sense amplifier circuit provided for each of a large number of bit line pairs to amplify a potential difference between each bit line pair, a column address signal, and a large number based on the received column address signal And a column selection circuit for selecting one of the bit line pairs and inputting / outputting data to / from the outside. In a test mode, a word line drive circuit is provided for each of a predetermined number of Inspection word line selecting means for selecting a word line so that a plurality of word lines can be driven in an operation cycle;
Test bit line selecting means for selecting a plurality of bit line pairs in a plurality of bit line pairs in one operation cycle during the test mode, and inputting / outputting data to / from the selected plurality of bit line pairs; A data scramble circuit for inverting the value of write data input from the outside based on a row address signal or a column address signal.

According to the second semiconductor memory device, a word line adjacent to each of the plurality of word lines driven in the test mode is not driven, so that a selected word line and an unselected word line are provided between them. The same stress acts as during normal operation. Further, since a plurality of word lines are selected in one cycle of a write cycle or a read cycle, the time required for screening all word lines can be reduced. Further, since a data scramble circuit for inverting the value of write data input from the outside based on a row address signal or a column address signal is provided, a plurality of memory cells arranged in rows and columns are provided. Needless to say, 1 or 0 of the physical data can be written in all of them, and a stripe pattern in which the physical data value is inverted in units of rows or columns, and one memory cell and another adjacent to the one memory cell. A checker pattern in which the physical data values of the memory cells differ from each other can be easily generated, and voltage stress can be applied by various stress application patterns.

According to a third semiconductor memory device of the present invention, there are provided a plurality of word lines and a plurality of bit line pairs crossing each other,
A memory cell array consisting of a large number of memory cells provided in a matrix at each intersection of a large number of word lines and a large number of bit lines, a row address signal, and a large number of word lines based on the received row address signal. A word line driving circuit for selectively driving, a sense amplifier circuit provided for each of a large number of bit line pairs to amplify a potential difference between each bit line pair, a column address signal, and a large number based on the received column address signal And a column selection circuit for selecting one of the bit line pairs and inputting / outputting data to / from the outside. In a test mode, a word line drive circuit is provided for each of a predetermined number of Test word line selection means for selecting a word line so that a plurality of word lines can be driven in an operation cycle, a large number of word lines including spare word lines, and a memory cell array including spare word lines. A plurality of word lines which have spare memory cells driven by word lines and are driven by the test word line selecting means in the test mode include spare word lines selected every predetermined number. ing.

According to the third semiconductor memory device, many word lines include spare word lines, and the memory cell array has spare memory cells driven by the spare word lines. In addition, the inspection word line selecting means may include a word line and a spare word line so that the word line driving circuit can drive a plurality of word lines at predetermined intervals among a large number of word lines and in one operation cycle. For this selection, the screening test efficiency can be improved even in a configuration having spare memory cells, so-called redundant memory cells.

In the third semiconductor memory device, in the test mode, a plurality of bit line pairs among a plurality of bit line pairs are selected in one operation cycle, and data is input to the selected plurality of bit line pairs. It is preferable to further include a test bit line selecting means for performing output. In this way, the screening time for a plurality of bit lines can be reduced.

A fourth semiconductor memory device according to the present invention includes a plurality of memory cell arrays each having a large number of memory cells provided in a matrix at each intersection of a large number of word lines and a large number of bit lines. A plurality of shared gate circuits provided so that a bit line pair can be shared between mutually adjacent memory cell arrays of the plurality of memory cell arrays, and a shared gate circuit between mutually adjacent memory cell arrays. A sense amplifier circuit for amplifying a potential difference between each bit line pair, a word line driving circuit for receiving a row address signal and selectively driving a number of word lines based on the received row address signal, and a column address signal And selects one of a number of bit line pairs based on the received column address signal to input / output data to / from an external column. And road, the test mode, by activating the shared gate circuit, and a shared gate control means for simultaneously writing operation for each bit line pair between the memory cell array adjacent to each other.

According to the fourth semiconductor memory device, a plurality of memory cell arrays, a plurality of shared gate circuits sharing a bit line pair between mutually adjacent memory cell arrays, and a shared gate circuit are activated in a test mode. Shared gate control means for simultaneously performing a write operation on each bit line of the memory cell arrays adjacent to each other, wherein the shared gate control means controls the shared gate circuit with respect to the adjacent memory cell arrays in the normal mode. By disconnecting any one of the bit line pairs and activating the shared gate circuit in the inspection mode, write operations to the bit line pairs of the adjacent memory cell arrays are performed simultaneously. Therefore, even in a configuration including a plurality of memory cell arrays, the inspection time for screening the plurality of memory cell arrays can be reduced.

In the fourth semiconductor memory device, in the test mode, the word line drive circuit selects word lines so that a plurality of word lines can be driven at predetermined intervals and in one operation cycle for a large number of word lines. A test word line selecting means for selecting a plurality of bit line pairs in a plurality of bit line pairs in one operation cycle in a test mode, and inputting and outputting data to and from the selected plurality of bit line pairs. It is preferable to further include a bit line selecting means for inspection.

According to the method of testing a semiconductor memory device of the present invention, a number of word lines and a number of bit line pairs intersecting with each other and a plurality of word lines and a number of bit line pairs are provided in a matrix at each intersection. A memory cell array composed of a large number of memory cells, a word line driving circuit for receiving a row address signal and selectively driving a large number of word lines based on the received row address signal, and a plurality of bit line pairs. ,
A sense amplifier circuit for amplifying the potential difference between each bit line pair,
A column selection circuit for receiving a column address signal, selecting one of a number of bit line pairs based on the received column address signal, and inputting / outputting data to / from the outside; and a word line driving circuit in a test mode A test word line selecting means for selecting a word line so that a plurality of word lines can be driven at predetermined intervals and in one operation cycle with respect to a large number of word lines; Bit line selecting means for selecting a plurality of bit line pairs in one operation cycle and inputting / outputting data to / from the selected plurality of bit line pairs, according to a row address or a column address value. And a data scramble circuit for inverting the value of write data from the outside. When writing for the number of memory cells, by passing the write data to the data scramble circuit, writing a predetermined physical data pattern for a number of memory cells.

According to the semiconductor memory device inspection method of the present invention, when writing externally input write data to a large number of memory cells in the inspection mode, the write data is passed through a data scramble circuit, whereby Since a predetermined physical data pattern is written to the memory cells of the present embodiment, the time required for screening all the word lines and the previous bit lines can be reduced, and various stress application patterns can be easily generated without preparing them in advance. it can.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block configuration of a semiconductor memory device according to the first embodiment of the present invention. As shown in FIG. 1, on a semiconductor substrate, for example, 256 word lines WLm (where m = 0, 1,
2, ..., 255. ) And 256 bit line pairs B
A memory cell array 14 is provided in a matrix at the intersection of Lm, / BLm, each word line WLm, and each bit line pair BLm, / BLm, and has a memory capacity of 64 k bits.

In the specification of the present application, a symbol "/" added before a signal name indicates a signal having a complementary relationship with the signal or a signal which becomes significant (active) at a low level.

One end of each word line WLm receives row (row) address decode signals / RD0 to / RD63 and word line drive signals WD0 to WD3, and receives the row address decode signals / RD0 to / RD63. A word line driver 15 for selectively driving 256 word lines WLm is connected.

One end of each bit line pair BLm, / BLm is provided for each bit line pair BLm, / BLm, and amplifies the potential difference between the potentials read out for each bit line pair BLm, / BLm. Are connected to a sense amplifier array 16 for determining the data values.

The sense amplifier array 16 includes a test mode switching signal AWL (hereinafter referred to as a test mode switching signal AWL) which is activated in the test mode.
Call. ) And an internal column address signal,
The internal column address signal is decoded and each bit line pair B
Lm and / BLm are selected, and data I /
A column selecting circuit for performing O and a column decoder and selector 17 as a test bit line selecting means are connected.

On the other hand, the word line driver 15 has row address predecode signals XPA0 to XPA7, XPB0.
XPB7 to row address decode signal / RD0
To / RD63 are connected.

Each of the row decoders 18 has one terminal connected to a row address predecode signal XPA0 to XPA.
7, any one of XPB0 to XPB7 is input, and a test mode switching signal AWL is input to the other terminal. The circuit 19 is connected.

The control circuit 19 for raising a plurality of word lines receives internal row address signals AX0 to AX7, and receives row address predecode signals XPA0 to XPA7, XPB.
0 to XPB7 are connected to the row predecoder 20. The row predecoder 20 receives external row address signals A0 to A7 and receives an internal row address signal AX.
An address buffer 21 for generating 0 to AX7 is connected.

Between the row predecoder 20 and the word line driver 15, four terminals each of which receives a word line drive timing control signal WD at one terminal and a row address predecode signal at the other terminal. Is connected to a word line drive signal generation circuit 22 composed of an AND circuit.

The column decoder / selector 17 receives a write control pulse WRUN, is connected to a read / write amplifier 23 for writing or reading data, and receives column address signals A0 to A7 from outside, and A column address buffer for generating a column address signal and a column predecoder 24 are connected.

The timing generation circuit 25 generates a row address strobe signal RA as a trigger for starting a memory operation.
S, a column address strobe signal CAS serving as a trigger for a read operation, a write enable signal WE for restricting a write operation permission state or a prohibition state, and an output enable signal OE for permitting or prohibiting an output operation of read data to the outside. It outputs a word line drive timing control signal WD or an internal write enable signal WEN.

The delay control circuit 26 receives the word line drive timing control signal WD and generates a first delay amount (time) T1 which is a normal delay time.
And a second delay circuit 262 as a test delay time generating means for generating a second delay amount (time) T2 which is a test delay time, and a first delay circuit 261 and a second delay circuit 262. And a first selector 263 for receiving one of the delayed word line drive timing control signals WD, selecting one of them based on a test mode switching signal AWL, and outputting the selected signal as a sense amplifier drive signal SE. I have.

The write control pulse width switching circuit 27 as a write control means receives the internal write enable signal WEN and generates a third delay amount (time) T3, a third delay circuit 271 and a fourth delay amount. (Time) Fourth delay circuit 272 for generating T4 and third delay circuit 27
The second circuit receives the delayed internal write enable signal WEN from the first and fourth delay circuits 272, selects one of them based on the test mode switching signal AWL, and outputs the selected signal as a write control pulse WRUN.
And the selector 273 of FIG.

Between the delay control circuit 26 and the sense amplifier array 16 receiving the sense amplifier drive signal SE from the delay control circuit 26, one input terminal receives the sense amplifier drive signal SE and the other input terminal A sense amplifier disable control circuit 28 at the time of a write operation as sense amplifier amplification inhibiting means for receiving the inverted write control pulse WRUN and outputting a sense amplifier drive signal SE is connected.

FIG. 2 shows an example of a circuit configuration of the word line driver 15 and the row decoder 18 in the semiconductor memory device according to the present embodiment. As shown in FIG. 2, the word line driver 15 has a unit word line driver 15a provided for each word line WLm.

Each unit word line driver 15a has an input terminal connected to any one of row address decode signals / RD0 to / RD63, and an output terminal connected to word line W.
It has a first inverter 151 composed of a p-type transistor TP1 and a first n-type transistor TN1 connected to any one of Lm. The first inverter 151 of the 256 unit word line drivers 15a
Are connected to any one of the word line drive signals WD0 to WD3 so as to be repeated in this order.

Each of the unit word line drivers 15a has a drain connected to the word line WLm, a source grounded, and a gate inverted by the second inverter 152. It has a second n-type transistor TN2 that receives one of them.

The row decoder 18 is composed of 64 unit row decoders 18a, and each unit row decoder 18a has eight row address predecode signals XPA0 to XPA7, XPB0 from the row predecoder 20 respectively.
To XPB7, one of the 64 combinations is input, and the row address decode signal / R
NA for outputting any one of D0 to / RD63
An ND gate 181 is provided. For example, the unit row decoder 18a receiving the row address predecode signals XPA0 and XPB0 and outputting the row address decode signal / RD0 outputs the row address decode signal / RD0.
To the four unit word line drivers 15a connected to the word lines WL0 to WL3. Also, row address predecode signals XPA1 and XPB0 are input,
The unit row decoder 18a that outputs the row address decode signal / RD1 receives the row address decode signal / RD.
1 is output to four unit word line drivers 15a connected to the word lines WL4 to WL7.

FIG. 3 shows an example of the circuit configuration of the memory cell array 14, the sense amplifier array 16, the column decoder and selector 17, and the read / write amplifier 23 in the semiconductor memory device according to the present embodiment. As shown in FIG. 3, in the memory cell array 14, memory cells 13 each including a memory cell capacitor MC and a memory cell access transistor TWL are arranged in a matrix.

In the memory cell 13, for example, the memory cell access transistor TWL has a drain connected to the bit line BL0, a gate connected to the word line WL1, and a source connected to one electrode of the memory cell capacitor MC. , The other electrode of the memory cell capacitor MC is connected to a cell plate power supply VCP having a voltage value that is a half of the power supply voltage VDD.

The sense amplifier array 16 includes a sense amplifier drive circuit 161, a sense amplifier 162, and a bit line precharge circuit 163.

In the sense amplifier drive circuit 161, the gate receives the inverted signal of the sense amplifier drive signal SE, the source receives the power supply voltage VDD, and the drain is each sense amplifier 16.
2, a p-type sense amplifier driver transistor TPSE that supplies a power supply voltage VDD to each sense amplifier 162, a gate receives the sense amplifier drive signal SE, a source receives the ground voltage VSS, and a drain is each sense amplifier driver TPSE. 162, and an n-type sense amplifier driver transistor TNSE that supplies the ground voltage VSS to each sense amplifier 162.

The sense amplifier 162 includes a first inverter including a first p-type sense amplifier transistor TPSm and a first n-type sense amplifier transistor TNSm;
A second inverter including a second p-type sense amplifier transistor TPSmN and a second n-type sense amplifier transistor TNSmN is configured to be flip-flop connected.

The output terminal of the first inverter is a bit line B
Lm, and the output terminal of the second inverter is connected to the bit complementary line / BLm. The power supply voltage VDD is supplied from the sense amplifier drive circuit 161 to each of the p-type transistors TPSm and TPSmN of the first and second inverters, and each of the n-type transistors TNSm and TNSmN of the first and second inverters. Is supplied with the ground voltage VSS.

The bit line precharge circuit 163 has a source and a drain connected to the bit line pair BLm and / BLm, a gate receiving the bit line precharge signal BP at the gate, a bit line equalizing transistor TNEQm, and a bit line pair BLm and / BLm. , A common drain is connected to a bit line precharge power supply VBP having a voltage value of one half of the power supply voltage VDD, and a first bit line receiving a bit line precharge signal BP at each gate is provided. It comprises a precharge transistor TNPRm and a second bit line precharge transistor TNPRmN.

The column decoder and the selector 17 are arranged as shown in FIG.
, An AND gate 17a receiving a column predecode signal from the column address buffer and column predecoder 24, one input terminal receiving a test mode switching signal AWL, and the other input terminal being an AND gate 17a
And an OR gate 17b for receiving the output signal from the OR gate 17b. Further, one source / drain is connected to the bit line BLm, the other source / drain is connected to the data line DL used for reading or writing data, and the first column switch transistor has a gate receiving an output signal from the OR gate 17b. TNCm, one source / drain is connected to bit complementary line / BLm, the other source / drain is connected to data complementary line / DL, and the gate is OR
A second column switch transistor TNCmN for receiving an output signal from the gate 17b.

The read / write amplifier 23 is connected to the data line pair DL, / DL, amplifies the data read out to the data line pair DL, / DL, and amplifies the I / O buffer circuit 29.
Is connected to the I / O buffer circuit 29, and the amplified write data is output to the data line pair DL and / DL via an n-type switch transistor controlled by the write control pulse WRUN. And an amplifier 23b.

The operation of the semiconductor memory device configured as described above will be described below with reference to the drawings.

FIGS. 4 and 5 are timing charts of the operation of the semiconductor memory device according to the present embodiment. FIG. 4 shows a normal write operation, and FIG. 5 shows an operation in a test mode. (Normal Write Operation) A normal write operation will be described with reference to FIGS.

First, as shown in FIG. 4, in the normal mode, the test mode switching signal AWL is always at the low level. Here, among the signal names shown in FIG. 4, the signal names surrounded by a frame indicate that the signals are input from the outside.

Next, the row address strobe signal / RA
When S is activated by falling, the address buffer 21 shown in FIG. 1 takes in the row address signals A0 to A7,
Internal row address signal A is applied to row predecoder 20.
X0 to AX7 are output. Internal row address signal AX0
AX7, the row predecoder 20 receives 8
Row predecode signals XPA0 to XPA7 for each type,
One signal is selected from each of XPB0 to XPB7 and output to row decoder 18.

As shown in FIG. 2, the row decoder 18
Upon receiving the selected row predecode signal and selecting one of the 64 unit word line drivers 18a, 64 row address decode signals / RD0 are provided.
To / RD 63 and outputs a low-level signal value indicating an active state to the word line driver 15.

On the other hand, the timing generation circuit 25 shown in FIG.
The word line drive signal generation circuit 22 which receives the word line drive timing control signal WD from the row and the selection signal from the row predecoder 20 outputs four word line drive signals WD0
~ WD3 is selected and activated,
As a result, one of the word lines WLm is selected and activated. As a result, as shown in FIG. 3, the 256 memory cells 13 connected to one selected word line WL in the memory cell array 14 are held in the memory cell capacitors MC of the memory cells 13 respectively. The data of the minute potential is transferred to each bit line BLm and bit complementary line / BLm connected to the memory cell 13.

Next, as shown in FIG. 4, the sense amplifier drive signal SE rises after a first delay time T1 from the word line drive timing control signal WD. The first delay time T1 corresponds to the first delay time in the delay control circuit 26 shown in FIG.
Of the first delay circuit 261 is selected by the selector 263 of FIG. When the sense amplifier drive signal SE is activated, as shown in FIG. 3, the sense amplifier drive circuit 161 of the sense amplifier row 16 receiving the sense amplifier drive signal SE is activated, and each bit line pair BL
m, / BLm connected to each sense amplifier 16
2 amplifies the data read for each bit line pair BLm, / BLm to determine the value. This completes the read operation on the bit line pair BLm, / BLm of each memory cell 13.

Next, as shown in FIG. 4, the write enable signal / WE falls to set the write permission state. Subsequently, the column address strobe signal / CAS falls and is activated to take in the column address signals A0 to A7, and the column address buffer and the column predecoder 24 shown in FIG. 1 are activated. Subsequently, one bit line pair BL, / BL specified by the input address is selected by the column decoder and selector 17 shown in FIG.

Next, as shown in FIGS. 1 and 4, an internal write enable signal WE is supplied from the timing generation circuit 25 which has received the activated write enable signal / WE.
N is output, and the write control pulse WRUN is generated only during the third delay time T3 from the rise of the internal write enable signal WEN. This third delay time T3
Is a write control pulse width switching circuit 27 shown in FIG.
, The low-level test mode switching signal AW
L to the third delay circuit 27
It is generated by selecting the output signal on one side. Subsequently, as shown in FIG. 3, the bit line pair BLm, BLm, which is selected while the write control pulse WRUN is being generated.
The predetermined write data Din is input to / BLm through the write amplifier 23b.

At this time, as shown in FIG. 1, the sense amplifier disable control circuit 28 inhibits the output of the sense amplifier drive signal SE during the write operation while the write control pulse WRUN is activated. The drive signal SE becomes inactive during the generation of the write control pulse WRUN. As a result, the sense amplifier array 16 and the write amplifier 23b are not activated at the same time, so that the data write operation can be performed even in the case of the inversion write in which the complementary value of the read data is written. Can be performed in a short time. (Test Operation) Next, a test operation performed by simultaneously activating a plurality of word lines will be described with reference to FIGS.

First, as shown in FIG. 5, by raising and activating the test mode switching signal AWL,
The operation mode of the device is changed to the test mode.

Next, row address strobe signal / RA
When S is activated, the address buffer 21 shown in FIG.
Fetches row address signals A0 to A7, and supplies internal row address signals AX0 to AX to row predecoder 20.
X7 is output. At this time, the row predecode signals XPA0 to XPA0 are controlled by the control circuit 19 for starting up a plurality of word lines that receives the high-level test mode switching signal AWL.
Each of XPA7 and XPB0 to XPB7 is activated. Thereby, in row decoder 18 shown in FIG. 2, all of row address decode signals / RD0 to / RD63 are activated to low level, and word line driver 1 is activated.
5 is input.

At this time, internal word line drive signals WD0 to WD0
When one signal of WD3 is selected, 25
One quarter of the six word lines WLm, that is, 64
Are selected simultaneously, and the selected 64 word lines WL
Are transferred to each bit line pair BLm and / BLm. That is,
64 memory cells 1 are connected to a pair of bit lines BL and / BL.
3 will be read simultaneously.

In this case, the word line drive signals WD0 to WD
Since one of the three drives 64 word lines WL, the rise time of the word lines WL is longer than in the normal mode. In order to secure the rise time of the word line WL in the test mode, the present embodiment employs a delay control circuit 26 for generating the sense amplifier drive signal SE shown in FIG.
In the test mode, this is realized by selecting an output signal from the second delay circuit 262 that generates a second delay time longer than the first delay time T1 in the test mode.

Next, as shown in FIG. 5, the write enable signal / WE falls to bring the write enable state. Subsequently, the same data read and write operations as described above are performed by the column address strobe signal / CAS signal.

Here, the test mode switching signal AWL
Is active, 256 bit line pairs BL through the column decoder and selector 17 shown in FIG. 1 regardless of the values of external column address signals A0 to A7.
m and / BLm are selected at the same time. To realize this, the control circuit 19 for starting up a plurality of word lines is used.
This can be easily realized by incorporating a control circuit (not shown) having an OR gate similar to the above into the column address buffer and column predecoder 24.

In this way, one write data Din is developed at the time of the write operation, and the two
A write operation is performed on all 56 bit line pairs BLm and / BLm. Further, as a feature of the present embodiment, the write control pulse width switching circuit 27 for generating the write control pulse WRUN shown in FIG. 1 generates a fourth delay time T4 longer than the third delay time T3 in the test mode. By selecting the output signal from the fourth delay circuit 272 side and making the pulse width of the write control pulse WRUN longer than in the normal mode, the write operation margin for the 256 pairs of bit lines BLm and / BLm can be reduced. It secures and makes writing easy.

As described above, according to the present embodiment, (1) the number of word lines WL activated in the test mode is 64 times that in the normal mode, The same stress as in the mode can be applied in 1/64 time. In the present embodiment, 256 word lines WLm
64 (64/256) are selected at the same time, but four word line drive signals WD0
To WD3 at the same time, the number of activated word lines WLm becomes 12 compared to that in the normal mode.
As a result, the stress time equivalent to that in the normal mode can be further halved, that is, the time can be easily reduced to 1/128. (2) Stress can be easily applied between the word lines WL as compared with the stress application method of activating all the word lines WLm at once. For example, for each operation cycle,
The word line drive signals WD0 to WD3 are sequentially activated, and a total of 64 word lines WL are selected out of every 256 word lines WLm per cycle. This makes it possible to deactivate the unselected word lines WL adjacent to each of the activated word lines WL.
Stress can be reliably applied to the adjacent word lines WL. (3) By simultaneously selecting all of the plurality of bit line pairs BLm and / BLm and performing a write operation, stress is applied to each bit line pair BLm and / BLm, each memory cell 13, and each sense amplifier 162. Can be applied in a very short time.

As shown in this embodiment, 256 pairs of bit lines BLm and / BL
Although it is preferable to select all of m at once, it is not always necessary to select all the bit line pairs BLm and / BLm at the same time in consideration of the driving capability of the write circuit. (4) By providing the delay control circuit 26, the write control pulse width switching circuit 27, and the write operation sense amplifier disable control circuit 28, the read operation and the write operation for the plurality of bit line pairs BLm and / BLm in the test mode are performed. Can be performed stably.

First, the delay control circuit 26 detects the second delay amount T2 during the test operation in the sense amplifier drive signal SE.
Is made larger than the first delay amount T1 in the normal mode, the rising operation of the plurality of word lines WLm requiring a longer time than in the normal mode, the activation operation of the sense amplifier 162, and each memory Since an operation margin can be secured for the data read operation from the cell 13 to each bit line pair BLm, / BLm, the amplification operation of each sense amplifier 162 can be stabilized.

The write pulse width switching control circuit 27 sets the active period (= T4) of the write control pulse WRUN in the test operation to the active period (= T4) in the normal mode.
2), a plurality of bit line pairs B
A stable write operation can be guaranteed for Lm and / BLm.

Further, at the time of write operation, the sense amplifier disable control circuit 28 controls the sense amplifier 1 during write operation.
62 and the write amplifier 23b are simultaneously activated, that is, the pair of bit lines BLm and / BL amplified by the sense amplifier 162 even during inversion writing.
As compared with the method of forcibly rewriting the read data of m by the write amplifier 23b, even if the size of the write amplifier 23b is reduced or its capability is reduced, the writing operation can be performed in a short time and stably. It is advantageous for conversion.

As described above, according to the present embodiment, in the test mode, the efficiency of stress application is greatly improved as compared with the normal mode, so that the stress time for burn-in inspection and the like can be greatly reduced, and the conventional method can be used. Screening of a leak system between word lines WL and screening of a sense amplifier 162 and a bit line BL system, which cannot be obtained by a method such as batch activation of all word lines, can be performed, so that deterioration in quality can be suppressed.

Further, by combining the write operation in the test mode and the read operation in the normal mode according to the present embodiment, the test of the memory cell array 14 can be performed in a very short time, and can be used for monitoring such as burn-in inspection. In addition, the inspection time can be shortened also in the wafer inspection of the device or the inspection after the package sealing.

(First Modification of First Embodiment) Hereinafter, a first modification of the first embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows an example of a circuit configuration of a sense amplifier drive circuit of a semiconductor memory device according to a first modification of the present embodiment. As shown in FIG. 6, the sense amplifier driving circuit 161A according to the present modification has the bit line amplitude enlarging circuit unit 30 activated in the test mode in the sense amplifier driving circuit 161 shown in FIG. Here, circuits other than the sense amplifier drive circuit 161A have the same configuration as the circuit configuration shown in FIGS.

The bit amplitude enlarging circuit unit 30 receives the sense amplifier drive signal SE at one input terminal and receives the inverted signal of the test mode switching signal AWL at the other input terminal, and outputs the result of the AND operation. And a delay circuit 302 that outputs a sense ground control signal SGC obtained by delaying the output signal of the NAND circuit 301, a p-type transistor TPSG and a first n-type transistor TNSG1, and the input sense ground And an inverter that outputs a sense bottom potential SGND obtained by inverting the control signal SGC. Further, the semiconductor device includes a second n-type transistor TNSG2 in which the gate and the drain are diode-connected and the source is grounded, and the sense bottom voltage SGND is applied to the gate and the drain of the second n-type transistor TNSG2. . Here, when the sense ground control signal SGC is at a low level, the sense bottom voltage SGND is clamped to about the threshold voltage of the second n-type transistor TNSG2. The drain of the second n-type transistor TNSG2 is connected to the n-type sense amplifier driver transistor T described above.
Connected to NSE source.

Hereinafter, the operation of the semiconductor memory device including the sense amplifier driving circuit 161A configured as described above will be described.

FIG. 7 shows a timing chart in a normal operation, and FIG. 8 shows a timing chart in a test mode.

As shown in FIG. 7, this modification employs a dynamic sense ground system for reducing the off-leak current of an access transistor in a memory cell during a normal write operation or read operation. The dynamic sense ground scheme is an improved version of the boost sense ground scheme. The dynamic sense ground scheme raises the low level of the bit line BLm with respect to the ground voltage VSS to reduce the off-leak of the access transistor of the memory cell. This is a method for improving charge retention characteristics. Further, in order to facilitate the sensing operation of the sense amplifier array even at the time of low power supply voltage driving, the sense bottom voltage SGND is set to the ground voltage VSS only for a predetermined period immediately after the start of the operation of the sense amplifier array. Second n-type transistor TNSG
The threshold voltage is raised to about 2 Vtn.

As described above, the bit line pair BL, / BL at the time of normal operation by the dynamic sense ground system is used.
The operating amplitude of the high-level side is the power supply voltage VDD,
The low level is substantially equal to the ground voltage VSS and the threshold voltage V
tn.

On the other hand, in the test mode shown in FIG. 8, in the bit line amplitude enlarging circuit section 30 shown in FIG. 6, the NAND circuit 301 outputs the high level sense amplifier drive signal SE and the high level test mode switching signal AWL. Receives the sense ground control signal S
GC becomes high level. As a result, the sense bottom voltage SGND becomes the ground voltage VSS, so that the bit line pair B
The operating amplitudes of Lm and / BLm are the power supply voltage VDD on the high level side and the ground voltage VSS on the low level side, and the amplitude of the bit line pair is surely larger than in the normal operation.

As a result, in the normal operation mode, the operation margin of the read operation or the write operation can be secured while reducing the off-leakage current, and the bit rate in the test mode is smaller than that in the normal mode. Since a large voltage stress can be applied to the line and the memory cell array, the stress efficiency can be further improved.

(Second Modification of First Embodiment) Hereinafter, a second modification of the first embodiment of the present invention will be described with reference to the drawings.

FIG. 9 shows an example of a circuit configuration of a data scramble circuit of a semiconductor memory device according to a second modification of the present embodiment. As shown in FIG. 9, the semiconductor memory device according to this modification includes a data scramble circuit 31 provided between the read / write amplifier 23 and the I / O buffer circuit 29 shown in FIG.

The data scramble circuit 31 receives the internal row address signal A from the address buffer 21 shown in FIG.
A data inversion control circuit 311 that receives X0 and AX1 and outputs an inversion control signal for instructing whether or not to invert the value of data input from the outside; An inverting circuit 312 for inverting, and an inverting circuit 31 for inverting the inversion control signal only while the test mode switching signal AWL is activated.
And an AND circuit 313 for activating the logic circuit 2.

The inverting circuit 312 has a first EXOR circuit 312a that receives an inversion control signal at one input terminal, receives read data at the other input terminal, performs an exclusive OR operation, and outputs the result to the outside. Input terminal receives the inversion control signal, and the other input terminal
The second EXO which receives the read data from the memory device, performs an exclusive OR operation, and outputs the result to the read / write amplifier 23
And an R circuit 312b.

The operation of the semiconductor memory device configured as described above will be described below.

In the normal operation, since the inversion control signal is always at the low level, the values of the read data and the write data are input / output as they are without being inverted.

In the test mode, the test mode switching signal AWL is activated from a low level to a high level. Thereby, the internal row address signals AX0 and AX
The signal level of the inversion control signal can be changed based on the four signals consisting of 1s. Therefore, when the signal level of the inversion control signal is high, the values of the read data and the write data are respectively inverted.

Thus, each memory cell 13 shown in FIG.
Can be changed according to the purpose of inspection. For example, by writing physical data "1" to all of the memory cells 13, a method of maximizing the voltage stress between the memory cells 13 and the substrate,
By writing physical data "0" to all of the memory cells 13, a method of maximizing the stress between the memory cell 13, the word line WLm and the power supply potential, and further,
A stripe pattern in which data values are alternately inverted in units of rows as physical data, or a data pattern in which data values are alternately inverted in units of rows and columns, and one memory cell 13 and another adjacent to the one memory cell 13 A method of increasing the voltage stress between the memory cells 13 by writing a so-called checker pattern having a different data value from the memory cells 13 can be considered.

Thus, in the test mode, the data scramble circuit 31 can easily generate a stripe pattern or a checker pattern as an input pattern of test data given from the outside, so that the semiconductor memory device to be tested can be easily generated. Stress margin evaluation and analysis can be performed extremely efficiently.

(Second Embodiment) Hereinafter, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 10 shows a block configuration of a semiconductor memory device according to the second embodiment of the present invention. In FIG. 10, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. As shown in FIG. 10, the semiconductor device according to the present embodiment is characterized in that a memory cell array 14 has a plurality of spare memory cells, so-called redundant memory cells 13a. Recent large-capacity semiconductor memory devices include a memory cell 13, a word line WL
In general, when there is a slight defect in m or the pair of bit lines BLm and / BLm, the defective portion is set to an unused state, and repaired using a spare memory cell 13a instead.

As shown in FIG. 10, the semiconductor memory device according to the present embodiment includes a redundant address detection circuit 32, a redundant word line activation control circuit 33, a redundant row decoder 34,
A redundant word line driver 35, an OR circuit 36, and a predecode control circuit 37 are provided.

The redundant address detection circuit 32 receives the output of the address buffer 21 and outputs 2-bit redundant address detection signals FS0 and FS1 for specifying a defective portion.

The redundant word line start-up control circuit 33
One input terminal receives the redundant address detection signal FS0,
A first OR circuit 3 receives the test mode switching signal AWL at the other input terminal, and generates and outputs a redundant row address predecode signal XPS0 composed of the logical sum of these signals.
3a and one input terminal is a redundant address detection signal FS1.
And the other input terminal receives the test mode switching signal A
A second OR that receives and generates and outputs a redundant row address predecode signal XPS1 composed of a logical sum of these WLs
And a circuit 33b.

The redundant word line driver 35 has eight unit word line drivers 15a constituting the word line driver 15 shown in FIG.
a is connected to the redundant word lines SWL0 to SWL7, respectively.

The OR circuit 36 outputs the redundant address detection signal F
S0 and FS1 are received, a logical sum of them is calculated, and the result is output.

The predecode control circuit 37 has one input terminal receiving the inverted output from the OR circuit 36 and the other input terminal among the row address predecode signals XPA0 to XPA7 and XPB0 to XPB7 from the row predecoder 20. And an AND circuit 37a for calculating a logical product of the received signals and outputting the result.

In the inspection step, when a defect is detected in the memory cell 13 or the like, the redundant address detection circuit 32
, For example, a fuse ROM is programmed to avoid the defective memory cell 13. As a result, only when a defective address is externally accessed, the redundant address detection signals FS0 and FS1 which are normally inactive at low level are activated to high level, and the redundant row decoder 34 and redundant word line driver 35 are activated. Operate, redundant word lines SWL0-SWL0
Any one of WL7 is selected, and access to redundant memory cell 13a is performed.

At the time of screening inspection for a semiconductor memory device having such a configuration, first, an externally input test mode switching signal AWL is changed from an inactive state to an active state.

As shown in FIG. 10, the test mode switching signal AWL is supplied to the control circuit 19 for starting up a plurality of word lines.
The signal is input to all OR circuits constituting the redundant word line start-up control circuit 33. As a result, the row address predecode signals XPA0 to XPA7, XPB0 to XPB regardless of the presence or absence of the redundancy repair programming.
7 and the redundant row address predecode signals XPS0, XPS
By simultaneously selecting PS1 and the normal word line WLm, voltage stress is applied to 64 out of the 256 word lines WLm and 8 in the case of the redundant word line SWL.
Voltage stress is applied to two of the books.

As described above, according to the present embodiment, in the test mode, as in the first embodiment, the word line drivers 15 are provided at predetermined intervals and at a plurality of word lines W.
Since L is driven simultaneously, the word lines WL located on both sides of the driven word line are not driven. Therefore, the same stress acts on the adjacent word lines WL as in the normal operation, and the screening effect is improved.
In addition, since stress can be applied to the redundant memory cell 13a in the same manner as the normal memory cell 13, it is very effective for shortening the screening time and ensuring quality.

In the present embodiment, a configuration in which redundant word lines SWL are provided is taken as an example, but a configuration in which spare bit line pairs (redundant bit line pairs) BL and / BL are provided may be used. . In this case, a circuit for a redundant bit line is provided in each of the sense amplifier array 16, the column decoder and the selector 17, and the column address buffer and the column predecoder 24.

(Third Embodiment) Hereinafter, a third embodiment of the present invention will be described with reference to the drawings.

FIGS. 11 and 12 are block diagrams of a semiconductor memory device according to the third embodiment of the present invention.
1 shows a configuration of a portion including a plurality of memory cell arrays,
FIG. 12 shows a configuration of another peripheral portion. FIG.
12 and FIG. 12, the same components as those shown in FIG.
As shown in FIG. 11, the semiconductor memory device according to the present embodiment includes eight memory cell arrays 14A to 14H, and a region outside each of the memory cell arrays 14A to 14H in the bit line direction has a sense amplifier array. 16 are provided.

A memory cell array 14A is provided between each of the memory cell arrays 14A to 14H and each sense amplifier row 16.
Bit line BL between .about.14H and the sense amplifier row 16
A shared gate (transfer gate) circuit 38 for selectively connecting m and / BLm is provided. Thus, for example, the sense amplifier array 16 provided between the first memory cell array 14A and the second memory cell array 14B shares the bit line pair BLm, / BLm between these memory cell arrays, The number of sense amplifier rows 16 is reduced.

Each shared gate circuit 38 is provided with a shared gate control circuit 39 for selectively turning on the shared gate circuit 38.

Shared gate control circuit 39 has a first input terminal receiving any one of bank switching row predecode signals BK0-BK7 for selecting memory cell arrays 14A-14H, and a second input terminal. Includes a NAND circuit receiving an inverted signal of test mode switching signal AWL. However, in the shared gate control circuit 39 connected to the shared gate circuit 38 located on the opposite side of the first memory cell array 14A from the second memory cell array 14B, the ground voltage VSS is applied to the first input terminal. ing. The shared gate control circuit 39 connected to the shared gate circuit 38 located on the side opposite to the seventh memory cell array with respect to the eighth memory cell array 14A also receives the ground voltage VSS applied to the first input terminal. I have.

Each of the row decoders 18 receives one of the bank switching row predecode signals BK0 to BK7. Further, the bit line pair BLm, / BL
m, 128 pairs of global data lines DL0 to DL12 shared by the memory cell arrays 14A to 14H.
7, / DL0 to / DL127. The required column address is 8 bits (A0
To A7).

As shown in FIG. 12, in order to specify eight memory cell arrays 14A to 14H, three newly added A8 to A10 are stored in the address buffer 21.
Bit is input. Thereby, the address buffer 2
1 generates the internal row address signals AX8 to AX10 and outputs them to the row predecoder 21.
Outputs row predecode signals BK0 to BK7 for bank switching to the newly added bank switching control circuit 40.

The operation of the semiconductor memory device configured as described above will be described below.

First, at the time of normal write operation or read operation, the shared gate 38 is turned on so that only the sense amplifier row 16 adjacent to the selected and activated memory cell array is activated. As a result, the bit line pair B connected to the activated sense amplifier row 16
The amplification operation is performed only on L and / BL.

For example, in FIG. 11, it is assumed that BK0 of the row predecode signal from bank switching control circuit 40 has been activated to a high level. At this time, shared gate control circuit 39 receiving row predecode signal BK1 for bank switching outputs a high level (activation) control signal, and shared gate control circuit 39 receiving row predecode signal BK0 outputs low level. (Inactivation) control signal is output. Thereby, of the two shared gates 38 arranged between the first memory cell array 14A and the second memory cell array 14B, the shared gate 38 on the first memory cell array 14A side becomes conductive, and the second The shared gate 38 on the memory cell array 14B side is turned off.

Next, in the test mode, since test mode switching signal AWL is activated, all shared gate circuits 38 receiving all activated test mode switching signal AWL conduct. Transition to the state. Thereby, all the memory cell arrays 14A to 14H are activated.
A write operation to the bit line pair BLm, / BLm of the memory cell array adjacent to one sense amplifier row 16 can be performed simultaneously. As a result, even if the configuration includes a plurality of memory cell arrays 14A to 14H, the first
In the test mode, since the word line driver 15 simultaneously drives a plurality of word lines WL at predetermined intervals and in the test mode, the word lines located on both sides of the driven word line WL are not driven. Therefore, the same stress as in the normal operation acts on the adjacent word lines WL, the screening effect is improved, and the stress can be applied for a short time.

[0119]

According to the first semiconductor memory device of the present invention, the sense amplifier for setting the amplitude of the amplified voltage for amplifying the potential difference between the pair of bit lines in the test mode to be larger than the amplitude of the amplified voltage in the normal mode. Since the driving circuit is provided, a larger voltage stress can be applied to the bit lines and the memory cells in the test mode than in the normal mode, so that the screening test efficiency can be improved.

According to the second semiconductor memory device of the present invention, in the test mode, the word line driving circuit drives a plurality of word lines every predetermined number and in one operation cycle, so that the driven word lines are driven. Are not driven. Therefore, the same stress is applied to the adjacent word lines as in the normal operation, and the screening effect is improved. Furthermore, since a data scramble circuit for inverting the value of write data input from the outside is provided, a stripe pattern in which physical data values are inverted in units of rows or columns for a plurality of memory cells, and a checker Since a pattern can be easily generated, inspection efficiency can be improved.

According to the third semiconductor memory device of the present invention, even in a configuration having spare memory cells, the word line drive circuit can switch a plurality of word lines including the spare word line every predetermined number. Since the driving is performed in one operation cycle, the screening inspection efficiency can be improved.

According to the fourth semiconductor memory device of the present invention, the bit line pair shared by the memory cell arrays is activated by activating the shared gate circuit sharing the bit line pair between the adjacent memory cell arrays in the test mode. Since the writing operation to the pair can be performed at the same time, the inspection time for screening a plurality of memory cell arrays can be reduced even in a configuration including a plurality of memory cell arrays.

According to the semiconductor memory device inspection method of the present invention, the inspection method for the second semiconductor memory device of the present invention, wherein the time for performing screening for all word lines and all bit lines is reduced. In addition to being able to shorten, various stress application patterns that increase the voltage stress can be easily generated.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a word line driver and a row decoder of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing a memory cell array, a sense amplifier array, a column decoder, and a read / write amplifier of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing a normal write operation of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a timing chart showing an operation in a test mode of the semiconductor memory device according to the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing a sense amplifier drive circuit of a semiconductor memory device according to a first modification of the first embodiment of the present invention.

FIG. 7 is a timing chart showing a normal operation of the semiconductor memory device according to the first modification of the first embodiment of the present invention;

FIG. 8 is a timing chart showing an operation in a test mode of the semiconductor memory device according to the first modification of the first embodiment of the present invention.

FIG. 9 is a circuit diagram showing a data scramble circuit of a semiconductor memory device according to a second modification of the first embodiment of the present invention.

FIG. 10 is a block diagram illustrating a semiconductor memory device according to a second embodiment of the present invention.

FIG. 11 is a partial block diagram showing a semiconductor memory device according to a third embodiment of the present invention.

FIG. 12 is a partial block diagram illustrating a semiconductor memory device according to a third embodiment of the present invention.

[Explanation of symbols]

WL word line BL bit line / BLm complementary bit line 13 memory cell 14 memory cell array 15 word line driver (word line drive circuit) 15a unit word line driver 151 first inverter 152 second inverter 16 sense amplifier train 161 sense amplifier drive Circuit 162 Sense amplifier 163 Bit line precharge circuit 17 Column decoder and selector (inspection bit line selecting means) 17a AND gate 17b OR gate 18 Row decoder 18a Unit row decoder 181 NAND gate 182 NAND gate 19 Multiple word line rise control Circuit (inspection word line selection means) 20 row predecoder 21 address buffer 22 word line drive signal generation circuit 23 read / write amplifier 23a read amplifier 23b write Amplifier 24 column address buffer and column predecoder 25 timing generation circuit 26 delay control circuit 261 first delay circuit 262 second delay circuit (inspection delay time generation means) 263 first selector 27 write control pulse width switching circuit ( Write control means) 271 Third delay circuit 272 Fourth delay circuit 273 Second selector 28 Sense amplifier disable control circuit during write operation (Sense amplifier amplification prohibition means) 29 I / O buffer circuit 30 Bit line amplitude expansion circuit Unit 301 NAND circuit 302 Delay circuit 31 Data scramble circuit 311 Data inversion control circuit 312 Inversion circuit 312a First EXOR circuit 312b Second EXOR circuit 313 AND circuit 32 Redundant address detection circuit 33 Redundant word line rise control Circuit 33a First OR circuit 33b Second OR circuit 34 Redundant row decoder 35 Redundant word line driver 36 OR circuit 37 Predecode control circuit 38 Shared gate circuit 39 Shared gate control circuit 40 Bank switching control circuit AWL Multiple word line rise Test mode switching signal (test mode switching signal) / RAS Row address strobe signal / CAS Column address strobe / WE Write enable signal OE Output enable signal A0-A7 Row address signal A0-A7 Column address signal AX0-AX7 Internal row address signal XPA0 -7 Row address predecode signal XPB0-7 Row address predecode signal XPC0,1 Row address predecode signal / RD0 // RD63 Row address decode signal No. / RD0 // RD127 Row address decode signal WD Word line drive timing control signal WEN Internal write enable signal WRUN Write control pulse SE Sense amplifier drive signal

Claims (8)

[Claims] 1. A memory cell array comprising a large number of word lines and a large number of bit line pairs crossing each other, and a large number of memory cells provided in a matrix at each intersection of the large number of word lines and a large number of bit lines. A word line driving circuit that receives a row address signal and selectively drives the plurality of word lines based on the received row address signal; and a potential difference between each bit line pair provided for each of the plurality of bit line pairs. A sense amplifier circuit that amplifies the data, a column selection circuit that receives a column address signal, selects one of the plurality of bit line pairs based on the received column address signal, and performs input / output of data with the outside. A sense amplifier drive circuit for setting the amplitude of the amplified voltage for amplifying the potential difference between the bit line pair in the test mode to be larger than the amplitude of the amplified voltage in the normal mode. The semiconductor memory device characterized in that it comprises. 2. In the test mode, a test for selecting the word lines so that the word line drive circuit can drive a plurality of word lines at predetermined intervals and in one operation cycle for the plurality of word lines. And a word line selecting means for selecting a plurality of bit line pairs among the plurality of bit line pairs in one operation cycle in the test mode, and inputting and outputting data to and from the selected plurality of bit line pairs. 2. The semiconductor memory device according to claim 1, further comprising: a test bit line selecting unit for performing a test. 3. A memory cell array comprising a large number of word lines and a large number of bit line pairs crossing each other, and a large number of memory cells provided in a matrix at each intersection of the large number of word lines and a large number of bit lines. A word line driving circuit that receives a row address signal and selectively drives the plurality of word lines based on the received row address signal; and a potential difference between each bit line pair provided for each of the plurality of bit line pairs. A sense amplifier circuit that amplifies the data, a column selection circuit that receives a column address signal, selects one of the plurality of bit line pairs based on the received column address signal, and performs input / output of data with the outside. In the test mode, the word line drive circuit selects the word lines so as to drive a plurality of word lines at predetermined intervals and in one operation cycle with respect to the large number of word lines. A plurality of bit line pairs in the plurality of bit line pairs in one operation cycle during the test mode, and input data to the selected plurality of bit line pairs. A semiconductor device comprising: a test bit line selecting means for performing output; and a data scramble circuit for inverting a value of write data inputted from the outside based on the row address signal or the column address signal. Storage device. 4. A memory cell array comprising a large number of word lines and a large number of bit line pairs crossing each other, and a large number of memory cells provided in a matrix at each intersection of the large number of word lines and a large number of bit lines. A word line driving circuit that receives a row address signal and selectively drives the plurality of word lines based on the received row address signal; and a potential difference between each bit line pair provided for each of the plurality of bit line pairs. A sense amplifier circuit that amplifies the data, a column selection circuit that receives a column address signal, selects one of the plurality of bit line pairs based on the received column address signal, and performs input / output of data with the outside. In the test mode, the word line drive circuit selects the word lines so as to drive a plurality of word lines at predetermined intervals and in one operation cycle with respect to the large number of word lines. Test word line selecting means, the plurality of word lines include a spare word line, and the memory cell array has spare memory cells driven by the spare word line. The semiconductor memory device, wherein the plurality of word lines driven by the test word line selecting means sometimes include the spare word lines selected every predetermined number. 5. A test for selecting a plurality of bit line pairs from the plurality of bit line pairs in one operation cycle and inputting / outputting data to / from the selected plurality of bit line pairs in the test mode. 5. The semiconductor memory device according to claim 4, further comprising: a use bit line selecting unit. 6. A plurality of memory cell arrays each having a large number of memory cells provided in a matrix at respective intersections of a large number of word lines and a large number of bit line pairs; A plurality of shared gate circuits provided so that the bit line pairs can be shared between adjacent memory cell arrays; and a plurality of shared gate circuits provided between the adjacent memory cell arrays via the shared gate circuit. A sense amplifier circuit for amplifying a potential difference between the pair, a word line driving circuit for receiving a row address signal and selectively driving the plurality of word lines based on the received row address signal, and a column address signal for receiving and receiving the column address signal. A column selection circuit for selecting any of the plurality of bit line pairs based on a column address signal and performing input / output of data with the outside; A shared gate control means for activating the shared gate circuit in a test mode to simultaneously perform a write operation on each bit line pair of the memory cell arrays adjacent to each other. Storage device. 7. In the test mode, a test for selecting the word lines so that the word line drive circuit can drive a plurality of word lines at predetermined intervals and in one operation cycle for the plurality of word lines. And a word line selecting means for selecting a plurality of bit line pairs among the plurality of bit line pairs in one operation cycle in the test mode, and inputting and outputting data to and from the selected plurality of bit line pairs. 7. The semiconductor memory device according to claim 6, further comprising: a test bit line selecting means for performing a test. 8. A memory cell array comprising a large number of word lines and a large number of bit line pairs intersecting each other, and a large number of memory cells provided in a matrix at each intersection of said large number of word lines and a large number of bit lines. And receives the row address signal,
A word line drive circuit for selectively driving the plurality of word lines based on the received row address signal, a sense amplifier circuit provided for each of the plurality of bit line pairs, and amplifying a potential difference between each bit line pair; A column selection circuit for receiving a column address signal, selecting one of the plurality of bit line pairs based on the received column address signal, and inputting / outputting data to / from the outside; A drive circuit for selecting a word line so as to be able to drive a plurality of word lines at predetermined intervals and in one operation cycle with respect to the large number of word lines; and Test bit line selecting means for selecting a plurality of bit line pairs among the plurality of bit line pairs in one operation cycle and inputting / outputting data to / from the selected plurality of bit line pairs; A data scramble circuit for inverting the value of write data from the outside according to the value of the row address or the column address. A semiconductor memory device for writing a predetermined physical data pattern to the multiple memory cells by passing the write data through the data scramble circuit when writing data to the multiple memory cells; Inspection method.