JP2000182397A - Semiconductor memory and method for checking the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a screening time, and to sufficiently operate memory cell screening, inter-adjacent word line screening and bit line screening, and peripheral circuit screening. SOLUTION: A row decoder 18 for receiving a row address pre-decode signal, and for generating a row address decode signal is connected with a word line driver 15 for driving plural word lines WL. A control circuit 19 for raising plural word lines to which the row address pre-decode signal and plural word line rise test mode switching signal AWL are inputted is connected with the row decoder 18. A word line driving signal generating circuit 22 to which a word line driving timing control signal WD and the row address pre-decode signal are inputted is connected between a row pre-decoder 20 and the word line driver 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device comprising a dynamic random access memory (DRAM), and more particularly to a semiconductor memory device capable of efficiently screening for initial failures and a method of inspecting the same.

[0002]

2. Description of the Related Art In recent years, with the increase in density and integration of semiconductor memory devices, the time required for testing the devices and the time required for screening for initial failures such as burn-in have been increasing. On the other hand, with the spread of system LSIs and the advancement of functions and the complexity of functions, how to reduce or reduce the screening time and reduce the manufacturing cost has become a major issue.

[0003] Among others, in burn-in screening, some studies have been made to shorten or reduce the number of steps without reducing the quality of products.

[0004] Burn-in screening in a semiconductor memory device such as a DRAM is performed under high temperature and high voltage conditions.
In general, a method of performing an ordinary read operation and a write operation on a device to stress a device, particularly a memory cell, to screen for an initial failure. In this method, signals such as an address signal, a data signal, and a clock signal are input from the outside, a plurality of word lines are selected one by one, and stress is sequentially applied to the selected word lines.

[0005] One of the methods studied or adopted to improve the efficiency of stress application and shorten the time is to start up all the word lines in the device at the same time and collectively collect all the memory cells. And applying stress.

According to this method, all the word lines are simultaneously activated within one cycle regardless of the external address, and the same is applied to all the memory cell arrays. At the same time, stress is applied. This method has attracted attention as a method for reducing the screening time, and has been studied not only for the burn-in inspection in the conventional package state but also for the high-voltage stress test and the like at the time of burn-in or wafer inspection at the wafer level. ing.

[0007]

However, the above-described conventional semiconductor memory device and its inspection method have the following problems.

That is, a first method for sequentially applying a stress to each word line by sequentially selecting a word line while changing an address as in the normal operation is as follows.
Needless to say, there is a problem that the screening time becomes enormous.

On the other hand, the second method of applying the stress by driving all the word lines collectively reduces the screening time, but (1) at the time of normal operation, one word of many word lines By driving only the lines, stress is applied between one driven word line and the other non-driven word line adjacent to the one word line.
In the second method, as a result of driving all the word lines, no stress is applied to the adjacent word lines, so that the screening effect is reduced.

(2) In the method of driving all the word lines at once, the same read operation and write operation as in the normal operation are not performed.
Furthermore, the stress on the sense amplifier circuit is not sufficient, and the screening is incomplete in this respect as well.

As described above, it is difficult to secure sufficient quality in the second method of starting up the word lines all at once.

It is an object of the present invention to solve the above-mentioned conventional problems and to sufficiently perform screening of memory cells and word lines adjacent to each other, bit lines and peripheral circuits while greatly reducing the screening time. With the goal.

[0013]

In order to achieve the above object, the present invention provides a method of simultaneously selecting and driving a predetermined number of word lines out of a large number of word lines during a test such as a stress test. At the same time, it is configured to perform a sensing operation or a writing operation.

More specifically, the semiconductor memory device according to the present invention has a number of word lines and a number of bit line pairs crossing each other, and a matrix at each intersection of a number of word lines and a number of bit line pairs. A memory cell array comprising a large number of memory cells provided; a word line driving circuit for receiving a row address signal and selectively driving a large number of word lines based on the received row address signal; Provided,
A sense amplifier circuit for amplifying the potential difference between each bit line pair,
A column selection circuit that receives a column address signal, selects one of a number of bit line pairs based on the received column address signal, and inputs / outputs data to / from an external device; A test word line selecting means for selecting a line drive circuit so as to drive a plurality of word lines at predetermined intervals and in one operation cycle for a large number of word lines; Selecting a plurality of bit line pairs of the line pairs in one operation cycle;
Test bit line selecting means for inputting / outputting data to / from a plurality of selected bit line pairs.

According to the semiconductor memory device of the present invention, in response to the inspection mode control signal, the word line drive circuit can drive a plurality of word lines at predetermined intervals and in one operation cycle for a large number of word lines. Since the word line selecting means for selecting is provided, a word line adjacent to each of the plurality of word lines driven in the test mode is not driven. Therefore, the same stress as in the normal operation acts between the selected word line and the unselected word line. In addition, one of the write cycle or the read cycle
Since a plurality of word lines are selected in a cycle, the time for performing screening for all word lines can be reduced.

According to the semiconductor memory device of the present invention, the timing for activating the word line selected by the test word line selecting means and the timing for activating the bit line pair selected by the test bit line selecting means are determined. And a test delay time generating means for generating a test delay time for providing a delay between the test time and the test delay time generating means. It is preferable that the setting is made longer than a normal delay time for providing a delay between the activation timing and the timing at which the bit line pair selected by the column selection circuit is activated. With this configuration, in the test mode, a test delay time generation that generates a test delay time longer than the normal delay time between the timing when the word line is activated and the timing when the bit line pair is activated is performed. Means, a sufficient operation margin is secured between the rising operation of multiple word lines, which requires more time than the normal operation, and the data reading operation from the sense amplifier and memory cell to the bit line pair. it can.

Preferably, the semiconductor memory device of the present invention further comprises sense amplifier amplification inhibiting means for inhibiting the amplification operation of the sense amplifier circuit during the write operation. By doing so, the amplification operation of the sense amplifier is inhibited (disabled) during the write operation. Therefore, for example, the write amplifier for writing data is operated while the sense amplifier is activated, as compared with the case where the write amplifier for writing data is operated. The drive capability of the amplifier can be reduced.

The semiconductor memory device according to the present invention further comprises a write control means for outputting a write control pulse for controlling whether or not to input write data to the column selection circuit, wherein the write control means is provided in the test mode. It is preferable to set the pulse width of the write control pulse so that the pulse width of the write control pulse is larger than the pulse width of the write control pulse in the normal mode. By doing so, the active period of the write control pulse in the test mode is longer than in the normal operation, and the write operation on the plurality of bit line pairs is further stabilized.

Preferably, the semiconductor memory device of the present invention further includes an internal address generating means (address counter) for receiving a test mode control signal and internally generating a row address signal. This eliminates the need for an external address signal in the test mode, so that the number of external control terminals can be reduced. As a result, measurement can be simplified and the device can be simplified.

In the semiconductor memory device according to the present invention, the internal address generating means outputs the internally generated row address signal in place of the externally applied row address signal in the test mode.
It is preferable to output the word lines so that word lines selected every predetermined number out of a large number of word lines are sequentially replaced.

It is preferable that the semiconductor memory device of the present invention further includes an external terminal for receiving a test mode control signal.

According to the first method for testing a semiconductor memory device of the present invention, a plurality of word lines and a plurality of bit line pairs intersecting with each other and a matrix at each intersection of the many word lines and a plurality of bit line pairs are provided. A method for testing a semiconductor memory device having a memory cell array composed of a large number of memory cells arranged in a shape, and is selected in a predetermined number of word lines and in one operation cycle among a large number of word lines in a test mode. The word lines are driven so that a plurality of word lines are sequentially replaced.

According to the first semiconductor memory device inspection method, in the inspection mode, the word lines are selected such that a plurality of word lines selected in a predetermined number out of a large number of word lines in one operation cycle are sequentially replaced. , The word line adjacent to each of the plurality of word lines driven in the test mode is not driven. Therefore, the same stress as in the normal operation acts between the selected word line and the unselected word line. Further, since a large number of word lines are selected in one cycle of a write cycle or a read cycle, the time required for screening all the word lines can be reduced.

According to a second method for testing a semiconductor memory device according to the present invention, a plurality of word lines and a number of bit line pairs intersecting each other, and a matrix at each intersection of a number of word lines and a number of bit line pairs. A memory cell array composed of a large number of memory cells provided in a shape, a word line driving circuit for receiving a row address signal and selectively driving a large number of word lines based on the received row address signal, and a large number of bit line pairs A sense amplifier circuit that amplifies the potential difference between each bit line pair, receives a column address signal, selects one of a number of bit line pairs based on the received column address signal, and In response to a column selection circuit for inputting / outputting data and a test mode control signal, a word line drive circuit can drive a plurality of word lines at predetermined intervals and in one operation cycle for a large number of word lines. Receiving a test mode control signal, selecting a plurality of bit line pairs among a number of bit line pairs in one operation cycle, and selecting the selected plurality of bit line pairs. The present invention is directed to a semiconductor memory device inspection method including an inspection bit line selecting means for inputting / outputting data, wherein an inspection mode control signal is a first bit.
In the case of the state, the first step of selecting a plurality of word lines at predetermined intervals for a large number of word lines and in one operation cycle by using the inspection word line selecting means; In this case, a plurality of bit line pairs among a large number of bit line pairs are selected in one operation cycle by using the inspection bit line selecting means, and data is written to the memory cell through the selected plurality of bit line pairs. And a third step of selecting one of the plurality of bit line pairs using the column selection circuit when the test mode control signal is in the second state, and in a second state, And a fourth step of reading written data by amplifying the potential difference between the selected bit line pair using a sense amplifier circuit.

According to the second method for testing a semiconductor memory device, for example, after performing a data write operation on the first semiconductor memory device according to the present invention in the first mode of the test mode, Since data is read in the normal mode, which is the state 2, the peripheral circuits such as the sense amplifier circuit can be simultaneously screened.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a block configuration of a semiconductor memory device according to one embodiment of the present invention. As shown in FIG. 1, for example, 256 word lines WLm (where m = 0, 1, 2, 2,
..., 255. ) And 256 bit line pairs BL
m, / BLm, each word line WLm and each bit line pair B
At the intersection of Lm and / BLm, a memory cell array 14 including memory cells 13 provided in a matrix and having a storage capacity of 64 kbits is provided.

In this specification, a symbol "/" added before a signal name indicates a complementary value of the signal or a signal which becomes significant (active) at a low level.

One end of each word line WLm receives row (row) address decode signals / RD0 to / RD63 and word line drive signals WD0 to WD3, and receives the row address decode signals / RD0 to / RD63. A word line driver 15 for selectively driving 256 word lines WLm is connected.

One end of each bit line pair BLm, / BLm is provided for each bit line pair BLm, / BLm, and amplifies the potential difference between the potentials read out for each bit line pair BLm, / BLm. A sense amplifier array 16 for determining each data value is connected.

The sense amplifier array 16 receives a plurality of word line rise test mode switching signals AWL as an inspection mode control signal and an internal column (column) address signal, decodes the internal column address signal, and decodes each bit line pair BLm. , / BLm, and a column selection circuit for performing data I / O with the outside, and a column decoder and selector 17 as a test bit line selection means are connected.

On the other hand, the word line driver 15 has row address predecode signals XPA0 to XPA7, XPB0.
XPB7 to row address decode signal / RD0
To / RD63 are connected.

Each of the row decoders 18 has one terminal connected to a row address predecode signal XPA0 to XPA0.
7, one of XPB0 to XPB7 is input and the other terminal is supplied with a plurality of word line rising test mode switching signal AWL. Control circuit 19 is connected.

The control circuit 19 for raising a plurality of word lines receives internal row address signals AX0 to AX7 and receives row address predecode signals XPA0 to XPA7, XPB.
0 to XPB7 are connected to the row predecoder 20. The row predecoder 20 receives external row address signals A0 to A7 and receives an internal row address signal AX.
An address buffer 21 for generating 0 to AX7 is connected.

Between the row predecoder 20 and the word line driver 15, four terminals each having one terminal receiving the word line drive timing control signal WD and the other terminal receiving the row address predecode signal. Is connected to a word line drive signal generation circuit 22 composed of an AND circuit.

The column decoder / selector 17 receives a write control pulse WRUN, is connected to a read / write amplifier 23 for writing or reading data, and receives column address signals A0 to A7 from outside, and A column address buffer for generating a column address signal and a column predecoder 24 are connected.

The timing generation circuit 25 generates a row address strobe signal RA as a trigger for starting a memory operation.
S, a column address strobe signal CAS serving as a trigger for a read operation, a write enable signal WE for restricting a write operation permission state or a prohibition state, and an output enable signal OE for permitting or prohibiting read data output operation to the outside It outputs a word line drive timing control signal WD or an internal write enable signal WEN.

The delay control circuit 26 receives the word line drive timing control signal WD, generates a first delay time (normal delay time) T1, and a second delay time (inspection time). Delay circuit 262 as a test delay time generating means for generating a delay time
Receiving the delayed word line drive timing control signals WD from the delay circuit 261 and the second delay circuit 262, and selects one of them based on a plurality of word line start-up test mode switching signals AWL, and senses the selected signal. First selector 263 that outputs as amplifier drive signal SE
It is composed of

The write control pulse width switching circuit 27 as a write control means receives the internal write enable signal WEN and generates a third delay (time) T3, a third delay circuit 271 and a fourth delay (Time) Fourth delay circuit 272 for generating T4 and third delay circuit 27
Upon receiving the delayed internal write enable signal WEN from the first and fourth delay circuits 272, one of them is selected based on the multiple word line rise test mode switching signal AWL, and the selected signal is written into the write control pulse WRU.
And a second selector 273 for outputting N.

Between the delay control circuit 26 and the sense amplifier array 16 receiving the sense amplifier drive signal SE from the delay control circuit 26, one input terminal receives the sense amplifier drive signal SE, and the other input terminal A sense amplifier disable control circuit 28 at the time of a write operation as sense amplifier amplification inhibiting means for receiving the inverted write control pulse WRUN and outputting a sense amplifier drive signal SE is connected.

FIG. 2 shows a circuit configuration of the word line driver 15 and the row decoder 18 in the semiconductor memory device according to the present embodiment. As shown in FIG. 2, the word line driver 15 has a unit word line driver 15a provided for each word line WLm.

Each unit word line driver 15a has a p-type transistor having an input terminal connected to any one of row address decode signals / RD0 to / RD63 and an output terminal connected to any one of word lines WLm. It has a first inverter 151 composed of TP1 and a first n-type transistor TN1. The drive voltage supply terminals of the first inverter 151 of the 256 unit word line drivers 15a are connected to the word line drive signal WD0, respectively.
To WD3 so as to be repeated in this order.

Each unit word line driver 15a has one of the word line drive signals WD0 to WD3 whose drain is connected to the word line WLm, whose source is grounded, and whose gate is inverted by the second inverter 152. It has a second n-type transistor TN2 that receives one.

The row decoder 18 is composed of 64 unit row decoders 18a, and each unit row decoder 18a has eight row address predecode signals XPA0 to XPA7, XPB0 from the row predecoder 20 respectively.
To XPB7, one of the 64 combinations is input, and the row address decode signal / R
It has a NAND gate 181 that outputs any one of D0 to / RD63. For example, a unit row decoder 18 that receives row address predecode signals XPA0 and XPB0 and outputs a row address decode signal / RD0
a outputs the row address decode signal / RD0 to four unit word line drivers 15a connected to the word lines WL0 to WL3, receives the row address predecode signals XPA1 and XPB0, and outputs the row address decode signal / RD1. Is output from the unit row decoder 18a.
The row address decode signal / RD1 is applied to the word line WL4
To the four unit word line drivers 15a connected to .about.WL7.

FIG. 3 shows a circuit configuration of the memory cell array 14, the sense amplifier row 16, the column decoder 17, and the read / write amplifier 23 in the semiconductor memory device according to the present embodiment. As shown in FIG. 3, in the memory cell array 14, memory cells 13 each including a memory cell capacitor MC and a memory cell access transistor TWL are arranged in a matrix.

In the memory cell 13, for example, the memory cell access transistor TWL has a drain connected to the bit line BL0, a gate connected to the word line WL1, and a source connected to one electrode of the memory cell capacitor MC. , The other electrode of the memory cell capacitor MC is connected to a cell plate power supply VCP having a voltage value that is a half of the power supply voltage VDD.

The sense amplifier array 16 includes a sense amplifier drive circuit 161, a sense amplifier 162, and a bit line precharge circuit 163.

In the sense amplifier drive circuit 161, the gate receives the inverted signal of the sense amplifier drive signal SE, the source receives the power supply voltage VDD, and the drain is each sense amplifier 16.
2, a p-type sense amplifier driver transistor TPSE that supplies a power supply voltage VDD to each sense amplifier 162, a gate receives the sense amplifier drive signal SE, a source receives the ground voltage VSS, and a drain is each sense amplifier driver TPSE. 162, and an n-type sense amplifier driver transistor TNSE that supplies the ground voltage VSS to each sense amplifier 162.

The sense amplifier 162 includes a first inverter including a first p-type sense amplifier transistor TPSm and a first n-type sense amplifier transistor TNSm;
A second inverter including a second p-type sense amplifier transistor TPSmN and a second n-type sense amplifier transistor TNSmN is configured to be flip-flop connected.

The output terminal of the first inverter is a bit line B
L, and the output terminal of the second inverter is connected to the bit complementary line / BL.
From 61, the power supply voltage V is applied to each of the p-type transistors TPSm and TPSmN of the first inverter and the second inverter.
DD is supplied, and the ground voltage VSS is supplied to each of the n-type transistors TNSm and TNSmN of the first inverter and the second inverter.

The bit line precharge circuit 163 has a source and a drain connected to the bit line pair BLm and / BLm, a gate receiving the bit line precharge signal BP at the gate, a bit line equalizing transistor TNEQm, and a bit line pair BLm and / BLm. , A common drain is connected to a bit line precharge power supply VBP having a voltage value of one half of the power supply voltage VDD, and a first bit line receiving a bit line precharge signal BP at each gate is provided. It comprises a precharge transistor TNPRm and a second bit line precharge transistor TNPRmN.

The column decoder / selector 17 has one source / drain connected to the bit line BLm, the other source / drain connected to the data line DL used for reading or writing data, and the gate receiving the column predecode signal. A first column switch transistor TNCm connected to the gate 17a, one source and drain are connected to the bit complementary line / BLm, and the other source and drain are connected to a data complementary line / DL used for reading or writing data; The gate comprises a second column switch transistor TNCmN connected to an AND gate 17a for receiving a column predecode signal.

The read / write amplifier 23 is connected to the data line pair DL, / DL, amplifies the data read to the data line pair DL, / DL, and amplifies the I / O buffer circuit 29.
Is connected to the I / O buffer circuit 29, and the amplified write data is output to the data line pair DL and / DL via an n-type switch transistor controlled by the write control pulse WRUN. And an amplifier 23b.

Hereinafter, the operation of the semiconductor memory device configured as described above will be described with reference to the drawings.

FIGS. 4 and 5 are operation timing charts of the semiconductor memory device according to the present embodiment. FIG. 4 shows a normal write operation, and FIG. 5 shows a test operation.

(Normal Write Operation) A normal write operation will be described with reference to FIGS.

First, as shown in FIG. 4, in the normal mode, a plurality of word line start-up test mode switching signals A
WL is always at a low level. Here, among the signal names shown in FIG. 4, the signal names surrounded by a frame indicate that the signals are input from the outside.

Next, row address strobe signal / RA
When S is activated by falling, the row address signals A0 to A7 are fetched, and the internal row address signals AX0 to AX7 are output from the address buffer 21 to the row predecoder 20 shown in FIG. The row predecoder 20 receiving the internal row address signals AX0 to AX7
Each of eight types of row predecode signals XPA0 to XPA0
One signal is selected from each of XPA7 and XPB0 to XPB7 and output to row decoder 18.

As shown in FIG. 2, the row decoder 18
Upon receiving the selected row predecode signal and selecting one of the 64 unit word line drivers 18a, 64 row address decode signals / RD0 are provided.
To / RD63, and outputs the signal value to the word line driver 15 as an active low level.

On the other hand, the timing generation circuit 25 shown in FIG.
The word line drive signal generation circuit 22 which receives the word line drive timing control signal WD from the row and the selection signal from the row predecoder 20 outputs four word line drive signals WD0
~ WD3 is selected and activated,
As a result, one of the word lines WLm is selected and activated. As a result, as shown in FIG. 3, the 256 memory cells 13 connected to one selected word line WL in the memory cell array 14 are held in the memory cell capacitors MC of the memory cells 13 respectively. The data of the minute potential is transferred to each bit line BLm and bit complementary line / BLm connected to the memory cell 13.

Next, as shown in FIG. 4, the sense amplifier drive signal SE rises after a first delay time T1 from the word line drive timing control signal WD. In the delay control circuit 26 shown in FIG. 1, the first selector 263 that receives the low-level plural word line rise test mode switching signal AWL outputs the output signal of the first delay circuit 261. Generated by selection.
When the sense amplifier drive signal SE is activated, as shown in FIG. 3, the sense amplifier drive circuit 161 of the sense amplifier row 16 receiving the sense amplifier drive signal SE is activated, and each bit line pair BLm, / BLm is activated. Is connected to each bit line pair BLm, / BL
Data read every m is amplified to determine a value. Thereby, the bit line pair BL of each memory cell 13
The read operation to m, / BLm is completed.

Next, as shown in FIG. 4, the write enable signal / WE falls to bring the write enable state. Subsequently, the column address strobe signal / CAS falls and is activated to take in the column address signals A0 to A7, and the column address buffer and the column predecoder 24 shown in FIG. 1 are activated. Subsequently, one bit line pair BL, // designated by the address is designated by the column decoder and selector 17 shown in FIG.
BL is selected.

Next, as shown in FIGS. 1 and 4, the timing generation circuit 25 receiving the activated write enable signal / WE outputs the internal write enable signal WE.
N is output, and the write control pulse WRUN is generated only during the third delay time T3 from the rise of the internal write enable signal WEN. This third delay time T3
Is a write control pulse width switching circuit 27 shown in FIG.
, The third selector 271 receiving the low-level multiple word line rising test mode switching signal AWL
Is generated by selecting the output signal of the third delay circuit 271 side. Subsequently, as shown in FIG. 3, predetermined write data Din is input to the selected bit line pair BLm, / BLm through the write amplifier 23b while the write control pulse WRUN is being generated.

At this time, as shown in FIG. 1, the sense amplifier disable control circuit 28 during the write operation prohibits the output of the sense amplifier drive signal SE while the write control pulse WRUN is activated. The drive signal SE becomes inactive during the generation of the write control pulse WRUN. As a result, the sense amplifier array 16 and the write amplifier 23b are not activated at the same time, so that the data write operation can be performed even in the case of the inversion write in which the complementary value of the read data is written. Can be performed in a short time.

(Test Operation) Next, a test operation performed by simultaneously activating a plurality of word lines will be described with reference to FIGS.

First, as shown in FIG. 5, the operation mode of the device is transited to the test mode by raising and activating the multiple word line rise test mode switching signal AWL.

Next, row address strobe signal / RA
S is activated to take in the row address signals A0 to A7, and the internal address signals AX0 to AX are sent from the address buffer 21 to the row predecoder 20 shown in FIG.
7 is output. At this time, each of the row predecode signals XPA0 to XPA7 and XPB0 to XPB7 is activated by the multiple word line rise control circuit 19 which receives the high level multiple word line rise test mode switching signal AWL. Thereby, row address decode signal / RD in row decoder 18 shown in FIG.
All of 0 to / RD63 become low level and are activated and input to the word line driver 15.

At this time, internal word line drive signals WD0 to WD0
When one signal of WD3 is selected, 25
One quarter of the six word lines WLm, that is, 64
Are selected simultaneously, and the selected 64 word lines WL
Are transferred to each bit line pair BLm and / BLm. That is,
64 memory cells 1 are connected to a pair of bit lines BL and / BL.
3 will be read simultaneously.

In this case, the word line drive signals WD0 to WD
Since one of the three drives 64 word lines WL, the rise time of the word lines WL is longer than in the normal mode. In order to secure the rise time of the word line WL in the test mode, the present embodiment employs a delay control circuit 26 for generating the sense amplifier drive signal SE shown in FIG.
In the test mode, this is realized by selecting an output signal from the second delay circuit 262 that generates a second delay time longer than the first delay time T1 in the test mode.

Next, as shown in FIG. 5, the write enable signal / WE falls to bring the write enable state. Subsequently, the same data read and write operations as described above are performed by the column address strobe signal / CAS signal.

Here, since the multiple word line rise test mode switching signal AWL is in an active state, regardless of the values of externally applied column address signals A0 to A7, FIG.
Through the column decoder and selector 17 shown in FIG.
All of the paired bit lines BLm and / BLm are simultaneously selected. A configuration for realizing this can be easily realized by incorporating a control circuit (not shown) having an OR gate similar to the control circuit 19 for raising a plurality of word lines into the column address buffer and the column predecoder 24.

In this way, one write data Din is developed at the time of the write operation, and two write data Din selected at the same time are selected.
A write operation is performed on all 56 bit line pairs BLm and / BLm. Further, as a feature of the present embodiment, the write control pulse width switching circuit 27 for generating the write control pulse WRUN shown in FIG. 1 generates a fourth delay time T4 longer than the third delay time T3 in the test mode. By selecting the output signal from the fourth delay circuit 272 side and making the pulse width of the write control pulse WRUN longer than in the normal mode, the write operation margin for the 256 pairs of bit lines BLm and / BLm can be reduced. It secures and makes writing easy.

As described above, according to the present embodiment, (1) the number of word lines WL activated in the test mode is 64 times that in the normal mode, The same stress as in the mode can be applied in 1/64 time. In the present embodiment, 256 word lines WLm
64 (64/256) are selected at the same time, but four word line drive signals WD0
To WD3 at the same time, the number of activated word lines WLm becomes 12 compared to that in the normal mode.
As a result, the stress time equivalent to that in the normal mode can be further halved, that is, the time can be easily reduced to 1/128.

(2) Stress can be easily applied between the word lines WL as compared with the stress applying method of activating all the word lines WLm at once. For example, the word line drive signals WD0 to WD3 are sequentially activated in each operation cycle, and a total of 64 word lines WL are selected out of 256 word lines WLm per cycle. By doing so, the unselected word lines WL adjacent to each of the activated word lines WL can be deactivated, so that stress can be reliably applied to the mutually adjacent word lines WL.

(3) Plural bit line pairs BLm and / BLm
Of the bit lines BLm and / BLm and each memory cell 1
Third, stress can be applied to each sense amplifier 162 in a very short time.

As shown in this embodiment, 256 pairs of bit lines BLm and / BL
It is preferable to select all m at once, but it is not always necessary to select all the bit line pairs BLm and / BLm at the same time in consideration of the capability of the write circuit and the like.

(4) By providing the delay control circuit 26, the write control pulse width switching circuit 27, and the write operation sense amplifier disable control circuit 28, a plurality of bit line pairs BLm and / BLm in the test mode are provided.
Read operation and write operation can be performed stably.

First, the delay control circuit 26 sets the second delay amount T2 during the test operation for the sense amplifier drive signal SE.
Is made larger than the first delay amount T1 in the normal mode, the rising operation of the plurality of word lines WL, which requires more time than in the normal mode, the activation operation of the sense amplifier 162 and each memory Since an operation margin can be secured for the data read operation from the cell 13 to each bit line pair BLm, / BLm, the amplification operation of each sense amplifier 162 can be stabilized.

The write pulse width switching control circuit 27 sets the active period T4 of the write control pulse WRUN during the test operation to be longer than the active period T2 during the normal mode, so that the plurality of bit line pairs BLm and / BLm
, A stable write operation can be guaranteed.

Further, at the time of write operation, the sense amplifier disable control circuit 28 controls the sense amplifier 1 during write operation.
62 and the write amplifier 23b are simultaneously activated, that is, the pair of bit lines BLm and / BL amplified by the sense amplifier 162 even during inversion writing.
As compared with the method of forcibly rewriting the read data of m by the write amplifier 23b, even if the size of the write amplifier 23b is reduced or its capability is reduced, the writing operation can be performed in a short time and stably. It is advantageous for conversion.

As described above, according to the present embodiment, in the test mode, the efficiency of stress application is greatly improved as compared with that in the normal mode. Screening of a leak system between word lines WL and screening of a sense amplifier 162 and a bit line BL system, which cannot be obtained by a method such as batch activation of all word lines, can be performed, so that deterioration in quality can be suppressed.

Further, by combining the write operation in the test mode and the read operation in the normal mode according to the present embodiment, the test of the memory cell array 14 can be performed in a very short time, and can be used for monitoring such as burn-in inspection. In addition, the inspection time can be shortened also in the inspection of the device after the wafer inspection or the package sealing.

(First Modification of Embodiment) Hereinafter, a first modification of the embodiment of the present invention will be described with reference to the drawings.

FIG. 6 shows a block configuration of a semiconductor memory device according to a first modification of the embodiment of the present invention. FIG.
In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Only differences from FIG. 1 will be described.

In FIG. 1, the word line drive signal generating circuit 22 outputs four systems of word line drive signals WD0 to WD3. However, in this modification, as shown in FIG. The signals are two systems WD0 and WD1. Further, the row predecoder 20 includes row address predecode signals XPA0 to XPA7, XPB0 to XB0.
By outputting signals of 18 systems of PB7, XPC0, and XPC1, the row decoder 18 generates 128 row address decode signals / RD0 to / RD127.

More specifically, as shown in FIG. 7, each unit row decoder 18a of the row decoder 18 according to the present modification example
Are two NAND gates 182 having three input terminals
Respectively. For example, among the plurality of unit row decoders 18a, the row address predecode signal XPA
NAND gate 18 receiving 0, XPB0 and XPC0
Numeral 2 outputs a row address decode signal / RD0, which is the result of the operation of the input signal, to two unit word line drivers 15a in the word line driver 15 at the same time.

As described above, in one operation cycle,
Since the number of activated word lines WLm is 128, the inspection efficiency at the time of stress application such as burn-in inspection is further improved.

(Second Modification of Embodiment) Hereinafter, a second modification of the embodiment of the present invention will be described with reference to the drawings.

FIG. 8 shows a block configuration of a semiconductor memory device according to a second modification of the embodiment of the present invention. FIG.
In FIG. 7, the same components as those shown in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted. Only differences from FIG. 1 will be described. As shown in FIG. 8, a 2-bit counter 31 as internal address generating means for outputting 2-bit data of AX0 and AX1 of the internal row address signals AX0 to AX7 to the row predecoder 20 and a multiple word line rise test A selector 32 is provided for selecting and outputting the output signal of the 2-bit counter 31 and the 2-bit data AX0 and AX1 output from the address buffer 21 based on the mode switching signal AWL.

Here, 2-bit counter 31 operates in a test mode in which a plurality of word lines WL are simultaneously activated.
The output value of the 2-bit counter 31 is used as an internal address. Thereby, 2 from the 2-bit counter 31
The word line drive signal generation circuit 22 receiving the bit data AX0 and AX1 selects one of the word line drive signals WD0 to WD3 and 64 word lines out of the 256 word lines WLm. WL is activated at the same time.

As described above, according to the present modification, in the test mode, the internal address is output from the 2-bit counter 31 and the high-level row address pre-predecode signals XPA0 to XPA are all supplied to the row decoder 18.
Since A7 and XPB0 to XPB7 are input, the external address signals A0 to A7 do not need both the row address and the column address. As a result, the number of control pins from the outside during a stress test such as a burn-in test can be reduced, so that the measurement system can be simplified.

Note that the 2-bit counter 31 has a normal D
An 8-bit counter for circulating all of the row addresses used for a refresh operation or the like in the RAM device, and the two bits on the LSB side are used as word line drive signals WD0 to WD0.
It is good also as a structure allocated to selection of D3.

[0093]

According to the semiconductor memory device of the present invention,
In the test mode, the word line driving circuit includes word line selecting means for selecting a plurality of word lines at predetermined intervals and driving a plurality of word lines in one operation cycle. Word lines adjacent to each of the plurality of driven word lines are not driven. As a result, the same stress as in the normal operation is applied between the selected word line and the unselected word line. Further, since a plurality of word lines are selected in one cycle of a write cycle or a read cycle, the time required for screening all word lines can be reduced. In addition, since the inspection bit line selecting means selects a plurality of bit line pairs among a large number of bit line pairs in one operation cycle, it is possible to apply stress to the bit lines and to the sense amplifier in a short time. Become like Therefore, stress similar to that during normal operation can be applied while significantly shortening the stress time for the burn-in test and the like, so that the test efficiency of the semiconductor memory device can be improved.

In the semiconductor memory device of the present invention, the timing at which the word line selected by the test word line selecting means is activated and the timing at which the bit line pair selected by the test bit line selecting means is activated are determined. And a test delay time generating means for generating a test delay time for providing a delay between the test time and the test delay time generating means. If it is set to be longer than the normal delay time for providing a delay between the timing of activation and the timing of the activation of the bit line pair selected by the column selection circuit, the number of operations is increased as compared with the normal operation. Sufficient operation margin is required between the rising operation of multiple word lines, which requires time, and the operation of reading data from sense amplifiers and memory cells to bit line pairs. Since it coercive, the read operation stabilizes.

If the semiconductor memory device of the present invention further comprises sense amplifier amplification inhibiting means for inhibiting the amplification operation of the sense amplifier circuit during the write operation, the amplification operation of the sense amplifier is inhibited during the write operation. For example, as compared with a case where a write amplifier for data writing is operated while a sense amplifier is activated, even if the driving capability of the write amplifier is reduced, the writing time does not greatly decrease, which is advantageous in layout.

The semiconductor memory device of the present invention further comprises write control means for outputting a write control pulse for controlling whether or not to input write data to the column selection circuit. When the pulse width of the write control pulse is set so that the pulse width of the write control pulse is larger than the pulse width of the write control pulse in the normal mode, the active period of the write control pulse in the test mode is longer than in the normal operation. Therefore, the write operation on the plurality of bit line pairs is further stabilized.

If the semiconductor memory device of the present invention further comprises an internal address generating means for receiving a test mode control signal and internally generating a row address signal, no external address signal is required in the test mode. The number of external control terminals can be reduced, and as a result, measurement can be facilitated and the device can be simplified.

In the semiconductor memory device according to the present invention, the internal address generating means outputs the internally generated row address signal instead of the externally applied row address signal in the test mode.
When the word lines selected every predetermined number out of a large number of word lines are alternately output, the number of external control pins during the stress application test can be reduced, so that the measurement system can be simplified.

According to the first semiconductor memory device testing method of the present invention, in the test mode, the word lines adjacent to each of the plurality of word lines driven in the test mode are not driven. The same stress as in normal operation is applied between the word line and the unselected word line. Furthermore, since a plurality of word lines are selected in one cycle of a write cycle or a read cycle, the time for performing screening for all word lines can be reduced, so that the efficiency of inspection can be improved.

According to the second method for inspecting a semiconductor memory device of the present invention, the same effect as that of the first method for inspecting a semiconductor memory device can be obtained. After that, the data is read in the normal mode in the second state, so that peripheral circuits such as the sense amplifier circuit can be simultaneously screened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a semiconductor memory device according to one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a word line driver and a row decoder of the semiconductor memory device according to one embodiment of the present invention.

FIG. 3 is a circuit diagram showing a memory cell array, a sense amplifier array, a column decoder, and a read / write amplifier of the semiconductor memory device according to one embodiment of the present invention.

FIG. 4 is a timing chart showing a normal write operation of the semiconductor memory device according to one embodiment of the present invention.

FIG. 5 is a timing chart showing a test operation of the semiconductor memory device according to one embodiment of the present invention.

FIG. 6 is a block diagram showing a semiconductor memory device according to a first modification of one embodiment of the present invention.

FIG. 7 is a circuit diagram showing a word line driver and a row decoder of a semiconductor memory device according to a first modification of the embodiment of the present invention.

FIG. 8 is a block diagram showing a semiconductor memory device according to a second modification of the embodiment of the present invention.

[Explanation of symbols]

WL word line BL bit line / BLm complementary bit line 13 memory cell 14 memory cell array 15 word line driver (word line drive circuit) 15a unit word line driver 151 first inverter 152 second inverter 16 sense amplifier train 161 sense amplifier drive Circuit 162 Sense amplifier 163 Bit line precharge circuit 17 Column decoder and selector (inspection bit line selecting means) 17a AND gate 18 Row decoder 18a Unit row decoder 181 NAND gate 182 NAND gate 19 Control circuit for starting multiple word lines (inspection Word line selecting means) 20 row predecoder 21 address buffer 22 word line drive signal generation circuit 23 read / write amplifier 23a read amplifier 23b write amplifier 24 column Dress buffer and column predecoder 25 Timing generation circuit 26 Delay control circuit 261 First delay circuit 262 Second delay circuit (test delay time generation means) 263 First selector 27 Write control pulse width switching circuit (Write control means) 271 Third delay circuit 272 Fourth delay circuit 273 Second selector 28 Sense amplifier disable control circuit during write operation (Sense amplifier amplification inhibiting means) 29 I / O buffer circuit 31 2-bit counter (Internal address generating means) 32 selector AWL Multiple word line rise test mode switching signal (test mode control signal) / RAS row address strobe signal / CAS column address strobe / WE write enable signal OE output enable signal A0-A7 row address Signals A0 to A7 Column address signals AX0 to AX7 Internal row address signals XPA0-7 Row address predecode signals XPB0-7 Row address predecode signals XPC0,1 Row address predecode signals / RD0 / RD63 Row address decode signals / RD0 / RD127 Row address decode signal WD Word line drive timing control signal WEN Internal write enable signal WRUN Write control pulse SE Sense amplifier drive signal

Claims (9)

[Claims] A plurality of pairs of word lines and a plurality of bit lines intersecting each other; and a plurality of memory cells provided in a matrix at each intersection of the plurality of word lines and the plurality of bit line pairs. A memory cell array, a word line driving circuit that receives a row address signal and selectively drives the plurality of word lines based on the received row address signal; and a bit line pair provided for each of the plurality of bit line pairs. A sense amplifier circuit for amplifying a potential difference between the plurality of bit line pairs, receiving a column address signal, selecting one of the plurality of bit line pairs based on the received column address signal, and inputting / outputting data to / from the outside. Receiving a test mode control signal and selecting the word line drive circuit so that the word line drive circuit can drive a plurality of word lines at predetermined intervals and in one operation cycle for the plurality of word lines. Receiving the inspection mode control signal, selecting a plurality of bit line pairs of the plurality of bit line pairs in one operation cycle, and selecting the selected plurality of bit line pairs. A semiconductor memory device comprising: a test bit line selecting means for inputting / outputting data. 2. A delay between a timing when a word line selected by the test word line selecting means is activated and a timing when a bit line pair selected by the test bit line selecting means is activated. And a test delay time generating means for generating a test delay time for providing the test delay time, wherein the test delay time generating means activates the test delay time by a word line selected by the word line drive circuit. A delay time between the activation timing and the activation timing of the bit line pair selected by the column selection circuit is set to be longer than a normal delay time for providing a delay. 2. The semiconductor memory device according to 1. 3. The semiconductor memory device according to claim 1, further comprising sense amplifier amplification inhibiting means for inhibiting an amplification operation cycle of said sense amplifier circuit during a write operation. 4. A write control unit for outputting a write control pulse for controlling whether or not to input write data to the column selection circuit, wherein the write control unit is configured to perform the write control pulse in a test mode. 2. The semiconductor memory device according to claim 1, wherein the pulse width of the write control pulse is set so that the pulse width of the write control pulse is larger than the pulse width of the write control pulse in the normal mode. 5. The semiconductor memory device according to claim 1, further comprising an internal address generating means for receiving the test mode control signal and internally generating a row address signal. 6. The internal address generating means, in a test mode, outputs a row address signal generated internally instead of an external row address signal among the plurality of word lines.
6. The semiconductor memory device according to claim 5, wherein the output is performed such that the word lines selected every predetermined number are sequentially changed. 7. The semiconductor memory device according to claim 1, further comprising an external terminal receiving said test mode control signal. 8. A large number of word lines and a large number of bit line pairs intersecting each other, and a large number of memory cells provided in a matrix at each intersection of the large number of word lines and the large number of bit lines. A test method for a semiconductor memory device including a memory cell array, wherein in a test mode, a plurality of word lines selected in a predetermined number of ones of the plurality of word lines and in one operation cycle are sequentially replaced. A method for testing a semiconductor memory device, wherein the word line is driven. 9. A plurality of word lines and a plurality of bit line pairs crossing each other, and a plurality of memory cells provided in a matrix at each intersection of the plurality of word lines and the plurality of bit line pairs. A memory cell array, a word line driving circuit that receives a row address signal and selectively drives the plurality of word lines based on the received row address signal; and a plurality of bit line pairs provided for each of the plurality of bit line pairs. A sense amplifier circuit for amplifying the potential difference between the bit line pair and a column selecting signal receiving and receiving a column address signal, selecting one of the plurality of bit line pairs based on the received column address signal, and inputting / outputting data to / from the outside. Receiving a circuit and a test mode control signal, selecting the word line drive circuit so as to be able to drive a plurality of word lines at predetermined intervals and in one operation cycle for the plurality of word lines. Receiving a test word line selecting means, receiving the test mode control signal, selecting a plurality of bit line pairs among the plurality of bit line pairs in one operation cycle, and setting data to the selected plurality of bit line pairs. A test bit line selecting means for performing input / output of the semiconductor memory device, wherein when the test mode control signal is in a first state, the test word line selecting means is used. A first step of selecting a plurality of word lines at predetermined intervals for a large number of word lines and in one operation cycle; and in the case of the first state, using the inspection bit line selecting means. A second step of selecting a plurality of bit line pairs of the plurality of bit line pairs in one operation cycle and writing data to the memory cell through the selected plurality of bit line pairs; and Two A third step of selecting one of the plurality of bit line pairs using the column selection circuit in the state, and a potential difference of the selected bit line pair in the second state. Reading out the written data by amplifying the data by using the sense amplifier circuit.