JPH0955475A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make up a part which can be easily programmed so as to decrease a program voltage by a method wherein a lower conductive wiring layer is formed on a first insulating film on a semiconductor substrate, and an anti-fuse is provided onto the stepped part of the lower conductive wiring layer. SOLUTION: A gate insulting film 102 is formed on a semiconductor substrate 101, and a gate electrode 104 is formed through the intermediary of the gate insulating film 102. An oxide film 103 is formed on the side wall of the gate electrode 104, and a lower conductive wiring layer 106 is formed above the gate electrode 104 through the intermediary of a first insulating film 105. Furthermore, a second insulating film 107 and an upper conductive wiring layer 109 are formed, and a connection hole is bored to connect the lower conductive wiring layer 106 to the upper conductive wiring layer 109, and amorphous silicon 108 is deposited inside the connection hole between the stepped part of the lower conductive wiring layer 106 and the upper conductive wiring layer 109 through a chemical vapor growth method for the formation of an anti-fuse. Therefore, a part which can be easily programmed is formed, whereby a program voltage can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to antifuse formation for semiconductor devices.

[0002]

2. Description of the Related Art FIG. 7 shows a conventional structure for forming an antifuse used as a small capacity ROM on a semiconductor substrate.

A gate insulating film 102 is formed on a semiconductor substrate 101.
The gate electrode 104 is formed through. Further, the gate side wall 103 is formed. Then, via the first insulating film 105,
A lower conductive wiring layer 106 is formed on the upper portion thereof. Further, a second insulating film 107 and an upper conductive wiring layer 109 are formed, and a connection hole portion for connecting the lower conductive wiring and the upper conductive wiring layer is provided, and the lower conductive wiring layer of the connection hole portion is formed. Amorphous silicon 1 between the upper conductive wiring layer
The fuse is formed by depositing 08 by a chemical vapor deposition method. In the past, when forming a fuse, no particular limitation was placed on the shape of the underlying lower conductive wiring layer.

[0004]

The conventional techniques have the following problems.

As described in the prior art, the antifuse has been formed so far regardless of the location in the chip and the shape of the base. As a problem that occurs in that case, when there is a step in the underlying lower conductive wiring layer, the depth of the connection hole is different between the upper part and the lower part of the step. When etching contact holes with different depths, the etching time is set according to the depth of the contact holes, so the surface of the lower conductive wiring layer is slightly scraped off by etching in the shallow contact holes, which results in shallow contact. The fuse shape differs between the fuse formed in the hole and the fuse formed in the deep connection hole. In addition, a step may be formed on the lower conductive wiring layer of the base, and a fuse may be formed at the step, and in that case, the shape is naturally different from that of the fuse formed on the flat part of the base. If the shape of the fuse is different, the value of the program voltage will be different, and the way of variation will also be different.

In this case, the following will be mentioned as a problem. When the program voltage is high, the resistance after writing the data becomes high, and the migration resistance becomes poor. Further, if the program voltage varies, the resistance after data writing also varies. Therefore, the present invention solves such a problem, and an object of the present invention is to suppress the program voltage to a low level and to suppress the variation in the program voltage by forming a part that is easily broken by an antifuse, that is, a part that is easily programmed. An object of the present invention is to provide a semiconductor device that can be manufactured.

[0007]

A semiconductor device according to the present invention comprises a lower conductive wiring layer formed on a first insulating film on a semiconductor substrate, a second insulating film formed on the lower conductive wiring layer, An upper conductive wiring layer formed on a second insulating film and a connection hole for connecting the upper layer and the lower conductive wiring layer are provided, and the connection hole is sandwiched between the upper conductive wiring layer and the lower conductive wiring layer. In the semiconductor device in which the amorphous silicon is deposited as described above to form the antifuse, the antifuse is formed only in the step portion of the lower conductive wiring layer.

A lower conductive wiring layer formed on the first insulating film on the semiconductor substrate, a second insulating film formed on the lower conductive wiring layer, and an upper conductive wiring formed on the second insulating film. Layer and a connection hole for connecting the upper layer and the lower conductive wiring layer, amorphous silicon is deposited in the connection hole so as to be sandwiched between the upper conductive wiring layer and the lower conductive wiring layer, and an anti-fuse In the semiconductor device for forming the semiconductor device, polycrystalline silicon is partially deposited between the first insulating film and the lower conductive wiring layer to form a step at a position where a fuse is desired to be formed, and an insulating film is formed on the polycrystalline silicon. The lower conductive wiring layer is provided with a step.

[0009]

1 is a sectional view of a first embodiment of the present invention.
Shown in 101 is a semiconductor substrate, 102 is a gate insulating film,
103 is a gate side wall, 104 is a gate electrode, 105 is a first insulating film, 106 is a lower conductive wiring layer, 107 is a second insulating film, 108 is amorphous silicon, and 109 is an upper conductive wiring layer.

A gate insulating film 102 is formed on a semiconductor substrate 101.
And forming the gate electrode 104 through the gate insulating film.
To form Further, an oxide film 103 is formed on the side wall of the gate. Then, the lower conductive wiring layer 106 is formed on the first insulating film 105 with the first insulating film 105 interposed therebetween. Furthermore, the second insulating film 1
07, the upper conductive wiring layer 109 is formed, and has a connection hole portion for connecting the lower conductive wiring and the upper conductive wiring layer, and the lower conductive wiring layer and the upper conductive wiring layer are provided in the connection hole portion. A fuse is formed by depositing the amorphous silicon 108 by a chemical vapor deposition method.

Next, a manufacturing method of the first embodiment according to the present invention will be described with reference to FIGS.

First, the gate oxide film 1 is formed on the semiconductor substrate 101.
02 is formed by a silicon oxide film with a thickness of 150 to 200Å,
On top of that, polycrystalline silicon is deposited by chemical vapor deposition and molybdenum silicide is deposited by 2000Å.
Then, the gate electrode 104 is formed by photolithography and etching. After that, a silicon oxide film is deposited on the entire surface to about 2000 to 4000 Å, and RIE is performed.
It is also necessary to form the side wall 103 of the gate electrode by etching by (Reactive Ion Eching). FIG. 2 shows this state.

Thereafter, a first insulating film composed of a silicon oxide film and a BPSG film is formed to a thickness of about 10000 Å, and a lower conductive wiring layer is formed by sputtering, photo and etching.
FIG. 3 shows this state.

Further, a second insulating film made of NSG film is formed. When forming the second insulating film, first, 4000 to 60
00Å deposit and then apply eg organic SOG,
It is advisable to flatten the surface by etching back or the like and then further deposit an NSG film of 5000 to 6000 Å. After that, a connection hole for forming a fuse is formed by isotropic wet etching or anisotropic dry etching. At that time, the connection hole is formed in a step portion of the lower conductive wiring layer. In that case, the connection hole is formed by a step due to the polycrystalline silicon, or a Locos (Local oxidati) formed by selective oxidation for electrically isolating the element.
A hole is formed on a step formed by on of silicon or a step formed by forming the polycrystalline silicon on the Locos. FIG. 4 is a diagram showing this state.

Amorphous silicon is deposited on the entire surface, and photolithography and etching are performed so that the amorphous silicon remains only under the connection holes. After that, an upper conductive wiring layer is formed by the same method as that for forming the lower conductive wiring layer. FIG. 5 shows this state.

The above is the manufacturing method of the first embodiment of the present invention.

Next, FIG. 6 shows a sectional view of a semiconductor device according to a second embodiment of the present invention. A manufacturing method according to the second embodiment of the present invention will be described.

The steps up to the formation of the first insulating film are the same as in the first embodiment. Polycrystalline silicon is formed on the entire surface of the first insulating film by a chemical vapor deposition method, and the polycrystalline silicon is partially left by photo and etching to form a step. Further, an insulating film is formed on it. Then, a lower conductive wiring layer is formed, and the subsequent steps are the same as those in the first embodiment.

In this case, the lateral distance between the edge of the polycrystalline silicon and the edge of the contact hole may be shifted from each other by about 0.5 μm on the left and right with the edge of the polycrystalline silicon as the center. FIG. 8 shows a sectional view of a semiconductor device when a fuse is formed on a flat base, and FIG. 9 is a sectional view of a semiconductor device when a fuse is formed on a base having a step. FIG.
Shows the program voltage value in both cases. As shown in FIG. 10, the program voltage is 7 to 8 V when the base is stepped, whereas the program voltage is 7.5 to 9.5 when the base is flat and the base is stepped. The program voltage is lower when the fuse is formed on the
Variations are also suppressed.

The fuse must be formed on the step portion, which limits the place where the fuse is formed. However, in the conventional product, the fuse is formed on the place where the base is flat according to the design rule. Therefore, it is considered that forming the fuse only in a place where the base has a step does not pose a problem.

By forming the fuse only in the step portion of the lower conductive wiring layer as in the above embodiment, an acute angle portion is formed in the fuse, and the electric field is concentrated in the acute angle portion, so that the break easily occurs. By forming the portion that is easily broken in this way, it is possible to suppress variations in the program voltage. Further, since one fuse is always provided with one selection transistor for each step, it is possible to utilize the step due to the gate electrode of the transistor, and it is not necessary to form the step.

[0022]

According to the present invention described above, it is possible to suppress the program voltage of the antifuse in the semiconductor device in which the antifuse is formed on the semiconductor substrate, and to suppress the variation in the program voltage.

[Brief description of drawings]

FIG. 1 is a sectional view showing a first embodiment of a semiconductor device of the present invention.

FIG. 2 is a cross-sectional view for explaining the first embodiment of the method of manufacturing a semiconductor device according to the present invention in the order of steps.

FIG. 3 is a cross-sectional view for explaining the first embodiment of the method of manufacturing a semiconductor device of the present invention in process order.

FIG. 4 is a cross-sectional view for explaining the first embodiment of the method of manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 5 is a cross-sectional view for explaining the first embodiment of the method of manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 6 is a sectional view showing a second embodiment of the semiconductor device of the present invention.

FIG. 7 is a sectional view showing a conventional structure of the present invention.

FIG. 8 is a sectional view of a semiconductor device according to the present invention.

FIG. 9 is a sectional view of a semiconductor device according to the present invention.

FIG. 10 is a graph showing a difference in program voltage depending on the shape of a fuse.

[Description of Reference Signs] 101 semiconductor substrate 102 gate oxide film 103 gate sidewall 104 gate electrode 105 first insulating film 106, 203 lower conductive wiring layer 107, 204 second insulating film 108, 205 amorphous silicon 109, 206 upper conductive wiring layer 201 Polycrystalline silicon 202 Interlayer insulating film

Claims (3)

[Claims] 1. A lower conductive wiring layer formed on a first insulating film on a semiconductor substrate, a second insulating film formed on the lower conductive wiring layer, and an upper conductive layer formed on the second insulating film. A wiring layer and a connection hole for connecting the upper layer and the lower conductive wiring layer are provided, and amorphous silicon is deposited in the connection hole so as to be sandwiched between the upper conductive wiring layer and the lower conductive wiring layer. In a semiconductor device for forming a gap, an antifuse is provided at a step portion of the lower conductive wiring layer. 2. A selection transistor for selecting the antifuse, wherein a part of the lower conductive wiring layer is arranged on the gate of the selection transistor to form the step. The semiconductor device described. 3. A step of forming a first insulating film on a semiconductor substrate, a step of forming a first conductive wiring layer on the first insulating film, and a step of forming a first conductive wiring layer on the first conductive wiring layer. A step of forming a second insulating film, a step of forming a second conductive wiring layer on the second insulating film, and a step of forming the first conductive wiring layer on the step portion of the first conductive wiring layer. A method of manufacturing a semiconductor device, comprising: a step of providing a connection hole for connecting to the second conductive wiring layer; and a step of providing an antifuse in the connection hole.