JPH0955092A - Applying method for operation pulse and generating circuit for operation pulse of non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the distribution of threshold value of a memory cell in narrow without degradation of the boosting efficiency of a charge pump circuit by applying a pulse train pulse a steps type pulse and having repetition of two times or more of the same voltage value. SOLUTION: A multiplexer 12 selects successively one signal voltage out of a group of signal voltage having different values generated by each step of a charge pump circuit 11 by a control signal from a shift register of a pulse controller 13, and outputs a signal S12 of a step-wise waveform. A pulse controller 14 inputs the signal S12, generates at least two pulses or more for one step of an input voltage value, and supplies an output signal S14 to a memory cell as a writing pulse or an erasing pulse. Thereby, distribution of threshold values of a memory cell can be controlled in narrow without degradation of boosting efficiency of the charge pump circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to EPROM, EE
The present invention relates to an electrically rewritable semiconductor non-volatile memory such as a PROM, and particularly to an operation pulse applying method and an operation pulse generating circuit thereof.

[0002]

2. Description of the Related Art Among semiconductor non-volatile memories, there are EPROMs or EEPROMs having a floating gate type, MNOS type, or MONOS type memory cell structure.
In such non-volatile memory, when writing and erasing are performed by taking in and out charges through a thin insulating film, application of stepped pulses that gradually increase the voltage value is advantageous for deterioration of the insulating film.

When the information of the memory cell is changed to data of "1" to "0" or "0" to "1" by charging and discharging charges, in general, a pulse train having the same voltage value is applied. However, in this case, as shown in FIG. 5A, since the high electric field E is applied in the first several pulses, the insulating film is easily deteriorated. On the other hand, in the stepwise pulse, such a high electric field is not applied as shown in FIG.

FIG. 6 shows an example of the relationship between the threshold voltage Vth of the memory cell and the pulse application time t when a stepped pulse is applied. In FIG. 6, the reason why the threshold voltage Vth is not a smooth curve but is gradually changed is that the pulse voltage value is gradually increased. When operating the nonvolatile memory at a low voltage, it becomes necessary to control the distribution of the write threshold voltage Vth and the erase threshold voltage Vth to be narrow. In that case, it is necessary to reduce the difference between the voltage values of the stepwise adjacent pulses to reduce the fluctuation value of the threshold voltage Vth per step which is stepwise in FIG.

FIG. 7 is a circuit diagram showing an example of a circuit for generating the stepped pulse. The stepwise pulse generation circuit 10 is configured to generate voltage values having different stepwise pulse values from each stage of a so-called charge pump circuit.

Specifically, a plurality of diodes D ₁ , D ₂ , ..., Dn, Dn + 1, ..., Dm-, which are n-channel MOS transistors whose gates and drains are connected to each other, are formed.
1, Dm (m> n) are connected in series in m stages, and these connection nodes N ₁ , N ₂ , ..., Nn, Nn + 1, ..., Nm-1,
Every other Nm is a capacitor C ₁ , C ₂ , ...,
, Cm-1, Cm are connected to the input lines of the clock signal φ and its inverted clock signal / φ. Then, each connection node N ₁ , N ₂ , ..., N
The voltages of n, Nn + 1, ..., Nm-1, Nm are output through the waveform shaping diode DO.

In such a structure, boosting of the nodes N _{1 to} Nm is sequentially performed by capacitive coupling of the capacitors C _{1 to} Cm based on inputs of clock signals φ and / φ having complementary levels. , Voltage values having different stepped pulse values are generated from the respective stages, and these signal voltages are output through the waveform shaping diode DO.

Here, in order to reduce the difference between the voltage values of the adjacent stages of the charge pump 11, it is necessary to reduce the boosted voltage per one stage of the charge pump. To this end, the capacitance C is made smaller or the clock amplitude Vφ is made smaller, as can be derived from the equation of the boosted voltage per stage shown below, which is considered based on the n, n + 1 stage boosted portion shown in FIG. Alternatively, it is necessary to increase the threshold voltage Vth of the transistor forming the diode.

[0009]

## EQU1 ## (Vn + 1−Vn) ∝ {C / (C + Cs)} Vφ−Vth

[0010]

However, reducing the capacitance C leads to a reduction in boosting current and boosting efficiency, and reducing the clock amplitude Vφ and increasing the threshold voltage Vth lowers the boosting efficiency. Invite. Therefore, it is difficult to reduce the difference between the voltage values of the adjacent pulses in the stepwise shape for controlling the narrow threshold voltage Vth distribution, because it causes a decrease in the boosting current and boosting efficiency of the charge pump.

The present invention has been made in view of the above circumstances, and an object thereof is a semiconductor nonvolatile memory capable of controlling a threshold distribution of memory cells to be narrow without reducing the boosting efficiency of a charge pump circuit. To provide an operation pulse applying method and an operation pulse generating circuit.

[0012]

In order to achieve the above object, the present invention is a method for applying an operation pulse to a semiconductor non-volatile memory for applying a predetermined pulse train to a memory cell, which is used for writing or erasing information. , A step-like pulse that gradually increases the voltage value, and 2 at the same voltage value
A pulse train having a repetition of at least one time is applied.

Further, the present invention is an operation pulse generation circuit of a semiconductor nonvolatile memory for generating a stepwise pulse and supplying it to a memory cell, wherein a charge pump circuit for generating a signal voltage having a different value, and a control signal for a control signal. 1 out of the signal voltage group generated from each stage of the charge pump circuit according to the input
A selection circuit that selects and outputs only one signal voltage and the control signal that causes the selection circuit to output a voltage that is at least one step higher when the number of repetitive pulses with the same voltage value of the staircase pulse is counted. A first pulse controller for outputting to the selection circuit, and a first pulse controller for receiving an output signal voltage of the selection circuit and generating one or more pulses for one input voltage value stage and supplying the pulse to the memory cell. 2 pulse controllers.

According to the operation pulse applying method of the present invention, a write pulse or an erase pulse for a memory cell of a semiconductor non-volatile memory is a step-like pulse for gradually increasing the voltage value, and at the same voltage value. A pulse train having two or more repetitions of is applied. As a result, it becomes possible to control the threshold voltage distribution of the memory cell to be narrow without reducing the difference between the voltage values of the adjacent steps of the staircase pulse. Moreover, the boosting current and boosting efficiency of the charge pump circuit that generates the voltage value of the stepwise pulse do not decrease.

Further, according to the operation pulse generating circuit of the present invention, in the charge pump circuit, signal voltages having different values which are the origins of the stepwise pulses are generated from the respective boosting stages, and these signal voltages are outputted to the selecting circuit. It In the first pulse controller, when the number of repetitive pulses of the same voltage value of the staircase pulse is counted, a control signal is generated and output to the selection circuit so that the selection circuit next outputs a voltage of a value one step higher. It In the selection circuit, only one signal voltage is selected from the input signal voltage group generated from each stage of the charge pump circuit, and the signal having the stepwise waveform is output to the second pulse controller. Then, the second pulse controller receives the output signal voltage of the selection circuit, generates at least one pulse for at least one stage of the input voltage value, and supplies the pulse as a write pulse or an erase pulse to the memory cell. To be done. Thus, as the write pulse or the erase pulse, a pulse train that is a stepwise pulse that gradually increases the voltage value and that is repeated twice or more with the same voltage value is applied.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an example of a stepwise operation pulse generation circuit of a semiconductor nonvolatile memory according to the present invention. This step-like pulse generating circuit 10a is shown in FIG.
As shown in, the charge pump circuit 11, the multiplexer 12, the first pulse controller 13, and the second pulse controller 14 are included.

The charge pump circuit 11 has the same circuit configuration as the circuit configuration shown in FIG. 7, the clock signal phi taking complementary levels, based on input / phi, the capacitor C ₁
Sequentially performs boosting of the node N ₁ to NM by capacitive coupling ～Cm, node Nn, Nn + 1, ..., generating Nm-1, different signal voltages the underlying value of the step-like pulses from each stage of Nm Then, the waveform is shaped by the diode DO and the multiplexer 12 is used.
Output to

The multiplexer 12 selects only one signal voltage from the input signal voltage group generated from each stage of the charge pump circuit 11 and outputs it as the signal S12 to the second pulse controller 14. This multiplexer 12
The output signal S12 has a stepwise waveform.

The multiplexer 12 has its gate line controlled, for example, by the output control signal of the first pulse controller 13, and its output side is wired-OR. The number of transmission gates 121n, 121n + corresponding to the number of outputs of the charge pump circuit 11 is wired. 1, ..., 121m-1, 121m
When all the gate line groups controlled by the first pulse controller 13 are "0 (low level)", the multiplexer 1
A NOR circuit 122 for setting two outputs to “0”, and a gate connected to a connection point on the output side (wired OR) of the transmission gate group and the ground line, the gate of which is the NOR circuit 1.
It is composed of an n-channel MOS transistor 123 connected to the output of 22.

The first pulse controller 13 is
For example, it is composed of an n-ary counter 131 and a shift register 132.
Is made. Specifically, the pulse enable signal PE is set to n
Clock CK of the base counter 131 ₁And n-ary coun
N of the data 131 is repeated with the same voltage value of the stepped pulse
It is set to be the same as the number of pulses. n-ary counter 131
Carry signal Carry OUT of the shift register 132
CK₂Becomes Shift register according to this clock
Is Q_A, ... in sequence (high level (H) control signal
Output. Each output of the shift register 132 is directly or
Via the inverters INVn to INVm
The transmission gates 121n to 121 in the service 12
It is an input to each gate of m. To the multiplexer 12
Then, the shift register 132 controls the transformers in sequence.
By opening the mission gates 121n-121m
The stepwise waveform is output.

That is, the first pulse controller 13
Controls so that the multiplexer 12 can output a voltage one step higher when counting the number n of repetitive pulses of the staircase pulse at the same voltage value. When generating a normal step-like pulse, n in the first pulse controller 13
The advance counter 131 is omitted, and the pulse enable signal P
Let E be the clock CK _{2 of the} shift register 132 directly.

The second pulse controller 14 receives the stepwise waveform signal S12 from the multiplexer 12,
An actual staircase pulse applied to a memory cell (not shown) is output. Specifically, by outputting one pulse or two or more pulses for one stage of the input voltage value to the second pulse controller 14, it is a normal step pulse or a step pulse, and the same voltage value. Generate a pulse train having more than two repetitions of. The output pulse S14 from the second pulse controller 14 becomes a write pulse or an erase pulse applied to the memory cell.

The pulse controller 14 is connected between the transmission gate 141 controlled by the pulse enable signal PE, for example, and the output of the transmission gate 141 and the ground line, and the pulse enable signal PE is inverted at the gate by the inverter INV. It is configured by an n-channel MOS transistor 142 to which a signal (one gate input of the transmission gate) is input. The pulse enable signal PE becomes a signal synchronized with the output pulse S14 of the pulse controller 14.
FIG. 2 shows an example of the waveform of the output signal S14 of the pulse controller 14.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. Note that, here, the n-ary counter 13 of the first pulse controller 13
1 will be described as a ternary counter.

In the charge pump circuit 11, based on inputs of clock signals φ and / φ having complementary levels,
Due to the capacitive coupling of the capacitors C _{1 to} Cm, each node N ₁ to
Nm is stepped up sequentially, and nodes Nn, Nn + 1, ..., N
Signal voltages having different values which are the origins of the staircase pulses are generated from the respective m-1 and Nm stages, and these signal voltages are fed to the diode D.
The waveform is shaped by O and output to the multiplexer 12.

In the first pulse controller 13, ternary
In the counter 131, as shown in FIG.
Carrier pulse (Carry OU)
T) pulse is generated. This carryout pulse
It is supplied to the shift register 132 as a clock. So
Then, in the shift register 132, the input clock
Depending on the output Q _AHigh-level control signals in order from
Signal is output to the multiplexer 12.

In the multiplexer 12, the output control signal of the first pulse controller 13 becomes an input to each gate of the transmission gates 121n to 121m. Accordingly, in the multiplexer 12, the transmission gates 1 are sequentially controlled by the shift register 132.
21n to 121m open, and only one signal voltage is selected from the input signal voltage group generated from each stage of the charge pump circuit 11, and the signal S12 having a stepwise waveform is output to the second pulse controller 14.

The second pulse controller 14 outputs one pulse or two or more pulses for one input voltage value stage based on the input of the pulse enable signal PE, thereby generating a normal step pulse or step pulse. A pulse train that is present and has two or more repetitions with the same voltage value is generated, and this pulse train S14 is supplied to a memory cell (not shown) as a write pulse or an erase pulse.

As described above, for a memory cell of a semiconductor nonvolatile memory, a write pulse or an erase pulse is a stepwise pulse that gradually increases the voltage value and is repeated twice or more at the same voltage value. Pulse train S14 having
By applying, it is possible to control the threshold voltage Vth distribution of the memory cell to be narrow without decreasing the boosting efficiency of the charge pump circuit 11.

The reason why the repetitive pulse train is given twice or more instead of once at one voltage value of the stepwise pulse is as follows. That is, the boosting voltage per one stage of the charge pump is set to a value that ensures an appropriate boosting current and boosting efficiency, and is not set to a small value forcibly. By using such a charge pump, the difference in voltage value between the adjacent steps of the staircase pulse is not reduced. However, if this is left as it is, the variation value of the threshold voltage Vth per stage, which is stepwise as shown in FIG. So, one of the staircase pulse
If a repetitive pulse train is applied twice or more at one voltage value instead of once, the threshold voltage Vth fluctuation value between these pulses becomes small. Specifically, as shown in FIG. 2, at each voltage value of the stepped pulse, a pulse train that is repeated twice or more with the same voltage value is given. As a result, the threshold voltage Vth distribution of the memory cell can be controlled to be narrow without reducing the difference between the voltage values of the adjacent steps of the staircase pulse. Moreover, the boosting current and boosting efficiency of the charge pump that generates the voltage value of the stepwise pulse do not decrease.

FIG. 4 shows the relationship between the threshold voltage Vth of the memory cell and the pulse application time t when such a pulse is applied. FIG. 4 shows an example in which a pulse train repeated four times with the same voltage value is applied, and the black dot portion is the threshold voltage Vth for each pulse.

[0032] As described above, according to this embodiment, the stepped pulse generating circuit 10a, the clock signal phi taking complementary levels, based on input / phi, the capacitor C ₁ -C
The nodes N _{1 to} Nm are sequentially boosted by capacitive coupling of m, and signal voltages having different values which are the source of the staircase pulse are generated from the stages of the nodes Nn, Nn + 1, ..., Nm-1, Nm. The charge pump circuit 11, the multiplexer 12 that selects only one signal voltage from the input signal voltage group generated from each stage of the charge pump circuit 11 and outputs it as the signal S12, and the repetition of the staircase pulse with the same voltage value When the pulse number n is counted, the pulse controller 13 that controls the multiplexer 12 to output a voltage that is at least one step higher next, and the stepwise waveform signal S12 from the multiplexer 12 are input, and the input voltage value for one step is increased. By outputting one or more pulses, it is a normal step pulse or a step pulse and is repeated twice or more at the same voltage value. And a pulse controller 14 for generating a pulse train having the following, and the output pulse S14 of the pulse controller 14 is supplied to the memory cell as a write pulse or an erase pulse. The distribution of cells can be controlled narrowly.

Further, the above stepped pulse generation circuit 10a
Of the charge pump circuit 11 and multiplexer 1
2. Since all of the pulse controllers 13 and 14 can be manufactured by the MOS process, there is an advantage that they can be mounted on the same chip as that on which the memory array is mounted.

[0034]

As described above, according to the present invention,
It is possible to control the distribution of the memory cells to be narrow without reducing the boosting current and boosting efficiency of the charge pump circuit. Also,
A known charge pump circuit or multiplexer capable of producing by a MOS process a circuit that generates a normal staircase pulse that gradually increases the voltage value or a pulse train that is a staircase pulse and has two or more repetitions at the same voltage value. Can be realized by using. Therefore, it can be mounted on the same chip on which the memory array is mounted.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a stepwise pulse generation circuit of a semiconductor nonvolatile memory according to the present invention.

FIG. 2 is a diagram showing an example of a stepped pulse according to the present invention.

FIG. 3 is a timing chart for explaining the operation of FIG. 1;

FIG. 4 is a diagram showing the relationship between the threshold voltage of a memory cell and the pulse application time when a stepped pulse according to the present invention is applied.

FIG. 5 is a diagram showing an example of a general write (erase) pulse and stepwise pulse.

6 is a diagram showing the relationship between the threshold voltage of the memory cell and the pulse application time when the stepped pulse shown in FIG. 5 is applied.

FIG. 7 is a circuit diagram showing a configuration example of a charge pump circuit.

8 is an explanatory diagram of a boosted voltage per one stage of the charge pump circuit of FIG. 7. FIG.

[Explanation of symbols]

 10a ... Stepped pulse generation circuit 11 ... Charge pump circuit 12 ... Multiplexer 121n-121m ... Transmission gate 122 ... NOR circuit 123 ... N channel MOS transistor 13 ... First pulse controller 131 ... N-ary counter 132 ... Shift register 14 ... 2 pulse controller 141 ... Transmission gate 142 ... N-channel MOS transistor

Claims (2)

[Claims] 1. A method for applying an operation pulse to a semiconductor non-volatile memory, wherein a predetermined pulse train is applied to a memory cell, which is a stepwise pulse that gradually increases a voltage value when writing or erasing information, and A method for applying an operation pulse to a semiconductor nonvolatile memory, which applies a pulse train having two or more repetitions at the same voltage value. 2. An operation pulse generation circuit for a semiconductor non-volatile memory which generates a stepwise pulse and supplies it to a memory cell, the charge pump circuit generating a signal voltage having a different value, and a control signal depending on an input of a control signal. The selection circuit that selects and outputs only one signal voltage from the signal voltage group generated from each stage of the charge pump circuit and the above selection when the number of repetitive pulses of the same voltage value of the stepped pulse is counted A first pulse controller that outputs the control signal to the selection circuit so that the circuit outputs a voltage having a value higher by at least one stage; and a pulse for an input voltage value of one stage by receiving the output signal voltage of the selection circuit. And a second pulse controller for generating one or more of the above and supplying them to the memory cell.