JP2011004452A - Power circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal power circuit which suppresses a voltage ripple within a semiconductor device, that is, power noise, which arises when the internal power circuit operates, regardless of the transmission frequency of an oscillator that the internal power circuit has.SOLUTION: A power circuit is provided with: an oscillator which outputs a pulse signal whose level changes in preset cycles; a plurality of boosting circuits which boost power voltages inputted from outside according to the pulse signal that the oscillator outputs; and a control circuit which selects whether to input the pulse signal into each of the plurality of boosting circuits according to a change in the pulse signal that the oscillator outputs.

Description

  The present invention relates to a power supply circuit that boosts and outputs an input voltage.

  Some semiconductor devices have a processing circuit that requires a voltage different from the voltage of a power supply to be supplied. A semiconductor device includes an internal power supply circuit (boost circuit) that boosts the voltage of a power supply supplied to supply power to the processing circuit, thereby driving the processing circuit without preparing a plurality of voltages externally. Are used (Patent Document 1, Patent Document 2).

  FIG. 11 is a schematic block diagram showing a configuration of the semiconductor device 9 formed on, for example, a semiconductor chip. The semiconductor device 9 is supplied with power from an external DC power supply 8 provided outside. The semiconductor device 9 also includes a processing circuit 90 that performs data processing in the semiconductor device 9 and an internal power supply circuit 91 that boosts the voltage of the power supplied from the external DC power supply 8 and outputs the boosted voltage to the processing circuit 90. The processing circuit 90 and the internal power supply circuit 91 are connected to the external DC power supply 8, and the potential Vdd is applied from the positive side of the external DC power supply 8 and the potential Vss is applied from the negative side of the external DC power supply 8. Here, the semiconductor device 9 is, for example, a storage device such as a flash memory, an image processing device that converts and outputs an input image signal, and the like.

  FIG. 12 is a schematic block diagram and a circuit diagram showing the configuration of the internal power supply circuit 91. FIG. 12A is a schematic block diagram showing the configuration of the internal power supply circuit 91. The internal power supply circuit 91 includes a detection circuit 911, a reference potential output circuit 912, a comparator 913, an oscillator 914, and a booster 915.

The detection circuit 911 includes, for example, a voltage dividing circuit using resistors, and converts the output potential nVdd output from the pump circuits 915-1,... 915-m to the detection potential Va for comparison, and outputs it to the comparator 913. Output. Here, the potential nVdd indicates a potential obtained by multiplying the positive side potential Vdd of the external DC power supply 8 by n times.
The reference potential output circuit 912 outputs a reference potential Vref determined corresponding to a predetermined boost specified potential Vload to the comparator 913. Here, the boost specified potential Vload is an output potential required for the internal power supply circuit 91. Further, the reference potential Vref is determined corresponding to the boost specified potential Vload (specified potential), and is determined to match the detection potential Va when the output potential nVdd matches the boost specified potential Vload.

  The comparator 913 compares the detection potential Va output from the detection circuit 911 with the reference potential Vref output from the reference potential output circuit 912 when an H (High) level boost start signal is input from the outside, and detects the detection potential. When Va is equal to or lower than the reference potential Vref, the oscillator 914 performs control to output the pulse signal Tos. When the detection potential Va is higher than the reference potential Vref, the oscillator 914 performs control to stop outputting the pulse signal Tos. Here, when the boosting start signal is at the H level, the internal power supply circuit 91 is instructed to start the boosting operation. When the boosting start signal is at the L (Low) level, the internal power supply circuit 91 is instructed to stop the boosting operation. Signal.

The oscillator 914 is, for example, a ring oscillator in which a plurality of inverters are connected in series. When an H level boost start signal is input from the outside, the oscillator 914 continuously oscillates in response to the control signal Compout output from the comparator 913. Tos is output to the booster 915.
The booster 915 has a plurality of pump circuits 915-1,... 915-m, boosts the potential Vdd supplied from the external DC power supply 8 by the pulse signal Tos output from the oscillator 914, and outputs the boosted voltage to the processing circuit 90. To do. The plurality of pump circuits 915-1,..., 915-m have the same configuration, and the circuit configuration of the pump circuit 915-1 is described instead of the description of all the circuits, and the other circuits are described. Omitted.
For example, the number of pump circuits included in the booster 915 is determined according to the amount of charge supplied by each pump circuit, the load and power consumption of the processing circuit 90, and is formed into an IP (Intellectual Property) module. It is configured by combining pump circuits. At this time, one pump circuit is also called one part.

FIG. 12B is a circuit diagram showing a configuration of the pump circuit 915-1. The pump circuit 915-1 is a Dickson type booster circuit as shown in the figure, and includes n diodes 93-1,..., 93-n and diodes 93-1,. n corresponds to a connection point between n, and one end of the capacitors 94-1,..., 94- (n-1) connected to the connection point, and a pulse input from the oscillator 914 (FIG. 12A) And an inverter 95 for inverting the signal CK.
A positive potential Vdd is applied from the external DC power supply 8 (FIG. 11) to the anodes of the diodes 93-1 of the first stage of the diodes 93-1,..., 93-n connected in series. The boosted output potential nVdd is output from the diode 93-n at the final stage of the diodes 93-1, ..., 93-n connected in series. An input pulse signal CK and an inverted pulse signal obtained by inverting the pulse signal CK by the inverter 95 are alternately input to the other ends of the capacitors 94-1,..., 94- (n−1).

  The pump circuit 915-1 configured as described above moves the charge accumulated in the adjacent capacitor via the diodes 93-1,..., 93-n each time the potential of the input pulse signal CK changes. Each time it moves between the capacitors, the potential rises according to the amount of change in the potential of the pulse signal CK, and an output potential nVdd obtained by boosting the potential Vdd supplied from the diode 93-n at the final stage is output.

  FIG. 13 is a waveform diagram showing the operation of the internal power supply circuit 91. The vertical axis direction represents the level, voltage value, or current value of each signal, and the horizontal axis direction represents time. As shown in the figure, when an H level boost start signal is input from the outside at time t0 (operation of the semiconductor device 9), the comparator 913 causes the detection potential Va output from the detection circuit 911 and the reference potential output circuit. The control signal Compout for outputting the pulse signal Tos to the oscillator 914 is output when the reference potential Vref output from the reference numeral 912 is compared and when it is detected that the detection potential Va is lower than the reference potential Vref. At this time, as the detection potential Va, a potential corresponding to the initial value (0 V) output from the booster 915 is output.

  In the period from time t0 to time t1, the pump circuits 915-1,..., 915-m included in the booster 915 receive the potential Vdd supplied from the external DC power supply 8 in accordance with the pulse signal Tos output from the oscillator 914. The voltage is boosted and the boosted output potential nVdd is output.

  When the output potential nVdd becomes higher than the boost specified potential Vload at time t1, the detection potential Va output from the power supply detection circuit 911 becomes higher than the reference potential Vref. When the comparator 913 detects that the detection potential Va is higher than the reference potential Vref, the comparator 913 outputs a control signal Compout that causes the oscillator 914 to stop outputting the pulse signal Tos. The oscillator 914 stops outputting the pulse signal Tos according to the control signal Compout output from the comparator 913. The booster 915 stops boosting when the output of the pulse signal Tos is stopped. When the booster 915 stops boosting, the output potential nVdd gradually decreases as the potential nVdd boosted by the DC current path of the detection circuit 911, the processing circuit 90, and the like. When the output potential nVdd of the internal power supply circuit 91 becomes lower than the boost specified potential Vload, the detection potential Va output from the detection circuit 911 becomes lower than the reference potential Vref.

  At time t2, when the comparator 913 detects that the detection potential Va is lower than the reference potential Vref, the comparator 913 outputs a control signal Compout that causes the oscillator 914 to output the pulse signal Tos. The oscillator 914 outputs the pulse signal Tos to the booster 915, and the pump circuits 915-1,... 915-m included in the booster 915 are supplied from the external DC power supply 8 according to the pulse signal Tos output from the oscillator 914. The supplied potential Vdd is boosted, and the boosted output potential nVdd is output.

  When the comparator 913 detects that the detection potential Va is higher than the reference potential Vref at time t3, the comparator 913 outputs a control signal Compout that causes the oscillator 914 to stop outputting the pulse signal Tos. The oscillator 914 stops outputting the pulse signal Tos according to the control signal Compout output from the comparator 913, and the booster 915 stops boosting when the output of the pulse signal Tos is stopped.

At time t4, the internal power supply circuit 91 operates similarly to the above-described time t2, and at time t5, the internal power supply circuit 91 operates similarly to the above-described time t3.
After time t1, the above-described operation from time t1 to time t3 is repeated according to the change in the output potential nVdd until the boost start signal becomes L level. As shown in the drawing, a current Idd flows every time the internal power supply circuit 91 performs a boosting operation.
Further, the operation state of the internal power supply circuit 91 from time t0 to time t1 is referred to as a boosting operation state, and the state of the internal power supply circuit 91 after time t1 is referred to as a post-boosting potential maintaining state.

  FIG. 14 is a schematic diagram showing the influence caused by the operation of the internal power supply circuit 91 in the semiconductor device 9. In the semiconductor device 9 including the internal power supply circuit 91 configured as described above, when the internal power supply circuit 91 operates, the current Idd flows through the internal power supply circuit 91 and the voltage applied to the processing circuit 90 varies. In particular, when the internal power supply circuit 91 starts its operation (in FIG. 13, time t0, t2, t4), the voltage applied to the processing circuit 90 changes greatly.

  FIG. 15 is a waveform diagram showing changes in the current Idd flowing in the internal power supply circuit 91 and the supplied voltage Vdd1 and the voltage Vdd2 supplied to the processing circuit 90 when the internal power supply circuit 91 operates. In FIG. 15, the vertical axis indicates the current value and the voltage value, and the horizontal axis indicates the time. As shown in the figure, the internal power supply circuit 91 starts boosting, and a current Idd is generated between the internal power supply circuit 91 and the external DC power supply 8 (FIG. 11). At this time, the voltage supplied to the internal power supply circuit 91 is lowered by the parasitic resistance of the wiring connecting the internal power supply circuit 91 and the external DC power supply 8. In the example illustrated in FIG. 15, the voltage Vdd1 decreases from 3V to 2.75V. Further, the voltage Vdd2 applied to the processing circuit 90 changes due to a steep change in which the current Idd starts to flow through the internal power supply circuit 91. In the example shown in FIG. 15, the potential Vdd2 increases from 3V to about 3.125V.

  As described above, all of the pump circuits 915-1,..., 915-m included in the internal power supply circuit 91 start the boosting operation all at once, so that the voltage applied to the processing circuit 90 varies in the positive direction (noise). ) Occurs. Further, all of the pump circuits 915-1,..., 915-m included in the internal power supply circuit 91 stop the boosting operation all at once, thereby causing a negative fluctuation (noise) in the voltage applied to the processing circuit 90. . Thus, noise is generated in the internal power supply of the semiconductor device 9 due to the start and stop of the internal power supply circuit 91.

Here, the current Idd flowing through the internal power supply circuit 91 is expressed as follows using the current Io output from the internal power supply circuit 91.
Here, the input potential of the internal power supply circuit 91 is set to the positive potential Vdd of the external DC power supply 8, and the output potential of the internal power supply circuit 91 is set to a potential nVdd obtained by boosting the potential Vdd by n times. Further, the electric power Pi input to the internal power supply circuit 91 and the electric power Po output from the internal power supply circuit 91 are expressed as the following equations (A-1) and (A-2).
Pi = Vdd * Idd (A-1)
Po = nVdd * Io (A-2)

From Pi = Po,
Vdd * Idd = nVdd * Io
Idd = n · Io
It becomes. That is, the current Idd that flows through the internal power supply circuit 91 flows n times as much as the output current Io that is output to the processing circuit 90, so that the operation of the internal power supply circuit 91 fluctuates to the voltage applied to the processing circuit 90. It is one of the factors that give

FIG. 16 is a schematic diagram illustrating changes in the potential Vdd2 applied to the processing circuit 90. When the internal power supply circuit 91 starts the boosting operation, the current Idd flowing through the internal power supply circuit 91 rises sharply, and the potential difference ΔV (with respect to the parasitic resistance R of the wiring connecting the internal power supply circuit 91 and the external DC power supply 8 is increased. = R * ΔIdd). At this time, the positive potential Vdd applied to the processing circuit 90 rises due to the capacitive coupling of the processing circuit 90 to the parasitic capacitance Cs.
Here, ΔIdd represents the amount of change in the current Idd flowing through the internal power supply circuit 91 in the time interval Δt.

FIG. 17 is a schematic diagram showing the arrangement of the processing circuit 90 and the internal power supply circuit 91 on the semiconductor substrate P_sub. In the region where the internal power supply circuit 91 is configured, an N-type semiconductor N_Well1 is formed on the surface of the P-type semiconductor substrate P_sub, and a P-type semiconductor P_Well1 is formed on the surface of the N_Well1. Internal power supply circuit 91 includes a P-type transistor configured on N_Well1 and an N-type transistor configured on P_Well1. On the other hand, in the region where the processing circuit 90 is configured, as in the region where the internal power supply circuit 91 is configured, the N-type semiconductor N_Well2 is formed on the surface of the P-type semiconductor substrate P_sub, and the P-type semiconductor is formed on the surface of the N_Well2. P_Well2 is formed. The processing circuit 90 includes a P-type transistor configured on the N_Well2 and an N-type transistor configured on the P_Well2.
In order to suppress a change in potential applied to the processing circuit 90 by the current Idd flowing through the internal power supply circuit 91, a power supply circuit 8b for supplying power to the internal power supply circuit 91 and a power supply to the processing circuit 90 are shown as shown in the figure. Even if the power supply circuit 8a is separated, the potential Vss on the negative electrode side becomes common and the influence cannot be suppressed.

  FIG. 18 is a schematic block diagram showing the configuration of an internal power supply circuit 91a including six pump circuits 915-1,... 915-6, and a waveform diagram showing the operation. As shown in FIG. 18 (a), the internal power supply circuit 91a is shown in FIGS. 12 (a) and 12 (b), except that the booster 915a has six pump circuits 915-1,. It has the same configuration as that of the internal power supply circuit 91, and the corresponding portions are denoted by the same reference numerals and description thereof is omitted. The internal power supply circuit 91a includes a booster 915a instead of the booster 915, and the booster 915a includes six pump circuits 915-1, ..., 915-6.

FIG. 18B is a waveform diagram showing the operation of the internal power supply circuit 91a. The vertical axis direction represents the level, voltage value, or current value of each signal, and the horizontal axis direction represents time. As shown in the figure, when a pulse signal Tos that periodically changes is input when an H level boost start signal is input, the pump circuits 915-1,. -6 starts the boost operation. Thereby, the currents Idd_1,..., Idd_6 flowing through the pump circuits 915-1,..., 915-6 increase, and the current Idd flowing through the internal power supply circuit 91a increases sharply. Although not shown, when the internal power supply circuit 91a stops the boosting operation, all the pump circuits 915-1,... 915-6 stop all at once, and the pump circuits 915-1,. The flowing currents Idd_1,..., Idd_6 decrease, and the current Idd flowing through the internal power supply circuit 91a decreases sharply.
As described above, when all the pump circuits 915-1,... 915-6 start and stop the voltage boosting operation at the same time, the current Idd flowing through the internal power supply circuit 91 varies steeply. This is one of the causes of fluctuation (noise) of the voltage applied to the processing circuit 90 inside.

  FIG. 19 is a graph showing a simulation result by the configuration of the internal power supply circuit 91a. FIG. 19A is a waveform diagram of the pulse signal Tos input to each of the pump circuits 915-1,. The vertical axis direction indicates the level of each signal, and the horizontal axis direction indicates time. FIG. 19B is a waveform diagram showing a current Idd flowing through the internal power supply circuit 91a. The vertical axis represents current Idd [μA], and the horizontal axis represents time. In the internal power supply circuit 91a, when an H level boost start signal is input, the oscillator 914 outputs the pulse signal Tos to the pump circuits 915-1,... 915-6, and the pump circuits 915-1,. Each of 6 performs a boosting operation according to the pulse signal Tos.

In the internal power supply circuit 91a, when a boost start signal is input, all the pump circuits 915-1,... 915-6 included in the booster 915a operate at the same time, so that the current Idd flowing through the internal power supply circuit 91a The rising edge becomes steep and is one of the factors that cause the voltage Vdd2 applied to the processing circuit 90 to fluctuate.
When the internal power supply circuit 91a stops boosting, all the pump circuits 915-1,... 915-6 stop simultaneously, so that the fall of the current Idd flowing through the internal power supply circuit 91a becomes steep, similarly. This is one of the factors that cause the voltage Vdd2 applied to the processing circuit 90 to fluctuate.

  FIG. 20 is a schematic block diagram showing a part of a configuration example of the internal power supply circuit 91b for preventing the pump circuits 915-1,... 915-6 from operating all at once as described above, and a waveform diagram showing the operation. As shown in FIG. 20A, the internal power supply circuit 91b is different in the pulse signal Tos output from the oscillator 914a and the connection between the oscillator 914a and the pump circuits 915-1,. Moreover, the internal power supply circuit 91b has the same configuration as the internal power supply circuit 91a shown in FIG. 18A except for the points described above, and the corresponding portions are denoted by the same reference numerals and description thereof is omitted. .

The oscillator 914a includes inverters 96-1, ..., 96-6, a two-input NAND gate 97, and capacitors 98-1, ..., 98-6. The inverters 96-1,..., 96-6 are connected in series in the forward direction, and the inverter 96-6 outputs an output signal to one input terminal of the NAND gate 97. Further, the output signal of the NAND gate 97 is input to the inverter 96-1. A boost start signal is input to the other input terminal of the NAND gate 97, and whether or not the oscillator 914a oscillates and outputs a pulse signal is controlled by the boost start signal.
In addition, capacitors 98-1,..., 98-6 are connected to the output terminals of the inverters 96-1,..., 96-6, and the signals output to the pump circuits 915-1 to 915-6 are stabilized. It has become.

  The inverter 96-1 outputs the output signal A to the pump circuit 915-1 as the clock signal CK. The inverter 96-2 outputs the output signal B to the pump circuit 915-2 as the clock signal CK. The inverter 96-3 outputs the output signal C to the pump circuit 915-3 as the clock signal CK. The inverter 96-4 outputs the output signal D to the pump circuit 915-4 as the clock signal CK. The inverter 96-5 outputs the output signal E to the pump circuit 915-5 as the clock signal CK. The inverter 96-6 outputs the output signal F to the pump circuit 915-6 as the clock signal CK. That is, the oscillator 914a operates the pump circuits 915-1, ..., 915-6 at different timings by outputting different internal signals as clock signals CK to the pump circuits 915-1, ..., 915-6, respectively. .

  FIG. 20B is a waveform diagram showing the operation of the internal power supply circuit 91b. The vertical axis represents the level of each signal, and the horizontal axis represents time. In the internal power supply circuit 91b, when an H level boost start signal is input from the outside, the oscillator 914a oscillates, and the output levels of the output signals A,..., F sequentially change with a delay of the gate delay ΔT. As the levels of the output signals A,..., F change, the pump circuits 915-1,.

  With the above-described configuration, the internal power supply circuit 91b operates the pump circuits 915-1,..., 915-6 at different timings, whereby the currents Idd_1 flowing through the pump circuits 915-1,. ..., Idd_6 is prevented from rising at the same time when boosting is started. Thereby, the semiconductor device 9 includes the internal power supply circuit 91b instead of the internal power supply circuit 91a, thereby suppressing the influence of the current Idd flowing through the internal power supply circuit 91b on the voltage applied to the processing circuit 90.

Japanese Unexamined Patent Publication No. 2000-040385 JP 2000-331489 A

  However, in the circuit configuration shown in FIG. 20A, the operation start timing of each of the plurality of pump circuits cannot be changed beyond the half cycle of the pulse signal output from the oscillator. Therefore, when the oscillation frequency of the oscillator is increased, the timing for starting and stopping the operation of each pump circuit becomes extremely short, and even if there is a difference in the timing for starting and stopping the operation of multiple pump circuits, This causes a sharp increase in the current flowing through the internal power supply circuit, and a sharp decrease in the current flowing through the internal power supply circuit when the boosting operation is stopped. As a result, there is a problem that power supply noise due to fluctuations in the positive direction and fluctuations in the negative direction occurs with respect to the voltage applied to the processing circuit 90.

  The present invention has been made to solve the above problems, and its object is to generate a voltage in a semiconductor device that is generated when the power supply circuit operates regardless of the oscillation frequency of the oscillator included in the power supply circuit provided in the semiconductor device. It is an object of the present invention to provide a power supply circuit that suppresses fluctuations, that is, power supply noise.

  (1) In order to solve the above problem, the present invention provides an oscillator that outputs a pulse signal whose signal level changes in a predetermined cycle, and an external input according to the pulse signal output from the oscillator. A plurality of booster circuits that boost the power supply voltage, and a control circuit that selects whether or not to input the pulse signal to each of the plurality of booster circuits in accordance with a change in the pulse signal output from the oscillator. This is a power supply circuit.

  (2) Further, according to the present invention, in the above-described invention, the control circuit has a bit corresponding to each of the plurality of booster circuits, and has a shift register that changes in response to rising of the pulse signal. In accordance with the level of each of the plurality of bits, whether or not to input the pulse signal to each of the plurality of booster circuits is selected.

  (3) Further, according to the present invention, in the above-described invention, the control circuit has a bit corresponding to each of the plurality of booster circuits, and changes according to rising or falling of the pulse signal. And selecting whether to input the pulse signal to each of the plurality of booster circuits according to the level of each of the plurality of bits.

  (4) Further, the present invention is characterized in that, in the above-described invention, a capacitor is provided having one end commonly connected to the outputs of the plurality of booster circuits and the other end grounded.

  According to the present invention, it is possible to suppress voltage fluctuation in the semiconductor device, that is, power supply noise that occurs when the internal power supply circuit of the semiconductor device operates.

1 is a schematic block diagram illustrating a configuration of a semiconductor device 100 according to a first embodiment. 1 is a schematic block diagram showing a configuration of an internal power supply circuit 1 in the present embodiment. FIG. 2 is a circuit diagram showing a configuration of a boost control circuit 16 in the present embodiment and a waveform diagram showing its operation. It is a wave form diagram which shows operation | movement of the pressure | voltage rise part 15 in this embodiment. FIG. 6 is a circuit diagram showing a configuration of a boost control circuit 16A of a second embodiment and a waveform diagram showing its operation. It is a schematic block diagram which shows the structure of the internal power supply circuit 1B of 3rd Embodiment, and the circuit diagram which shows the structure of the pressure | voltage rise control circuit 16B. It is a wave form diagram which shows operation | movement of the internal power supply circuit 1B in this embodiment. It is a graph which shows the simulation result by the structure of the internal power supply circuit 1 of 1st Embodiment. Comparison between the simulation result of the current Idd flowing through the internal power supply circuit 1 of the first embodiment and the simulation result of the current Idd when all the pump circuits included in the booster unit 15 of the internal power supply circuit 1 are started simultaneously. FIG. FIG. 3 is a waveform diagram showing a current Idd flowing through the internal power supply circuit 1 and a voltage applied to the processing circuit 2 in the first embodiment. It is a schematic block diagram which shows the structure of the semiconductor device 9 formed on a semiconductor chip. 2 is a schematic block diagram and a circuit diagram showing a configuration of an internal power supply circuit 91. FIG. 6 is a waveform diagram showing the operation of the internal power supply circuit 91. FIG. FIG. 10 is a schematic diagram showing the influence caused by the operation of internal power supply circuit 91 in semiconductor device 9; 7 is a waveform diagram showing changes in current Idd flowing in internal power supply circuit 91 and supplied voltage Vdd1 and voltage Vdd2 supplied to processing circuit 90 when internal power supply circuit 91 operates. FIG. 6 is a schematic diagram illustrating a change in potential Vdd2 applied to the processing circuit 90. FIG. It is the schematic which shows arrangement | positioning on the semiconductor substrate P_sub of the processing circuit 90 and the internal power supply circuit 91. FIG. It is the schematic block diagram which shows the structure of the internal power supply circuit 91a provided with the six pump circuits 915-1, ..., 915-6, and the wave form diagram which shows operation | movement. It is a graph which shows the simulation result by the structure of the internal power supply circuit 91a. FIG. 6 is a schematic block diagram showing a part of a configuration example of an internal power supply circuit 91b for preventing the six pump circuits 915-1,..., 915-6 from operating all at once, and a waveform diagram showing the operation.

  Hereinafter, a semiconductor device and an internal power supply circuit according to embodiments of the present invention will be described with reference to the drawings. Here, the semiconductor device is, for example, a flash memory formed on a semiconductor chip.

(First embodiment)
FIG. 1 is a schematic block diagram showing the configuration of the semiconductor device 100 according to the first embodiment. The semiconductor device 100 has an internal power supply circuit 1 (power supply circuit) and a processing circuit 2 and is connected to an external DC power supply 8. The internal power supply circuit 1 is connected to the external DC power supply 8, supplied with the positive potential Vdd and the negative potential Vss, boosts the voltage shared from the external DC power supply 8, and outputs it to the processing circuit 2. The processing circuit 2 is connected to the external DC power supply 8 and is supplied with the positive potential Vdd and the negative potential Vss, and is also supplied with the boosted potential nVdd from the internal power supply circuit 1 so that the semiconductor device 9 should perform. Signal processing.

FIG. 2 is a schematic block diagram showing the configuration of the internal power supply circuit 1 in the present embodiment. As shown, the internal power supply circuit 1 includes a detection circuit 11, a reference potential output circuit 12, a comparator 13, an oscillator 14 (oscillator), a booster 15, a boost control circuit 16 (control circuit), an internal And a capacitor 17 for smoothing the output of the power supply circuit 1.
The detection circuit 11 is, for example, a voltage dividing circuit using a plurality of resistors, converts the output potential nVdd output from the booster 15 into a detection potential Va for comparison, and outputs it to the comparator 13. Here, the potential nVdd indicates a potential obtained by multiplying the positive side potential Vdd of the external DC power supply 8 by n times.

  The reference potential output circuit 12 outputs a reference potential Vref determined corresponding to a predetermined boosting specified potential Vload to the comparator 13. Here, the boost specified potential Vload is an output potential required for the internal power supply circuit 91. Further, the reference potential Vref is determined corresponding to the boost specified potential Vload (specified potential), and is determined to match the detection potential Va when the output potential nVdd matches the boost specified potential Vload.

The comparator 13 compares the detection potential Va output from the detection circuit 911 with the reference potential Vref output from the reference potential output circuit 12 when an H (High) level boost start signal is input from the outside, and detects the detection potential. When Va is equal to or lower than the reference potential Vref, the oscillator 14 performs control to output the pulse signal Tos. When the detection potential Va is higher than the reference potential Vref, the oscillator 14 performs control to stop outputting the pulse signal Tos. Here, when the boosting start signal is at the H level, the internal power supply circuit 1 is instructed to start the boosting operation. When the boosting start signal is at the L (Low) level, the internal power supply circuit 1 is instructed to stop the boosting operation. Signal.
The oscillator 14 is, for example, a ring oscillator configured by connecting a plurality of inverters in series. When an H level boost start signal is input from the outside, a pulse oscillated in response to the control signal Compout output from the comparator 13. The signal Tos is output to the booster 15.

The booster 15 includes m pump circuits (boost circuits) 151-1, 151-2,..., 151 -m and m pump circuits provided for the pump circuits 151-1,. AND gates 152-1, 152-2, ..., 152-m. Each of the pump circuits 151-1,..., 151-m performs a boost operation by the pulse signal Tos output from the oscillator 14 and outputs an output potential nVdd boosted n times to the processing circuit (FIG. 1). Here, the pump circuits 151-1,..., 151-m have the same configuration, and further have the same configuration as the Dickson booster circuit and the pump circuit 915-1 shown in FIG. The description thereof is omitted.
The AND gates 152-1,..., 152-m mask the pulse signal Tos output from the oscillator 14 by the control signals EN1,.

The boost control circuit 16 receives the control signal Compout output from the comparator 13 as the enable signal EN and the pulse signal Tos output from the oscillator 14. Further, the boost control circuit 16 uses the input enable signal EN and the pulse signal Tos for each of the m pump circuits 151-1,. Control signals EN1,..., ENm for selecting whether to input the pulse signal Tos are output.
The capacitor 17 is a potential smoothing capacitor provided so that the load of the processing circuit 1 and the output potential nVdd output from the boosting unit 15 do not change suddenly due to fluctuations in the load.

  FIG. 3 is a circuit diagram showing a configuration of the boost control circuit 16 in the present embodiment and a waveform diagram showing its operation. As shown in FIG. 3A, the boost control circuit 16 includes flip-flops 161-1,. In the flip-flops 161-1,..., 161-m, the pulse signal Tos is input to the clock terminal CK, and the inverted enable signal EN is input to the reset terminal R. In addition, in each of the flip-flops 161-1,..., 161-m, a data input terminal D and a data output terminal Q are connected in series so as to constitute a shift register, and the data input terminal of the first stage flip-flop 161-1 Is connected to the power supply potential Vdd as an H level signal.

  In addition, each of the flip-flops 161-1,..., 161-m outputs a signal output from the data output terminal to the booster 15 as control signals EN 1,. That is, each of the flip-flops 161-1,..., 161 -m is associated with the pump circuit 151-1,. The pump circuit 151-1,..., 151-m is configured to select whether or not to input the pulse signal Tos.

  FIG. 3B is a waveform diagram showing the operation of the boost control circuit 16 configured as described above. The vertical axis represents the level of each signal, and the horizontal axis represents time. As shown in the figure, when an H level enable signal EN is input, each of the flip-flops 161-1,..., 161-m is released from the reset state, and a periodically changing pulse signal Tos is input. In response to the rise of the pulse signal Tos, the control signals EN1,..., ENm sequentially change from the L level to the H level. Here, the reset state means that the flip-flops 161-1,..., 161-m are L level signals from the data output terminal Q regardless of the levels of the signals input to the data input terminal D and the clock terminal CK. Is output.

  2, when the control signals EN1,..., ENm sequentially change to the H level in response to the rise of the pulse signal Tos as described above, the pulse signal Tos output from the oscillator 14 becomes the AND gates 152-1,. Is input to the pump circuits 151-1,..., 151-m of the booster 15 via −m. As a result, each of the pump circuits 151-1,..., 151-m starts to operate sequentially with a delay of one cycle of the pulse signal Tos.

  FIG. 4 is a waveform diagram showing the operation of the booster 15 in the present embodiment. The vertical axis direction indicates the level or current value of each signal, and the horizontal axis direction indicates time. When the boost control circuit 16 outputs the control signals EN1,..., ENm that change to the H level in response to the rise of the pulse signal Tos as described above to the booster 15, the pump circuits 151-1,. -M starts operating in sequence, and the output potential nVdd of each of the pump circuits 151-1,. Further, when the pump circuits 151-1,..., 151-m start operating in sequence, the currents Idd — 1,..., Idd_m flowing through the pump circuits also rise, and the current Idd flowing through the internal power supply circuit 1 Rises corresponding to the pump circuits 151-1,.

  In the semiconductor device 100, the internal power supply circuit 1 includes the boost control circuit 16 and the boost unit 15 controlled by the boost control circuit 16, so that the boost control circuit corresponds to the rise of the pulse signal Tos output from the oscillator 14. 16 outputs to the booster 15 control signals EN1,..., ENm for sequentially boosting the plurality of pump circuits 151-1,. As a result, the pump circuits 151-1,..., 151-m are controlled to start operation by the control signals EN 1,. It is possible to disperse, suppress a steep increase in current generated in the internal power supply circuit 1, and reduce a change in voltage applied to the processing circuit 2.

  That is, the internal power supply circuit 1 suppresses steep fluctuations in the current flowing through the internal power supply circuit 1 by starting the boosting operation of the plurality of pump circuits 151-1,..., 151-m according to the period of the pulse signal. As a result, noise generated in the voltage applied to the processing circuit 2 can be reduced. In addition, since the capacitor 17 is provided at the output of the booster 15, the output potential nVdd can be smoothed due to fluctuations in the connected load even if the boosting operation is performed with a small number of pump circuits.

(Second Embodiment)
The second embodiment is different in that it includes a boost control circuit 16A having a different configuration from the boost control circuit 16 of the first embodiment. Hereinafter, the configuration of the boost control circuit 16A will be described, and the description of the other configurations will be omitted.

  FIG. 5 is a circuit diagram showing the configuration of the boost control circuit 16A of the second embodiment and a waveform diagram showing its operation. As shown in FIG. 5A, the boost control circuit 16A includes flip-flops 161-1,. Each of the flip-flops 161-1,..., 161-m has a data input terminal D and a data output terminal Q connected in series so as to constitute a shift register, and the data input terminal of the first stage flip-flop 161-1 has The power supply potential Vdd is connected as an H level signal.

  In addition, each of the flip-flops 161-1,..., 161-m outputs a signal output from the data output terminal to the booster 15 as control signals EN 1,. That is, each of the flip-flops 161-1,..., 161 -m is associated with the pump circuit 151-1,. The pump circuit 151-1,..., 151-m is configured to select whether or not to input the pulse signal Tos.

  Also, the inverted enable signal EN is input to the reset terminals R of all the flip-flops 161-1,... The pulse signal Tos is input, and the inverted pulse signal Tos is input to the clock terminal CK in the even-numbered flip-flops counted from the first stage of the shift register.

FIG. 5B is a waveform diagram showing the operation of the boost control circuit 16A configured as described above. The vertical axis represents the level of each signal, and the horizontal axis represents time. As shown in the figure, when an H level enable signal EN is input, when a periodically changing pulse signal Tos is input, the control signal EN1, in accordance with the rise and fall (change) of the pulse signal Tos, ..., ENm sequentially changes from the L level to the H level. That is, the boost control circuit 16A sequentially changes the control signals EN1,..., ENm to the H level every half cycle of the pulse signal Tos.
The booster 15 receives the control signals EN1,..., ENm that sequentially change to the H level every half cycle of the pulse signal Tos from the boost control circuit 16A, whereby the pump circuits 151-1,. The operation is sequentially started every half cycle of the pulse signal Tos.

  In the second embodiment, the step-up operation of the pulse circuits 151-1,..., 151-m can be started every half cycle instead of one cycle of the pulse signal Tos, and the pump circuit 151 is compared with the first embodiment. -1,..., 151-m operation start timing can be adjusted by a half cycle which is a time interval shorter than one cycle.

(Third embodiment)
FIG. 6 is a schematic block diagram showing the configuration of the internal power supply circuit 1B of the third embodiment, and a circuit diagram showing the configuration of the boost control circuit 16B. As shown in FIG. 6A, the internal power supply circuit 1B includes a detection circuit 11, a reference potential output circuit 12, a comparator 13, an oscillator 14, a booster 15, a boost control circuit 16B, a capacitor 17, OR gate 18. The internal power supply circuit 1B according to the present embodiment is the same as the first embodiment except that the internal power supply circuit 1B includes a boost control circuit 16B and an OR gate 18 instead of the boost control circuit 16 as compared with the internal power supply circuit 1 of the first embodiment. Since it has a configuration, the corresponding portions are denoted by the same reference numerals, and the description thereof is omitted.

  The boost control circuit 16B receives a control signal Compout output from the comparator 13, an enable signal EN output from the OR gate 18, and a pulse signal Tos output from the oscillator 14. In addition, the boost control circuit 16B supplies each of the m pump circuits 151-1,..., 151-m included in the boost unit 15 according to the input control signal Compout, the enable signal EN, and the pulse signal Tos. On the other hand, control signals EN1,..., ENm for selecting whether or not to input the pulse signal Tos output from the oscillator 14 used for the boosting operation are output.

The OR gate 18 receives the control signal Compout output from the comparator 13 and the control signals EN1,..., ENm output from the boost control circuit 16B, and receives the input control signal Compout and the control signals EN1,. The result of the logical sum operation is output to the oscillator 14 and the boost control circuit 16B.
The oscillator 14 receives the enable signal EN output from the OR gate 18 instead of the control signal Compout output from the comparator 13 input in the first embodiment, and oscillates when an H level enable signal EN is input. The pulse signal Tos is output.

  FIG. 6B is a circuit diagram showing a configuration of the boost control circuit 16B. As shown in FIG. 6B, the boost control circuit 16B has flip-flops 161-1,. In the flip-flops 161-1,..., 161-m, the pulse signal Tos is input to the clock terminal CK, and the inverted enable signal EN is input to the reset terminal R. In addition, in each of the flip-flops 161-1,..., 161-m, a data input terminal D and a data output terminal Q are connected in series so as to constitute a shift register, and the data input terminal of the first stage flip-flop 161-1 Is supplied with the control signal Compout output from the comparator 13.

  In addition, each of the flip-flops 161-1,..., 161-m outputs a signal output from the data output terminal to the booster 15 as control signals EN 1,. That is, each of the flip-flops 161-1,..., 161 -m is associated with the pump circuit 151-1,. The pump circuit 151-1,..., 151-m is configured to select whether or not to input the pulse signal Tos.

FIG. 7 is a waveform diagram showing the operation of the internal power supply circuit 1B in the present embodiment. The vertical direction indicates the level of each signal, and the horizontal axis direction indicates time.
At time t1, when an H level boost start signal is input from the outside, the comparator 13 compares the detection potential Va corresponding to the output potential nVdd with the reference potential Vref and outputs an H level control signal Compout. When the H level control signal Compout is input, the OR gate 18 outputs an H level enable signal EN to the boost control circuit 16B and the oscillator 14. When the H level enable signal EN is input, the oscillator 14 starts oscillating and outputs the pulse signal Tos to the booster 15 and the boost control circuit 16B.
The boost control unit 16B sequentially changes the control signals EN1,..., ENm to the H level and outputs them to the boost unit 15 every time the pulse signal Tos rises. As a result, the boosting operation is started in the order of the pump circuit 151-1 to the pump circuit 151-m.

At time t2, when an L level boost start signal is input from the outside, the comparator 13 outputs an L level control signal Compout. When the L level control signal Compout is input to the boost control circuit 16B, the level changes to the L level in the order of the control signal EN1 to the control signal ENm every time the pulse signal Tos rises. When the control signals EN1,..., ENm are sequentially changed to the L level, the boosting operation is stopped in the order of the pump circuit 151-1 to the pump circuit 151-m.
When the control signal ENm finally changes to the L level, the OR gate 18 outputs the L level control signal EN to the boost control circuit 16B and the oscillator 14. In the boost control circuit 16B, all the flip-flops 161-1, .., 161-m are reset by the enable signal EN, and the oscillator 14 stops oscillation and output of the pulse signal Tos.

  With the above-described configuration and operation, the internal power supply circuit 1B has the pump circuits 151-1,..., 151-m in response to the rising edge of the pulse signal Tos at the start of boosting, like the internal power supply circuit 1 of the first embodiment. The boosting operation is started in order. Further, when an L level boost start signal is input from the outside, the internal power supply circuit 1B stops the boost operation in the order of the pump circuits 151-1,. As a result, the internal power supply circuit 1 can disperse the change in the current Idd that occurs when the boosting operation is stopped, according to the cycle of the pulse signal Tos, similarly to when the boosting operation starts, and the steep current generated in the internal power supply circuit 1B Therefore, the change (voltage noise) applied to the processing circuit 2 can be reduced.

  In the present embodiment, the configuration corresponding to the first embodiment, that is, the configuration in which the pump circuits 151-1,..., 151-m are stopped according to the one-cycle interval of the pulse signal Tos has been described. It is good also as a structure which stops pump circuit 151-1, ..., 151-m in order according to the half cycle interval of pulse signal Tos using the same structure with respect to 2 embodiment.

  The boost control circuit 16 of the first embodiment and the boost control circuit 16B of the third embodiment change the control signals EN1,..., ENm at one cycle interval of the pulse signal Tos, and the boost control of the second embodiment. The circuit 16A is configured to change the control signals EN1,..., ENm at a half cycle interval of the pulse signal Tos. However, the control signals EN1,. It is good also as composition changed to.

  In the boost control circuit 16 of the first embodiment, the boost control circuit 16A of the second embodiment, and the boost control circuit 16B of the third embodiment, the flip-flops 161-1, ..., 161-m constitute a shift register. The pump circuit 151-1,..., 151-m is configured to start the boost operation one by one, but the combination circuit is used to operate two or more pump circuits at a time. Also good. Further, the boosting operation of the pump circuit may be started every plural cycles without starting the boosting operation of the pump circuit every cycle of the pulse signal Tos. Thereby, even when the oscillation period of the oscillator 14 is short, the timing for starting the boosting operation of the pump circuit can be dispersed in time.

(simulation result)
FIG. 8 is a graph showing a simulation result by the configuration of the internal power supply circuit 1 of the first embodiment. However, the booster 15 has six pump circuits 151-1,..., 151-6, and when a boost start signal is input, three, four, five, The boosting operation of the pump circuit is started in the order of six.
FIG. 8A is a waveform diagram of the pulse signal Tos input to each of the pump circuits 151-1,..., 151-6. The vertical axis direction indicates the level of each pulse signal Tos, and the horizontal axis direction indicates time. FIG. 8B is a waveform diagram of the current Idd flowing through the internal power supply circuit 1. The vertical axis represents the current value, and the horizontal axis represents time. As shown, the current value of the current Idd increases as the number of operating pump circuits increases. FIG. 8C is a waveform diagram in which an auxiliary line indicating a change in the current value of the current Idd is added to FIG. 8B.

FIG. 9 shows a simulation result of the current Idd flowing through the internal power supply circuit 1 of the first embodiment and a simulation of the current Idd when all the pump circuits included in the booster unit 15 of the internal power supply circuit 1 are started simultaneously. It is a wave form diagram which compares a result. The vertical axis represents the current value, and the horizontal axis represents time. A waveform Ga represents the current Idd of the first embodiment, and a waveform Gb represents Idd when the pump circuits are operated all at once. As shown in the figure, the current Idd indicated by the waveform Gb rises steeply with the start of the operation, whereas the waveform Ga showing the current Idd of the present embodiment rises more slowly than the waveform Gb. Yes.
As described above, the semiconductor devices according to the first and second embodiments can suppress a steep change in the current Idd flowing through the internal power supply circuit 1.

FIG. 10 is a waveform diagram showing the current Idd flowing through the internal power supply circuit 1 and the voltage applied to the processing circuit 2 in the first embodiment. However, here, the booster 15 operates the ten pump circuits one by one in order. At this time, as shown in the figure, the current Idd of the internal power supply circuit 1 according to the first embodiment corresponds to the pulse signal Tos output from the oscillator 14 as compared to the current of the conventional internal power supply circuit 91 rising steeply. It has been shown to rise.
Further, it is shown that, by suppressing the steep rise in the current Idd as described above, the fluctuation caused by the internal power supply circuit 1 that occurs in the voltage applied to the processing circuit 2 can be suppressed to about one tenth.

  The present invention can be applied to a semiconductor device using a Dickson charge pump circuit.

DESCRIPTION OF SYMBOLS 1 ... Internal power supply circuit, 2 ... Processing circuit, 8 ... External DC power supply, 9 ... Semiconductor device 11 ... Detection circuit, 12 ... Reference potential output circuit, 13 ... Comparator, 14 ... Oscillator 15 ... Boosting part 16, 16A, 16B DESCRIPTION OF SYMBOLS ... Boost control circuit, 17 ... Capacitor 100 ... Semiconductor device 151-1, 151-m ... Pump circuit, 152-1, 152-m ... AND gate 161-1, 161-m ... Flip-flop 90 ... Processing circuit, 91, 91a, 91b ... Internal power supply circuit 93-1, 93-n ... Diode, 94-1, 94-n ... Capacitor 95 ... Inverter, 97 ... NAND gate 911 ... Detection circuit, 912 ... Reference potential output circuit, 913 ... Comparator 914 , 914a ... Oscillator, 915, 915a ... Booster 915-1, 915-2, 915-m ... Pump circuit

Claims (4)

An oscillator that outputs a pulse signal whose level changes in a predetermined cycle;
In response to the pulse signal output from the oscillator, a plurality of booster circuits that boost the externally input power supply voltage;
A power supply circuit comprising: a control circuit that selects whether or not to input the pulse signal to each of the plurality of booster circuits in accordance with a change in the pulse signal output from the oscillator. The control circuit includes:
A bit corresponding to each of the plurality of booster circuits, and a shift register that changes in response to rising of the pulse signal;
2. The power supply circuit according to claim 1, wherein whether or not to input the pulse signal to each of the plurality of booster circuits is selected according to the level of each of the plurality of bits. The control circuit includes:
A bit corresponding to each of the plurality of booster circuits, and a shift register that changes in response to a rising edge or a falling edge of the pulse signal;
2. The power supply circuit according to claim 1, wherein whether or not to input the pulse signal to each of the plurality of booster circuits is selected according to the level of each of the plurality of bits. The power supply circuit according to any one of claims 1 to 3, further comprising a capacitor having one end commonly connected to outputs of the plurality of booster circuits and the other end grounded.

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