JPH0737393A - Multilevel memory - Google Patents

Abstract

PURPOSE:To omit an encoder and to reduce the number of sense amplifiers by reading one bit of a superordinate bit at the time of reading at an initial stage, reading one subordinate bit at the time of reading at next stage, and controlling reading and holding of data with a controller. CONSTITUTION:A sequencer 7 is operated at a rise of a read signal, and a reference potential VC2 is output at a rising node C of a signal phi1. A read potential is compared with a potential VC2 by a sense amplifier 3. Since the read potential is low, 'H' is output to a node E, and held in an FF 61. Then, 'H' is output at a rising node H of a signal phi4, a transistor D51 is connected to a bias circuit 4, and a reference potential VC1 is output to the node C. The read potential is compared with the potential VC1 by the amplifier 3. Since the read potential is high, 'L' is output to the node E, and held in an FF 62. As a result, 'H' is output to an OUT 1 in response to stored data of a memory cell transistor, and 'L' is output to an OUT 2. Thus, a circuit can be simplified.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to multi-valued memories. In particular, it relates to a read circuit for storing four or more values of data in one memory cell in a mask ROM, EPROM, EEPROM or the like.

[0002]

2. Description of the Related Art Conventionally, multi-valued memories have been studied in order to dramatically increase the storage capacity of semiconductor memory devices. While an ordinary semiconductor memory stores binary data of “0” and “1” in one memory cell, that is, 1-bit data,
In a multi-valued memory, for example, "00", "0" are assigned to one memory cell.
It stores four values of 1 ”,“ 10 ”, and“ 11 ”, that is, 2 bits of data. In the case of a mask ROM, the channel length and the channel width of the memory cell transistors are made different, or by channel ion implantation. Multivalue storage is performed by changing the conductance of the memory cell transistor by adjusting the threshold value.In the case of EPROM or EEPROM, the conductance of the memory cell transistor is changed by changing the amount of electrons injected into the floating gate. By changing the conductance of the memory cell transistor in four ways, 2-bit data can be stored in one memory cell, and as a result, a storage capacity double that of a normal semiconductor memory can be realized.

As an example of such a multi-valued memory, the one applied to a mask ROM is disclosed in JP-A-57-58298 and W.
O80 / 01119 (PCT / US79 / 00989)
Are described in detail in. Further, the one applied to the EEPROM is described in detail in JP-A No. 2-40198.

[0004]

As described above, since the multilevel memory stores multilevel data in one memory cell, the storage capacity of the semiconductor memory can be dramatically improved. However, since the memory cell outputs the read data in an analog manner, for example, as voltage or current, there is a problem that the read circuit of the multilevel memory becomes more complicated than the read circuit of the normal memory.

For example, JP-A-57-58298 and WO
80/01119 (PCT / US79 / 00989) describes an example in which 4-level data is stored in one memory cell. For this purpose, three types of Vref (reference potential) generation circuits and three The differential sense amplifier of is used. Further, an encoder circuit for converting the outputs of these differential type sense amplifiers into 2-bit data is required. This led to an increase in chip area.

An object of the present invention is to eliminate such drawbacks, reduce the number of differential type sense amplifiers, and provide a multi-valued memory in which an encoder circuit is omitted.

[0007]

In order to achieve the above object, according to the present invention, a multi-valued memory cell array having a plurality of memory cell transistors for storing four or more values of data due to a difference in conductance, and a conductance of the memory cell transistors. A bit line Baice circuit for generating a read potential according to the reference potential generation circuit for generating a plurality of reference potentials, a sense amplifier for comparing the read potential and the reference potential and outputting data according to the comparison result, In the first stage of a read operation including a plurality of stages including the first and second flip-flop circuits, the reference potential generating circuit outputs a potential of a predetermined level, and the output data of the sense amplifier is held in the first flip-flop circuit. In the next stage, when the read potential is lower than the reference potential in the first stage, the level of the reference potential And a read control circuit that lowers the level of the reference potential when the read potential is higher than the reference potential of the first stage and holds the output data of the sense amplifier in the second flip-flop circuit. To provide multi-valued memory.

Further, a multi-valued memory cell array having a plurality of memory cell transistors for storing four or more values of data due to a difference in conductance, a bit line Baice circuit for generating a read potential according to the conductance of the memory cell transistors, and a first A first reference potential generating circuit for generating a reference potential of, and a second reference potential generating circuit for generating a second reference potential higher than the first reference potential,
A third reference potential generation circuit that generates a third reference potential higher than the second reference potential, and a sense that compares the read potential with the first to third reference potentials and outputs data according to the comparison result. An amplifier and first and second flip-flop circuits are included. In the first stage of a read operation including a plurality of stages, the second reference potential is input to the sense amplifier, and the output data of this sense amplifier is input to the first flip-flop circuit. In the next stage, when the read potential is lower than the second reference potential, the first reference potential is input to the sense amplifier, and when the read potential is higher than the second reference potential, the third reference potential is held. To a sense amplifier, and a read control circuit for holding output data of the sense amplifier in a second flip-flop circuit is provided.

[0009]

When the means provided by the present invention is used, the reading of the upper 1 bit of the first read (“1X” or “0”) is performed.
X ") can be performed, and the lower-order 1 bit can be read (" X1 "or" X0 ") in the read operation of the next stage. At this time, the read operation of the next stage is affected by the read operation of the first stage. By omitting the encoder, the number of sense amplifiers can be reduced.

[0010]

[First Embodiment] [First Embodiment] [Fig. 1] to [Fig. 4]
Will be explained. The multi-valued memory of the present invention has a structure as shown in FIG. That is, it includes a memory cell array 1, a bias circuit 2, a sense amplifier circuit 3, a reference potential generation circuit 5, a read control circuit 6, and a sequencer 7.

As will be described later, the memory cell array 1 has memory cell transistors M11, M12 and M13 for storing four-valued data arranged in a matrix according to the difference in conductance. The control gates of the memory cell transistors arranged in the same row are connected to the same word line WL. The word line WL is connected to a row decoder and a word line drive circuit (not shown), and is "H" (5V) when selected.
When it is not selected, it becomes "L" (0V). The drains of the memory cell transistors arranged in the same column are bit lines BL
Connected to column gate transistors Q11 and Q.
Commonly connected to the bias circuit 2 via 12 and Q13.

The bias circuit 2 includes transistors Q21, Q22 and inverters 21, 22 as shown in FIG. 2 (a).
And a P-channel transistor Q23.
These bias circuits use a potential corresponding to the conductance of the memory cell transistor M11 or the like as a read potential and output it to the node B.

The sense amplifier circuit 3 compares the potential of the node B (read potential) with the potential of the node C (reference potential), and if the read potential is lower than the reference potential, "H".
Is output to the node E, and if the read potential is higher than the reference potential, "L" is output to the node E. A specific circuit configuration is shown in FIG. 2 (b). That is, a differential sense amplifier including an operating circuit including P-channel transistors Q32 and Q33, a P-channel transistor Q31 functioning as a constant current source, and a current mirror type load including N-channel transistors Q34 and Q35, and further a differential sense amplifier including the differential sense amplifier. It comprises inverters 31 and 32 for amplification.

The reference potential generating circuit 5 is a dummy cell transistor D51, D52, D53 having different conductances.
And a bias circuit 4 connected to a node D having these drains commonly connected, and column gate transistors Q51, Q52, Q53 connected between the dummy cell transistor and the bias generation circuit 4. Transistor Q52
Control gate is controlled by signal φ1, transistor Q51 is controlled by signal H, and transistor Q53 is controlled by signal I. Therefore, reference potentials of different levels can be output to the node C depending on the potentials of the node I and the node H.
The bias circuit 4 has substantially the same configuration as the bias circuit 3 as shown in FIG.
The conductance of 23 is set large.

The read control circuit 6 includes flip-flop circuits 61 and 62, a node E and a flip-flop circuit 6.
A transistor Q65 for connecting 1 and a transistor Q66 for connecting the node E and the flip-flop circuit 62;
A transistor Q61 that connects the node H and one end of the flip-flop circuit 61, a transistor Q62 that discharges the node H, a transistor Q63 that connects the node I and the other end of the flip-flop circuit 61, and a transistor that discharges the node I. It consists of Q64. The signal φ3 is input to the control gate of the transistor Q65, and the signal φ2 is input to the control gate of the transistor Q66. Also, the transistor Q
Signal φ4 is applied to the control gates of 61 and Q63 by the transistor Q.
The signal / φ4 is input to the control gates of 62 and Q64.

The sequencer 7 has a structure as shown in FIG. 2 (c), and has various signals (φ) necessary for the circuit operation.
1 to φ4) is generated. The operation of this sequencer will be described later.

Next, the memory cell of the multilevel memory will be described with reference to FIG. FIG. 3A shows a sectional view of the memory cell transistor. That is, the N-type source region 12 and the drain region 11 provided at intervals on the surface of the P-type semiconductor substrate 10 and the gate electrode 14 formed on the channel region between both regions via the gate insulating film. Consists of. A predetermined amount of P-type impurity is ion-implanted into the channel region, and the conductance is adjusted in four ways by the amount of implantation. The source of this memory cell transistor is grounded, and the relationship between the gate voltage Vg and Id is shown in a graph with the ion implantation amount as a parameter [FIG. 3] (b). “11”, “10”, “01”, in ascending order of ion implantation amount,
The data of "00" is stored, and each threshold value is Vth.
1, Vth2, Vth3, Vth4. Thus, when a voltage of 5 V is applied to the gate electrode, different currents flow according to the stored data. These memory cell transistors are connected to the bias circuit 2 via the column gate transistor Q11 and the like. [FIG. 3] (c) shows the distribution of the read potential VB of a large number of memory cell transistors. The read potentials are "1" in ascending order.
1 ”,“ 10 ”,“ 01 ”,“ 00 ”.
Vg is 5V. The threshold values of the dummy cell transistors described above are Vth1 for D51, Vth2 for D52, and Vth3 for D53.
Is. That is, it corresponds to “11”, “10”, and “01”. However, since the conductance of the load transistor on the dummy cell side is larger than that on the memory cell side, the potential VC at the node C is Vc1 when the dummy cell transistor D51 is connected, and Vc2 and D53 when D52 is connected.
Is connected to Vc3. As shown, Vc1 is identified as "11" or "10", and Vc2 is identified as "10" or "0".
Vc3 is used to identify "1" and "01" and "00".

Next, the read operation will be described.
[FIG. 4] shows a time chart at the time of reading. It is assumed that "10" is stored in the memory cell to be read. When the Read signal rises, the sequencer 7 starts operating and the signal φ1 rises after a predetermined delay time. At the same time, the transistor Q52 becomes conductive, the dummy cell transistor D52 and the bias circuit 4 are connected, and the node C
Vc2 is output to. Here, the sense amplifier circuit 3 compares the read potential with the reference potential (Vc2). As a result, since the read potential is lower, "H" is output to the node E. Then, after a predetermined delay time, φ
A short pulse of 3 is input to the control gate of transistor Q65. As a result, the data “H” at the node E is held in the flip-flop circuit 61. Then φ1 also falls. After a delay of a predetermined time, φ4 rises and the transistors Q61 and Q62 become conductive, so that the node H and the node I
A signal corresponding to the flip-flop circuit 61 is output to. Here, “H” is output to the node H. At the same time, the transistor Q51 becomes conductive and the dummy cell transistor D51
Is connected to the bias circuit 4, and Vc1 is output to the node C. Here, the read potential and the reference potential (Vc1) are compared by the sense amplifier circuit 3. As a result, the read potential is higher, so that "L" is output to the node E. Then, after a predetermined delay time, a short pulse of φ2 is input to the control gate of the transistor Q66. As a result, the data “L” at the node E is changed to the flip-flop circuit 6
Held at 2. Then φ4 also falls. As a result,
Corresponding to the stored data "10" of the memory cell transistor, "H" is output to out1 and "L" is output to out2.

This is because the upper bit is read in the first (first stage) read operation, which is "H" or "1", and the lower bit is read in the second (next stage) read operation. This is an example of "L" or "0". In the second read operation, it was judged whether it was "11" or "10".

Contrary to the above example, when the read potential is higher than the reference potential in the first read operation, the node F of the flip-flop circuit 61 holds "L". As a result, the node I becomes "H" level and the transistor Q53 becomes conductive, so that Vc3 is output to the node C. Therefore, in the second read operation, "01"
Or "00" is determined.

To summarize the above, in the read operation of the first stage (while φ1 is "H"), the upper 1 bit is read ("1").
X "or" 0X "is performed, and the lower one bit is read (" X1 "or" X "in the read operation of the next stage.
0 "). At this time, the read operation of the next stage is affected by the read operation of the first stage. As a result, the encoder can be omitted and the number of sense amplifiers can be reduced from three to one. Reduces the chip area.

Next, a modification of the first embodiment [FIG. 5].
Will be described with reference to. FIG. 5A shows a modification of the read control circuit 6. Elements corresponding to those in FIG. 1 are designated by the same reference numerals. That is, the flip-flop circuits 61 and 62, the transistor Q65 connecting the node E and the flip-flop circuit 61, the transistor Q66 connecting the node E and the flip-flop circuit 62, and the node H and the terminal of φ4 are connected. Transistor Q61, transistor Q62 discharging node H, node I and φ4
It is composed of a transistor Q63 connected to the terminal and a transistor Q64 discharging the node I. The signal φ3 is input to the control gate of the transistor Q65, and the signal φ2 is input to the control gate of the transistor Q66. Further, the flip-flop circuit 6 is connected to the control gates of the transistors Q61 and Q64.
One end of the flip-flop circuit 61 is connected to the control gates of the transistors Q62 and Q63.

A modified example of the reference potential generating circuit 5 is shown in FIG. 5 (b). That is, the dummy cells D51, D52, D53
Is a transistor Q whose control gate is connected to the power supply potential
It is connected to the bias circuit 4 via 51, Q52 and Q53. A signal H, a signal φ1, and a signal I are input to the control gates of the dummy cells D51, D52, D53, respectively. This is an example in which the selection of the dummy cell is controlled by the gate voltage of the cell.

The operation of each modified example of FIG. 5 is almost the same as that of the first embodiment, and the operation is performed by using the sequencer 7 which is completely common, and therefore the description thereof is omitted. continue,
A second embodiment of the present invention will be described with reference to FIGS. 6 and 7. This is an example in which the reference potential generation circuit 8 is commonly used for a plurality of memory cell arrays MA.

FIG. 6 shows a circuit configuration diagram of the second embodiment. That is, four memory cell arrays MA1 and MA2
, MA3, MA4, read circuits RC1, RC2, RC3, RC4 provided correspondingly, and a reference potential generating circuit 8. The reference potential generation circuit 8 supplies three types of reference potentials (Vc1, Vc2, Vc3) to the common reference potential line R.
It outputs to 1, R2, and R3, respectively, and these reference potentials are input to each reading circuit.

FIG. 7 shows one memory cell array MA1, read circuit RC1, reference potential generating circuit 8 of FIG.
This is an example in which is extracted and shown in detail. The memory cell array MA1 has memory cell transistors M11, M12, and M13 that store four-valued data depending on the difference in conductance arranged in a matrix. The control gates of the memory cell transistors arranged in the same row have the same word line WL.
It is connected to the. The word line WL is connected to a row decoder and a word line drive circuit (not shown), and becomes "H" (5V) when selected and "L" (0V) when not selected.
The drains of the memory cell transistors arranged in the same column are connected to the bit line BL, which is commonly connected to the bias circuit 94 via the column gate transistors Q11, Q12, Q13.

The read circuit RC1 is a bias circuit 94.
, Sense amplifier circuit 95, and flip-flop circuit 6
1, 62 and a reference potential selection circuit 91. The bias circuit 94 and the sense amplifier circuit 95 are almost the same as those in the first embodiment. The read circuit RC1 further includes flip-flop circuits 61 and 62, a transistor Q65 connecting the node E and the flip-flop circuit 61, a transistor Q66 connecting the node E and the flip-flop circuit 62, a node H and the flip-flop circuit. A transistor Q61 connecting one end of 61, a transistor Q62 discharging the node H, a transistor Q63 connecting the node I and the other end of the flip-flop circuit 61, and a node I
And a transistor Q64 that discharges. The signal φ3 is input to the control gate of the transistor Q65, and the signal φ2 is input to the control gate of the transistor Q66. The signal .phi.4 is input to the control gates of the transistors Q61 and Q63, and the signal .phi.4 is input to the control gates of the transistors Q62 and Q64.

The reference potential selecting circuit 91 includes a transistor Q91 connecting the node A and the common reference potential line R1 and a transistor Q connecting the node A and the common reference potential line R2.
And a transistor Q93 connecting the node A and the common reference potential line R3. Transistors Q91, Q92, Q
The signal H, the signal φ1, and the signal I are input to the gate of 93, respectively.

The reference potential generating circuit 8 comprises three types of dummy cell transistors D81, D82, D83 and bias circuits 81, 82, 83 connected to them. These bias circuits 81, 82 and 83 are the same as those in the first embodiment, but the magnitude of the load is different from that of the bias circuit 94.
The threshold value of the dummy cell transistor is Vth1 for D51, D for
52 is Vth2 and D53 is Vth3. That is, "1
However, since the conductance of the load transistor is larger than that on the memory cell side, the potential of the common reference potential line R1 is Vc1 and the potential of R2 is Vc2, the potential of R3. Becomes Vc3.As mentioned above,
Vc1 is identified as "11" or "10", and Vc2 is "1"
Vc3 is used for identifying 0 "and" 01 "and for identifying" 01 "and" 00 ".

The read operation of the second embodiment is almost the same as that of the first embodiment, and the sequencer 7 can be the same as that of the first embodiment. The operation waveform is the same as in FIG. However, in the second embodiment, since the bias circuits on the dummy cell side are provided by the number of dummy cells, the common reference potential lines R1, R2, R3 can be provided, and when the memory architecture has a multi-bit configuration. The reference potential generation circuit can be shared, which contributes to the reduction of the chip area.

Next, a third embodiment will be described with reference to FIGS. 8 to 10. This is an example in which a CCD, which is an analog shift register, is used for data transfer. FIG. 8 shows a circuit configuration diagram of the third embodiment. That is, the memory cell transistors MC are arranged in a matrix to form a memory cell array, the control gates of the memory cell transistors MC on the same row are connected to the word line WL, and the memory cell transistors MC on the same column are connected. The drain is connected to the bit line BL. Each bit line BL resistance element 20 is connected. Two-phase clocks (φ7, φ8) in the row direction of the memory cell array
A control CCD analog shift register 300 is provided and transfers charges from left to right in the figure. Bit line BL
Transistors T1 and T2 are inserted in series between the CCD analog shift register and the CCD analog shift register, and a capacitive element C1 is connected between them. The transistor T2 stores the charge stored in the capacitive element C1 in the CCD analog shift register 3
Transfer to 00 completely. CCD analog shift register 3
The transfer layer at the right end of 00 is grounded, the transfer layer immediately before is connected to the read node J, and the capacitive element C is connected to the node J.
2 is connected. The read circuit RC is driven by clocks φ7 and φ8, and outputs 2-bit outputs out1 and out2 in accordance with the potential of the node J.

FIG. 9 shows details of the read circuit RC. That is, the sense amplifier circuit 3, the flip-flop circuits 71, 72, 73, and the reference potential generation circuit 91 are included. Since the sense amplifier circuit 3 and the reference potential generation circuit 91 are almost the same as those in the first embodiment, the same reference numerals are given and the description thereof will be omitted. The read circuit RC further includes a transistor Q that connects the flip-flop circuit 71 and the node E.
65, a transistor Q66 connecting the flip-flop circuit 72 and the node E, a transistor Q61 connecting the node H and one end of the flip-flop circuit 61, a transistor Q62 discharging the node H, a node I and the flip-flop circuit. Transistor Q63 connecting to the other end of 61
And a transistor Q64 discharging the node I.
Further, a transistor Q69 that connects the other end of the flip-flop circuit 71 and one end of the flip-flop circuit 73,
The inverter circuit 74 connected to the other end of the flip-flop circuit 73 is connected. The signal φ8 is input to the control gate of the transistor Q65, and the signal φ7 is input to the control gates of the transistors Q66 and Q69. A signal φ7 is input to the control gates of the transistors Q61 and Q63, and a signal / φ7 is input to the control gates of the transistors Q62 and Q64.

Next, the bit line, the CCD analog shift register and the connecting portion will be described with reference to FIG. 10 (a). That is, the N-type diffusion layers 301 and 302 formed on the P-type semiconductor substrate 300 at a predetermined interval, the control gate 303 formed on the channel region between both diffusion layers with an insulating film interposed therebetween, and the P-type semiconductor substrate. A control gate 304 formed on the channel region between the CCD analog shift register unit 306 and the N-type diffusion layer 302 on the surface of 300 via an insulating film, and a transfer gate 305 formed on the CCD analog shift register unit 306. Consists of. The control gate 303 corresponds to the transistor T1, and the control gate 304
Corresponds to the transistor T2. The N type diffusion layer 301 is connected to the bit line, and the N type diffusion layer 302 constitutes the capacitive element C1.

At the time of reading, a voltage drop occurs in the resistance element 20 according to the conductance of the memory cell, and the bit line B
A potential corresponding to the data stored in the memory cell is output to L. The capacitive element C1 performs VQ conversion (voltage / charge conversion). When the signal .phi.5 becomes "H" and the transistor T1 becomes conductive, the N-type diffusion layer 302 becomes the same potential as the bit line, and the electric charge corresponding to this potential is charged. When the signal .phi.5 becomes "L" and the bit line and the capacitive element C1 are cut off, and then the signal .phi.6 becomes "H", the charge accumulated in the capacitive element C1 is transferred to the CCD analog shift register section. . Here, if φ7 is set to "H", the charge is transferred according to the capacity division of the capacity of C1 and the capacity of the transfer section. The structure of the transistor T2 may be changed so that complete transfer can be realized.

[FIG. 10] (b) shows a signal waveform during operation. As described above, by inputting the pulse of the signal φ5 and the pulse of the signal φ6, the charge corresponding to the potential of the bit line is transferred to the CCD analog shift register. Subsequently, φ 7 and φ 8 are input one after another, whereby the shift register transfers charges. When the first pulse .phi.8 is input, a voltage corresponding to the electric charge of the rightmost bit line in FIG. 8 appears at the node J. This is the read circuit RC
To detect. The upper bit is detected according to this pulse φ 8 and is held in the flip-flop circuit 71. Then, when the pulse φ7 is input, the data in the shift register is transferred to the right one stage, and the lower bit is detected in the read circuit RC. That is, the reference potential based on the data held in the flip-flop circuit 71 is input to the sense amplifier circuit 3, and the result of comparing the potential (reading potential) of the node J with the reference potential is held in the flip-flop circuit 72. At the same time, the upper bit data held in the flip-flop circuit 71 is transferred to the flip-flop circuit 73. The operation described above is repeated thereafter.

Although the present invention has been described with reference to the first to third embodiments, the present invention is not limited to these embodiments and various modifications can be made. For example, the conductance of the memory cell transistor was adjusted according to the amount of ion implantation, but this may be done by changing the size of the transistor, the gate oxide film thickness, or the like. It may be performed by changing. It goes without saying that the latter case can be used for an EEPROM or the like. Further, in the embodiment, the description has been given focusing on the read circuit for reading 4-valued data, but this does not need to be 4-valued, but 8-valued, 16-valued or the like may be used. In the case of 8-value, it becomes possible to detect 3-bit data from "111" to "000" by detecting 3 times, and in the case of 16-value, similarly, "1111" can be detected by detecting 4 times. It is possible to detect 4-bit data from "0000" to "0000". In either case, in the first stage, the reference potential generation circuit outputs a predetermined level potential and the output data of the sense amplifier is held in the flip-flop circuit, and in the next stage, when the read potential is lower than the reference potential of the first stage, the reference potential The present invention can be realized by lowering the level of the sense amplifier and holding the output data of the sense amplifier in another flip-flop circuit when the read potential is higher than the reference potential of the first stage.

[0037]

As described above, according to the present invention, the number of differential sense amplifier circuits can be reduced even in a multi-valued memory, and an encoder circuit becomes unnecessary. As a result, the chip area can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 3 shows an example of a memory cell of the multilevel memory of the present invention.

FIG. 4 is a timing chart of a read operation according to the first embodiment of the present invention.

FIG. 5 is a modification of the first embodiment of the present invention.

FIG. 6 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 7 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 8 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 9 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 10 is an explanatory diagram showing a third embodiment of the present invention.

[Explanation of symbols]

 1 memory cell array 2 bias circuit 3 sense amplifier circuit 4 bias circuit 5 reference potential generation circuit 6 read control circuit 7 sequencer M multi-valued memory cell D dummy cell Q transistor

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Yuichiro Takahashi, 580-1, Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Toshiba Semiconductor Systems Engineering Center

Claims (3)

[Claims] 1. A multi-valued memory cell array having a plurality of memory cell transistors that store four or more values of data depending on the conductance, a bias circuit that generates a read potential according to the conductance of the memory cell transistors, and a multi-valued memory cell. A reference potential generating circuit that generates a reference potential, a sense amplifier that compares the read potential and the reference potential and outputs data according to a comparison result, and a first and a second flip-flop circuit. In the first stage of the read operation, the reference potential generating circuit outputs a potential of a predetermined level and the output data of the sense amplifier is held in the first flip-flop circuit. In the next stage, the read potential is the first stage of the reference. When it is lower than the potential, the level of the reference potential is lowered and the read voltage is lowered. Is higher than the reference potential of the first stage, the read control circuit increases the level of the reference potential and holds the output data of the sense amplifier in the second flip-flop circuit. Value memory. 2. A multi-valued memory cell array having a plurality of memory cell transistors for storing four or more levels of data depending on the conductance, a bit line baice circuit for generating a read potential according to the conductance of the memory cell transistors, A first reference potential generating circuit for generating a first reference potential; a second reference potential generating circuit for generating a second reference potential higher than the first reference potential; and a second reference potential higher than the second reference potential. A third reference potential generating circuit that generates a high third reference potential; a sense amplifier that compares the read potential with the first to third reference potentials and outputs data according to a comparison result; And a second flip-flop circuit, and the second reference potential is input to the sense amplifier at the first stage of a read operation including a plurality of stages. The output data of this sense amplifier is held in the first flip-flop circuit, and in the next stage, when the read potential is lower than the second reference potential, the first reference potential is input to the sense amplifier. A read control circuit that inputs the third reference potential to the sense amplifier when the read potential is higher than the second reference potential and holds output data of the sense amplifier in the second flip-flop circuit. A multi-valued memory comprising: 3. The multi-valued memory according to claim 1, wherein the read potential is transferred from the bit line Baice circuit to the sense amplifier by an analog shift register.