JPH0955091A - Flash memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an efficient and economical flash memory device by temporarily storing data to be written in a flash memory until fixed quantity can be obtained and reducing the frequency of writing data in a flash memory. SOLUTION: When a data writing in a flash memory is requested from a main device 11 to a flash memory device 5, the address of a region to be written and new data are temporarily stored in a buffer circuit 3 by the control of a transfer control circuit 4. At a point of time when fixed new data is stored in the buffer circuit 3, the data is transferred to a buffer memory circuit 2. The buffer memory circuit 2 arranges data for a writing form for the flash memory, and transfers data to the flash memory circuit 1. Thereby, the frequency of writing data in the flash memory can be reduced, change interval of a flash memory element is extended, and a whole processing time for writing data can be shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flash memory device composed of a flash memory device and used as an auxiliary storage device.

A main unit for processing data is a central processing unit that processes data at high speed, a main memory that supplies data necessary for processing to the central processing unit, and holds processing results output from the central processing unit. Composed of devices.

Since the main memory is required to operate following the processing speed of the central processing unit, it is generally relatively fast and relatively inexpensive dynamic memory device (hereinafter referred to as "DRAM") capable of reading and writing at any address. Or a random access memory element (hereinafter abbreviated as “RAM”) such as a static memory element (hereinafter abbreviated as “SRAM”) that is expensive but does not require refresh processing.

Since these RAMs are volatile storage elements that lose the data they hold when the power supply is cut off, the data that needs to be stored is stored in a non-volatile storage medium such as a magnetic disk or magnetic tape. Then stored.

However, in order to record on these storage media, a drive device that is weak against vibration and operates mechanically is required. Therefore, in a vibrating environment, a flash memory device using a non-volatile flash memory device is auxiliary. Used as a storage device.

However, in the flash memory device, it is necessary to once erase the entire chip at once before writing data, and the time required for the erase is long (for example, 0.3.
s), the writing time is longer (for example, 6 μs) than the data reading time (for example, 200 ns), and the number of times of writing is limited, so that efficient memory control is required.

[0007]

2. Description of the Related Art FIG. 11 is a block diagram of a conventional example.
Is a flowchart of a conventional example. Figure 1 for a conventional example
1, with reference to FIG. In the following description, the same parts or corresponding parts are denoted by the same reference numerals.

In FIG. 11, 1 is a flash memory circuit, 2 is a buffer memory circuit, 4'is a transfer control circuit, 5'is a flash memory device,
6 is a data line, 7 and 9 are control lines, 8 and 10 are address lines, and 11 is a main unit.

The flash memory circuit 1 is a memory circuit composed of m blocks of flash memory elements each having n words as one block, and is connected to the buffer memory circuit 2 and the main body device 11 via a data line 6. It is connected to the transfer control circuit 4'through the address line 10 and the control line 9, and the data stored under the control of the transfer control circuit 4'is erased in block units, and read and write are performed in individual address units. Memory circuit.

The buffer memory circuit 2 is a memory circuit having the same word configuration as that of the flash memory circuit 1 and having a number of words corresponding to one block of the flash memory circuit 1. Is connected to the flash memory circuit 1 and the main body device 11 and is connected to the transfer control circuit 4'via the control line 9 and the address line 10, and is read and written in the unit of individual address under the control of the transfer control circuit 4 '. It is a memory circuit in which

The transfer control circuit 4'is connected to the main body device 11 via a control line 7 and an address line 8, is connected to the flash memory circuit 1 and the buffer memory circuit 2 via a control line 9, and is connected to the address line 10. Is connected to the flash memory circuit 1 and the buffer memory circuit 2 via the, and receives a request from the main body device 11 to erase the flash memory circuit 1.
A transfer control circuit that controls reading and writing and controls reading and writing of the buffer memory circuit 2.

The flash memory device 5'is connected to the main body device 11 via a data line 6, a control line 7 and an address line 8 and is composed of a flash memory circuit 1, a buffer memory circuit 2 and a transfer control circuit 4 '. It is a storage device.

The main body device 11 is connected to the flash memory device 5'via the data line 6, the control line 7 and the address line 8, reads data from the flash memory device 5 ', performs processing, and outputs the processing result to the flash memory device. Device 5 '
It is a processing device for storing in.

When data writing is requested from the main body device 11 to the flash memory device 5 ', the request is accepted by the transfer control circuit 4'. In step S1, a block designation section (hereinafter abbreviated as "block address") of an address designated by the main body device 11 (hereinafter abbreviated as "flash address") in the flash memory circuit 1
The data of the area for one block designated by is transferred to the buffer memory circuit 2 by the transfer control circuit 4 '.

In step S2, the area of one block designated by the block address of the flash memory circuit 1 is erased by the transfer control circuit 4 '. Step S3
Then, the new data transferred from the main body device 11 is written by the transfer control circuit 4'in the area of the buffer memory circuit 2 designated by the word designating section of the flash address (hereinafter, abbreviated as "word address"). .

In step S4, the data of the buffer memory circuit 2 is transferred to the area designated by the block address of the flash memory circuit 1 by the transfer control circuit 4'in the order of the word address.

When a read request is issued from the main body device 11 to the flash memory device 5 ', the request is accepted by the transfer control circuit 4', and data is read from the area designated by the flash address of the flash memory circuit 1.

[0018]

A storage circuit using a flash memory device has a long erasing time required before writing and a long writing time, and other processing must be interrupted for a long time before writing. There was a problem saying

Further, since data is erased in units of chips, it is necessary to save data once and rewrite it. If the writing frequency is high, the number of writing restrictions of the chip is exceeded in a short period and the flash memory element must be replaced. There was a problem of disappearing.

According to the present invention, the data to be written in the flash memory circuit is temporarily stored until it reaches a certain amount, and then the data is written in the flash memory circuit.
It is an object to provide an efficient and economical flash memory device.

[0021]

FIG. 1 is a diagram illustrating the principle of the present invention. In FIG. 1, 1 is a flash memory circuit, 2 is a buffer memory circuit, 3 is a buffer circuit, 4 is a transfer control circuit, 5 is a flash memory device, 6 is a data line, Reference numerals 7 and 9 are control lines, 8 and 10 are address lines, and 11 is a main unit.

In the buffer circuit 3, buffer data divided into a block address, a word address, new data and a flag is stored in an area designated by a buffer address, and the buffer memory circuit 2 and the main unit are connected via a data line 6. 11 is a storage circuit which is connected to 11 and is connected to the transfer control circuit 4 through the control line 9 and the address line 10 and is read and written by the transfer control circuit 4 in units of individual addresses.

The transfer control circuit 4 is connected to the main body device 11 via the control line 7 and the address line 8, and is connected to the flash memory circuit 1, the buffer memory circuit 2 and the buffer circuit 3 via the control line 9, and the address It is connected to the flash memory circuit 1, the buffer memory circuit 2, and the buffer circuit 3 via a line 10, receives a request from the main body device 11,
A transfer control circuit that controls erasing, reading, and writing of the flash memory circuit 1, controls reading and writing of the buffer memory circuit 2, and controls reading and writing of the buffer circuit 3.

The flash memory device 5 is connected to the main body device 11 via a data line 6, a control line 7 and an address line 8 and is composed of a flash memory circuit 1, a buffer memory circuit 2, a buffer circuit 3 and a transfer control circuit 4. It is a storage device.

The principle of the present invention will be described with reference to FIG. When the main body device 11 requests writing of new data to the area specified by the flash address, the request is accepted by the transfer control circuit 4.

Next, the buffer address is sequentially changed, the buffer data is read from the buffer circuit 3, and it is searched whether or not the writing of the new data to the area has been performed prior to the request.

That is, an area designated by the buffer address of the buffer circuit 3 is read out, and an address (hereinafter abbreviated as "write address") connecting the block address and the word address stored in the area is illustrated. An indicator (hereinafter referred to as “flag”) that is not stored is referred to, and when the write address and the flash address match and the flag is on, a new area is specified in the area specified by the flash address prior to the request. When it is determined that the data writing is requested, new data is stored in the area specified by the buffer address, the write address and the flash address match, and when the flag is off, the data is specified by the flash address. The area specified by the buffer address is judged to have not been requested to write new data to the area When new data is stored, the flag is turned on, and the area in which the flag is off is read, a buffer address indicating the area is stored as an empty area in the management circuit (not shown) each time, and the block address of the write address and the When the block address of the flash address matches and the area in which the flag is turned on is read, it is considered that new data to be written in the area indicated by the block address is read, and the management circuit for the number of read words (not shown) increments by 1 each time. , Every time one word is read from the buffer circuit 3, the buffer address is incremented by 1, a region where a write address matching the flash address is stored and the new data is written, or the count value of the number of read words is not shown. The value exceeds the value indicated by the management circuit that manages the total number of data write words + 1 and is empty. It repeated until 該新 data is written in the area.

Each time writing is requested from the main unit 11, the process of writing the flash address and the new data to the buffer circuit 3 is repeated until the total number of written words becomes a certain amount or more, and the total number of written words becomes a certain amount. Transfer control circuit 4 when exceeded
Thus, the number of write words for each address is compared, and the transfer processing from the buffer circuit 3 to the buffer memory circuit 2 is performed with the block having the largest number of new data words written in the buffer circuit as the transfer target block.

In the transfer process, first, the area corresponding to the transfer target block of the flash memory circuit 1 is erased.
Next, the number of write words in the transfer target block is set as the number of transfer words, and the buffer address is set to 0.

Then, the buffer data is read from the area designated by the buffer address of the buffer circuit 3,
Buffer data in which the write address matches the flash address and the flag is ON is searched.

When the write data matches the flash address and the buffer data whose flag is on is detected, the new data in the buffer data is designated by the word address in the buffer data of the buffer memory circuit 2. Is written in the area, and the number of transfer words is decremented by one.

From the buffer circuit 3 to the buffer memory circuit 2
The transfer of new data to is repeated while incrementing the buffer address by 1 until the number of transfer words becomes 0. Next, the block address of the transfer target block is set as the transfer address, and the data is transferred from the buffer memory circuit 2 to the area designated by the transfer address of the flash memory circuit 1 in the order of the word address.

The writing process is completed when the final word is transferred. When a flash address is designated from the main body device 11 and data reading is requested, the request is accepted by the transfer control circuit 4.

Next, the search of the buffer circuit 3 for confirming whether the new data of the flash address is stored is performed while sequentially changing the buffer address. The area specified by the buffer address of the buffer circuit 3 is read, the write address and the flag stored in the area are referred to, and the write address and the flash address match and the flag-on buffer data is detected. Then, the new data in the buffer data is transferred to the main body device 11 via the data line 6, and if the write address and the flash address do not match, the transfer destination block is transferred to the management circuit (not shown). The transfer address held as the address is compared with the block address of the flash address. If they match, new data is read from the area designated by the word address of the flash address of the buffer memory circuit 2, and the data line 6 is read. It is transferred to the main unit 11 via the Data is read from the area specified by said flash address memory circuit 1 is transferred to the main unit 11 via the data line 6.

[0035]

2 is a block diagram of an embodiment of the present invention, FIG. 3 is a block diagram of a word number management circuit of an embodiment of the present invention, and FIG. 4 is a buffer circuit configuration of an embodiment of the present invention. FIG. 5 is a configuration diagram of a buffer memory circuit according to an embodiment of the present invention.

In FIG. 2, reference numeral 40 denotes a control circuit, which is 4
1 is an address circuit, 42 is a word number management circuit,
43 is a transfer word number circuit, 44 is an empty area circuit,
Reference numeral 45 is a total write word number circuit, 46 is a transfer address circuit, 47 is a read word number circuit, 48 is a most block circuit, 49 is a most word number circuit, and a control circuit 40 and an address circuit 41 are provided. The transfer control circuit 4 is composed of the word count management circuit 42, the transfer word count circuit 43, the empty area circuit 44, the total write word count circuit 45, the transfer address circuit 46, the read word count circuit 47, the most block circuit 48, and the most word count circuit 49. are doing.

The control circuit 40 includes the main unit 11 and the control line 7.
The flash memory circuit 1, the buffer memory circuit 2, the buffer circuit 3, the address circuit 41, the word number management circuit 42, the transfer word number circuit 43, the empty area circuit 44, the total write word number circuit 45, and the transfer address circuit 46. Is connected to the read word number circuit 47, the most block circuit 48, and the most word number circuit 49 via the control line 9, receives a request from the main body device 11, and receives the main body device 11, the buffer circuit 3, the buffer memory circuit 2, and the flash memory. The control circuit controls data transfer with the circuit 1.

The address circuit 41 is connected to the main body device 11 via the address line 8, is connected to the flash memory circuit 1, the buffer memory circuit 2 and the buffer circuit 3 via the address line 10, and is designated by the main body device 11. It is an address circuit that transfers the generated address to the flash memory circuit 1, the buffer memory circuit 2, and the buffer circuit 3.

The word number management circuit 42 is a management circuit which is connected to the control circuit 40 through the control line 9 and manages the number of buffer data whose flag is turned on as the number of write words in block units.

The transfer word number circuit 43 is connected to the control circuit 40 via the control line 9, sets the number of write words of the transfer target block, and transfers new data from the buffer circuit 3 to the buffer memory circuit 2 each time. It is a count circuit that is decremented by one.

The empty area circuit 44 is connected to the control circuit 40 via the control line 9, and stores the buffer address of the area of the buffer circuit 3 in which new data is not written.
It is used as an address indicating a write destination area when new data needs to be written in a new area of the buffer circuit 3.

The total write word number circuit 45 is connected to the control circuit 40 via the control line 9, and is managed by the word number management circuit 42 in units of blocks, that is, the total sum of the new data accumulated in the buffer circuit 3. This is a management circuit that manages the total number of write words.

The transfer address circuit 46 is a holding circuit which is connected to the control circuit 40 via the control line 9 and holds the write destination block address of the data held in the buffer memory circuit 2.

The read word number circuit 47 is a circuit which is connected to the control circuit 40 via the control line 9 and counts the number of new data read from the buffer circuit 3. The most block circuit 48 is a management circuit which is connected to the control circuit 40 via the control line 9 and manages the block address of the block having the largest number of write words.

The maximum number-of-words circuit 49 is a management circuit which is connected to the control circuit 40 via the control line 9 and manages the maximum number of written words. FIG. 6 is a flowchart (No. 1) of writing one embodiment of the present invention, FIG. 7 is a flowchart (No. 2) of writing one embodiment of the present invention, and FIG. 8 is a flowchart of No. 1 of the present invention.
It is an Example writing flowchart (the 3).

Regarding processing when there is a write request from the main body device 11 to the flash memory device 5, FIG. 6, FIG.
This will be described with reference to FIG. When a flash address is designated from the main body device 11 and a request for writing new data is made, the request is accepted by the transfer control circuit 4.

In step S1, the control circuit 40 sets the buffer address 0 in the address circuit 41 and the read word number circuit 47 in the read word number 0. Step S2
Then, a value obtained by adding +1 to the total number of written words read from the total number of written words circuit 45 is obtained by the control circuit 40 and compared with the number of read words.

When the number of read words exceeds the value obtained by adding 1 to the total number of write words, there is no data designated by the same flash address in all the buffer data of the buffer circuit 3, and new data is newly stored. Assuming that the region to be detected is detected, the process proceeds to step S9.

If the number of read words is less than the value obtained by adding 1 to the total number of write words, the process proceeds to step S3 to continue the search of the buffer circuit 3. In step S3, the control circuit 40 reads the buffer data from the area designated by the buffer address of the buffer circuit 3.

In step S4, the write address and the flash address are compared by the control circuit 40. If they are different, it is determined that there is no data designated by the same flash address, and the process proceeds to step S5. If they match, the process proceeds to step S8. move on.

In step S5, the control circuit 40 checks the flag in the buffer data. If it is on, it is determined that there is new data, and the process proceeds to step S7. If it is off, the flash address has been used in the past. Is determined to be unused at present, and the process proceeds to step S6.

In step S6, the control circuit 40 stores the buffer address in the empty area circuit 44, increments the buffer address by 1, and returns to step S2. In step S7, the control circuit 40 sets the buffer address to +1.
The number of read words is incremented by 1, and the process returns to step S2.

In step S8, the flag in the buffer data is checked by the control circuit 40, and if it is on, it is determined that there is new data, and the process proceeds to step S13. If it is off, the flash address has been used in the past. Is determined to be unused at present, and the process proceeds to step S10.

In step S9, the control circuit 40 reads the buffer address saved in the empty area circuit 44 and replaces it with a new buffer address. In step S10, the control circuit 40 increments the write word count of the block designated by the flash address of the word count management circuit 42 by 1, and increments the total write word count stored in the total write word count circuit 45 by 1.

In step S11, the control circuit 40 reads the number of write words of the block designated by the flash address of the word number management circuit 42, compares the read word number with the value stored in the maximum word number circuit 49, and the word number management circuit 42. If the number of write words in the block designated by the flash address is larger than the value stored in the maximum number of words circuit 49, the process proceeds to step S12, and the number of write words in the block designated by the flash address of the word number management circuit 42 is Maximum number of words circuit 4
If it is less than or equal to the value stored in 9, the process proceeds to step S13.

In step S12, the control circuit 40 writes the number of write words of the block designated by the flash address of the word number management circuit 42 into the maximum number of words circuit 49, and the block address of the block into the maximum number of block circuits 48.

In step S13, the control circuit 40 writes the flash address and new data in the area designated by the buffer address of the buffer circuit 3, and turns on the flag.

In step S14, the total number of written words is read from the total number of written words circuit 45 by the control circuit 40 and compared with the number of words in the buffer circuit 3 (the number of words = i in the case of FIG. 4). It is determined that the buffer circuit 3 is in use with 100% new data, and the process proceeds to step S16. If different, the process proceeds to step S15.

In step S15, the control circuit 40 waits for a write request from the main body device 11. If there is a write request, the process proceeds to step S1. In step S16, the control circuit 40 reads the block address from the most block circuit 48, and the data of one block indicated by the block address of the flash memory circuit 1 is transferred to the buffer memory circuit 2. Further, the block address is set in the transfer address circuit 46, the number of write words is transferred from the maximum number of words circuit 49 to the transfer word number circuit 43, and the number of write words is minus from the value stored in the total number of write words circuit 45. To be done.

In step S17, the area designated by the transfer address circuit 46 is erased by the control circuit 40.
Further, the number of write words is sequentially read from the word number management circuit 42, and the block address of the block having the largest number of write words next to the block designated by the transfer address circuit 46 is supplied to the block circuit 48 having the largest number of write words. The maximum number of words circuit 49 is set.

In step S18, the control circuit 40 sets the buffer address 0 in the address circuit 41.
In step S19, the number of transfer words is checked by the control circuit 40, and if it is less than 0, it is determined that all new data has been transferred to the buffer memory circuit 2 in step S19.
If it is 0 or more, it is determined that the new data still remains in the buffer circuit 3, and the process proceeds to step S20.

In step S20, the control circuit 40 reads the buffer data from the area designated by the buffer address of the buffer circuit 3. In step S21, the control circuit 40 compares the block address of the buffer data with the block address read from the transfer address circuit 46, and if they match, step S2.
2, the process proceeds to step S24 if they differ.

In step S22, the flag of the buffer data is checked by the control circuit 40. When the flag is on, it is determined that the data is new data and the process proceeds to step S23. When it is off, it is determined that the data is not new data and the process proceeds to step S24. move on.

In step S23, the control circuit 40 writes new data of the buffer data into the area designated by the word address of the buffer data of the buffer memory circuit 2, and the area indicated by the buffer address of the buffer circuit 3. Flag is turned off, and the transfer word number circuit 43
The number of transfer words is decremented by one.

In step S24, the control circuit 40 increments the buffer address by 1, and the process returns to step S19.
In step S25, the control circuit 40 sequentially transfers data from the word address 0 to the final address from the buffer memory circuit 2 to the flash memory circuit 1, and the writing process is completed.

FIG. 9 is a flow chart (No. 1) for reading one embodiment of the present invention, and FIG. 10 is a flow chart (No. 2) for reading one embodiment of the present invention. Main unit 11
FIG. 9 shows the processing when the reading is requested from
This will be described with reference to FIG.

From the main body device 11 to the flash memory device 5
On the other hand, when a data read request is made by designating a flash address, the request is accepted by the transfer control circuit 4.
In step S1, the control circuit 40 causes the address circuit 4
The buffer address 0 is set to 1 and the word number management circuit 42
The write word number of the block designated by the block address of the flash address read from
Is set as the number of read words.

In step S2, the number of read words is checked by the control circuit 40. If the number of read words is less than 0, it is determined that the new data of the buffer address does not exist in the buffer circuit 3, and the process proceeds to step S10. Continues to search the buffer circuit 3, the process proceeds to step S3.

In step S3, the control circuit 40 reads the buffer data from the area designated by the buffer address of the buffer circuit 3. In step S4, the flag in the buffer data is checked by the control circuit 40. If it is on, the process proceeds to step S5, and if it is off, the process proceeds to step S8.

In step S5, the control circuit 40 compares the write address in the buffer data with the flash address. If they match, it is determined that there is new data in the buffer circuit 3 and the process proceeds to step S9. In order to continue the search, the process proceeds to step S6.

In step S6, the control circuit 40 compares the block address in the buffer data with the block address of the flash address. If they match, the process proceeds to step S7. If they do not match, the process proceeds to step S8.

In step S7, the control circuit 40 decrements the read word number circuit 47 by one. In step S8, the control circuit 40 increments the buffer address by 1, and the process returns to step S2.

In step S9, the control circuit 40 transfers the new data to the main body device 11, and the process ends. In step S10, the block address read from the transfer address circuit 46 by the control circuit 40 is compared with the block address of the flash address. If they match, the process proceeds to step S11, and if they do not match, the process proceeds to step S12.

In step S11, the control circuit 40 reads the data from the area specified by the word address of the flash address of the buffer memory circuit 2, transfers the data to the main body device 11, and ends the processing.

In step S12, the control circuit 40 reads the data from the area designated by the flash address of the flash memory circuit 1, transfers the data to the main body device 11, and ends the processing.

Although the transfer control circuit 4 is composed of individual circuits in this embodiment, the same operation can be performed by providing a region corresponding to each individual circuit on the memory circuit and controlling by the processor.

[0077]

As is apparent from the above description, according to the present invention, the number of data writes from the external device to the flash memory circuit can be reduced, so that the replacement interval of the flash memory elements is extended and the total processing time required for the data write is increased. There is a remarkable industrial effect that can shorten.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment of the present invention.

FIG. 3 is a block diagram of a word count management circuit according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a buffer circuit according to an embodiment of the present invention.

FIG. 5 is a block diagram of a buffer memory circuit according to an embodiment of the present invention.

FIG. 6 is a first embodiment writing flowchart of the present invention (No. 1)

FIG. 7 is a writing flowchart (part 2) of the embodiment of the present invention.

FIG. 8 is a writing flowchart (part 3) of the embodiment of the present invention.

FIG. 9 is a flowchart (No. 1) for reading out an embodiment of the present invention.

FIG. 10 is a flowchart (No. 2) of reading out an embodiment of the present invention.

FIG. 11 is a configuration diagram of a conventional example.

FIG. 12 is a flowchart of a conventional example.

[Explanation of symbols]

 1 Flash Memory Circuit 2 Buffer Memory Circuit 3 Buffer Circuit 4, 4'Transfer Control Circuit 5, 5'Flash Memory Device 6 Data Line 7, 9 Control Line 8, 10 Address Line 11 Main Unit 40 Control Circuit 41 Address Circuit 42 Word Count Management Circuit 43 Transfer word number circuit 44 Empty area circuit 45 Total write word number circuit 46 Transfer address circuit 47 Read word number circuit 48 Most block circuit 49 Most word number circuit

Claims (4)

[Claims] 1. In a flash memory device, which erases already stored data and then writes new data to a flash memory circuit at the time of writing, a first buffer circuit and a second buffer circuit connected by a data bus. And a flash memory circuit, the new data is temporarily stored in the first buffer circuit, and the new data is stored in the second buffer circuit when a certain amount of the new data is accumulated in the first buffer circuit. To the flash memory circuit in the second buffer circuit, and transfers the data from the second buffer circuit to the flash memory circuit. 2. The flash memory device according to claim 1, wherein a write destination address of the flash memory circuit is stored together with new data in the first buffer circuit. 3. A write destination address of the flash memory circuit stored in the first buffer circuit is searched,
2. The flash memory device according to claim 1, wherein only new data in the erased block of the flash memory circuit is transferred to the second buffer circuit. 4. In response to a read request, the first buffer circuit is searched first, the second buffer circuit is searched when there is no data in the first buffer circuit, and the second buffer circuit is searched. 2. The flash memory device according to claim 1, wherein data is read from the flash memory circuit when there is no data in the flash memory device.