JPH09512967A - 適応型境界バッファ - Google Patents
適応型境界バッファInfo
- Publication number
- JPH09512967A JPH09512967A JP7525490A JP52549095A JPH09512967A JP H09512967 A JPH09512967 A JP H09512967A JP 7525490 A JP7525490 A JP 7525490A JP 52549095 A JP52549095 A JP 52549095A JP H09512967 A JPH09512967 A JP H09512967A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- phase
- control device
- error
- buffer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 29
- 230000003044 adaptive effect Effects 0.000 title abstract description 5
- 230000003111 delayed effect Effects 0.000 claims abstract description 7
- 238000011084 recovery Methods 0.000 claims description 6
- 230000006978 adaptation Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 3
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000002311 subsequent effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0046—User Network Interface
- H04J2203/005—Terminal equipment, e.g. codecs, synch
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims (1)
- 【特許請求の範囲】 1.電気通信システムの受信装置からの回復回線クロックと回復戻りクロックと の間の位相のエラーを測定するための手段を備える位相調整手段を有し、回復戻 りクロックの位相は、位相エラーの値により進むか遅れるかし、回復回線クロッ クの位相は、位相エラーの値より少ないことによりそれぞれ遅れるか進むかし、 位相調整された出力回線クロックを生み出す、電気通信システムにおいて使用さ れる境界バッファ制御装置。 2.特許請求の範囲第1項に記載の制御装置において、バッファがオーバーフロ ーし、あるいは、空になるのを防ぐための制御手段を有する制御装置。 3.特許請求の範囲第1項または第2項に記載の制御装置において、位相調整の 度数を調整するための手段をさらに有する制御装置。 4.特許請求の範囲第1項から第3項のいずれかに記載の制御装置において、各 フレームにつき1度以下の位相エラーが測定される、制御装置。 5.特許請求の範囲第1項から第4項のいずれかに記載の制御装置において、調 整の割合がプログラム可能な制御装置。 6.特許請求の範囲第1項から第5項のいずれかに記載の制御装置において、同 期ディジタル階層を用いる制御装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB9406324.5 | 1994-03-30 | ||
GB9406324A GB9406324D0 (en) | 1994-03-30 | 1994-03-30 | Adaptive boundary buffers |
PCT/GB1995/000695 WO1995027351A1 (en) | 1994-03-30 | 1995-03-28 | Adaptive boundary buffers |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH09512967A true JPH09512967A (ja) | 1997-12-22 |
JP3530967B2 JP3530967B2 (ja) | 2004-05-24 |
Family
ID=10752766
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP52549095A Expired - Lifetime JP3530967B2 (ja) | 1994-03-30 | 1995-03-28 | 適応型境界バッファ |
Country Status (10)
Country | Link |
---|---|
US (1) | US5923669A (ja) |
EP (1) | EP0753227B1 (ja) |
JP (1) | JP3530967B2 (ja) |
CN (1) | CN1076913C (ja) |
AU (1) | AU689245B2 (ja) |
DE (1) | DE69531238T2 (ja) |
GB (2) | GB9406324D0 (ja) |
NO (1) | NO964043L (ja) |
WO (1) | WO1995027351A1 (ja) |
ZA (1) | ZA952530B (ja) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE19947095A1 (de) * | 1999-09-30 | 2001-05-03 | Siemens Ag | Vorrichtung zur Synchronisierung des Rahmentaktes in Einheiten/Knoten datenübertragender Systeme |
US20070189428A1 (en) * | 2006-02-14 | 2007-08-16 | Knerr Barry F | Method and system for automatically calibrating a clock oscillator in a base station |
US20090135854A1 (en) * | 2007-11-27 | 2009-05-28 | Mark Bettin | System and method for clock synchronization |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4831637A (en) * | 1984-06-19 | 1989-05-16 | American Telephone And Telegraph Company | Apparatus and technique for timing jitter cancellation in a data receiver |
FR2668323B1 (fr) * | 1990-10-17 | 1993-01-15 | Telecommunications Sa | Dispositif de reduction de la gigue due aux sauts de pointeurs dans un reseau de telecommunications numeriques. |
US5268936A (en) * | 1991-07-08 | 1993-12-07 | At&T Bell Laboratories | Synchronous digital signal to asynchronous digital signal desynchronizer |
US5319680A (en) * | 1991-09-03 | 1994-06-07 | The Whitaker Corporation | Phase locked loop synchronization system for use in data communications |
US5517521A (en) * | 1993-06-25 | 1996-05-14 | Digital Wireless Corporation | Method and apparatus for synchronization between real-time sampled audio applications operating full-duplex over a half-duplex radio link |
-
1994
- 1994-03-30 GB GB9406324A patent/GB9406324D0/en active Pending
-
1995
- 1995-03-28 AU AU20772/95A patent/AU689245B2/en not_active Ceased
- 1995-03-28 EP EP95913228A patent/EP0753227B1/en not_active Expired - Lifetime
- 1995-03-28 CN CN95192373A patent/CN1076913C/zh not_active Expired - Lifetime
- 1995-03-28 JP JP52549095A patent/JP3530967B2/ja not_active Expired - Lifetime
- 1995-03-28 GB GB9506327A patent/GB2288106B/en not_active Expired - Lifetime
- 1995-03-28 ZA ZA952530A patent/ZA952530B/xx unknown
- 1995-03-28 DE DE69531238T patent/DE69531238T2/de not_active Expired - Lifetime
- 1995-03-28 US US08/704,552 patent/US5923669A/en not_active Expired - Lifetime
- 1995-03-28 WO PCT/GB1995/000695 patent/WO1995027351A1/en active IP Right Grant
-
1996
- 1996-09-26 NO NO964043A patent/NO964043L/no unknown
Also Published As
Publication number | Publication date |
---|---|
GB9506327D0 (en) | 1995-05-17 |
GB2288106B (en) | 1999-01-06 |
WO1995027351A1 (en) | 1995-10-12 |
GB2288106A (en) | 1995-10-04 |
CN1076913C (zh) | 2001-12-26 |
EP0753227A1 (en) | 1997-01-15 |
ZA952530B (en) | 1995-12-21 |
AU689245B2 (en) | 1998-03-26 |
US5923669A (en) | 1999-07-13 |
EP0753227B1 (en) | 2003-07-09 |
CN1145148A (zh) | 1997-03-12 |
DE69531238T2 (de) | 2004-02-05 |
NO964043D0 (no) | 1996-09-26 |
JP3530967B2 (ja) | 2004-05-24 |
AU2077295A (en) | 1995-10-23 |
NO964043L (no) | 1996-09-26 |
DE69531238D1 (de) | 2003-08-14 |
GB9406324D0 (en) | 1994-05-25 |
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