AU669315B2 - Arrangement for recovering a plesiochronous digital signal - Google Patents

Description

Description Arrangement for recovering a plesiochronous digital signal The invention relates to an arrangement for recovering a plesiochronous digital signal.

In order to be able to transmit plesiochronous digital signals in a data channel having a constant bit rate, the bit rates are matched by stuffing. The transmitted signal contains the data signal and, at periodic intervals, stuffing bit positions which, depending upon requirement, contain either bits of the data signal or blank bits. When the bit rate of the data signal lags behind the reserved bit transfer rate, it is necessary to insert blank bits; this is designated as positive stuffing.

If, by contrast, the bit rate of the data signal exceeds the reserved bit transfer rate, at least one data bit is additionally inserted into the stuffing bit position(s); this is designated as negative stuffing.

Stuffing methods which use both types of stuffing are designated as positive-zero-negative stuffing methods.

These methods are applied even when a plurality of digital signals are combined to form a multiplex signal .oooo: S"or when multiplex signals of a lower hierarchy level are combined to form a multiplex signal of a higher hierarchy level, as is performed, for example, in the case of the conventional PCM multiplex methods or in the case of the synchronous digital hierarchy (SDH).

The stuffing operations respectively comprise one bit or a plurality of bits, and also one or more bytes.

Each stuffing operation generates a phase shift in the outgoing digital signal. At the receiving end, the digital signal is read into a buffer memory by means of a gap clock signal and read out by means of a continuous clock signal. The phase shifts in the digital signal or in the associated output clock signal are smoothed at the receiving location by an analog or digital phase-locked 2 loop (PLL). The phase-locked loop acts in accordance with its dimensioning as a low-pass filter. The amplitude of the phase shifts (jitter) caused by stuffing is strongly reduced by the phase-locked loop if the time interval of the phase shifts is very small by comparison with the time constant of the phase-locked loop.

In the case of the positive-zero-negative stuffing method, the time intervals of the phase shifts can, however, be very large. In this case, without additional measures the phase shifts would be weakly damped by the phase-locked loop. The international patent application WO 91/12678 discloses a method and an arrangement for timing recovery. Abrupt changes in the correcting quantity for the phase-locked loop are firstly suppressed, in order then to be relayed continuously or in small steps within a lengthy balancing time to a digitally designed phase-locked loop. The control of the phase-locked loop is performed as a function of the level of a ramp counter into which initial values are loaded during stuffing operations. Only in the end position of the ramp counter is a PLL counter, which determines the "..frequency of the output clock, controlled by the occupancy of the buffer memory. The loop is designed in such a way that phase correction is continuously 25 performed even in the case of a synchronous clock signal.

The realization requires numerous counters and a relatively complicated arithmetic. As a result, there is only a slow change in the phase of the clock signal.

Due to the low speed of the phase correction, a jitter otherwise generated becomes a gradual change in the phase, designated as wander.

The object of the invention is to specify a simpler digitally operating arrangement for the receiving section, which generates only minimum jitter at high frequency. It should be possible for this to be matched easily to the different data rates.

This object is achieved by means of the arrangement, specified in Claim 1, for recovering a digital signal.

3 Advantageous embodiments are specified in the subclaims.

It is particularly advantageous in the arrangement that the control of phase correction is performed only by the stuffing information, and is not, as previously, made dependent on the memory contents. The occupancy of the memory is also used as a control criterion for the phase correction only in the connection phase and in the case of interference. There is no need in this arrangement for an auxiliary oscillator.

Particularly advantageous is the use of an aperiodic/quasiperiodic divider by means of which all the rational division ratios can be realized. Only minimum jitter is caused by inserting or gating out subperiods of this divider.

It is expedient to use a ramp generator to control the stuffing operations. In each stuffing operation, a numerical value is loaded which is reduced again to its zero value in numerous phase corrections.

The speed of the phase correction can also be a function of the magnitude and the frequency of the required phase correction prescribed by the stuffing information. One of the greatest advantages of the invention consists in the use of programmable devices. As 25 a result of this, the arrangement can be matched to the most varied data rates and to all the requirements in the stuffing operations.

The invention will be explained in more detail with the aid of figures in, which: Figure 1 shows a block diagram of the arrangement, Figure 2 shows a block diagram of a controllable A/B frequency divider, Figure 3 shows a block diagram of a ramp generator, Figure 4 shows a variant of the ramp generator for different time constants.

The block diagram represented in Figure 1 contains a clock regenerator 2 which is fed a synchronous multiplex signal MS via the input i. The output of the clock regenerator is connected to a "frame detector and L I 4 clock-pulse supply" 3 which supplies gap clock pulses TL1 to TLN, assigned to the individual digital signals, and the corresponding stuffing information SIl to SIN.

Circuits for a clock regenerator 2 and a "frame detector and clock-pulse supply" 3 are familiar to any person skilled in the art and are described, for example, in "Digitale Ubertragungstechnik" ("Digital Transmission Technology") by Peter Kahl, Decker's Verlag, Vol. 1 in 2.1.2.3.10, pages 22 to The received multiplex signal MS is fed to the data inputs, for example the data input 61, of N buffer memories, of which only the buffer memory 6 for the first data signal DS1 is represented. One output of the "frame detector and clock-pulse supply" 3, at which a write clock having gaps is output, is connected to a write clock input 63 of the buffer memory. The stuffing information signals SIl to SIN are fed in each case to a ramp counter 5 from the "frame detector and the clockpulse supply" 3 via a coder 4. The outputs 53 and 54 of said ramp counter are connected by a logic circuit 7 to the control inputs 81 and 82, respectively, of a frequency divider 8 whose clock input E8 is fed to the system clock TS.

The clock output 11 of the frequency divider 8 is 25 connected to the read clock input 64 of the buffer memory 6. A timer 9 supplies a memory clock pulse TE, derived from the system clock TS, to the logic circuit 7. The buffer memory 6, the ramp counter 5 and the frequency divider 8 are provided separately for each digital signal. The coder 4 and the timer 9 (or parts of these) can be used jointly for all the digital signals.

The system clock TS is derived in the clock regenerator 2 from the multiplex signal MS present at the input i. The "frame detector and clock-pulse supply" 3 detects the starter frame by means of a frame alignment word or appropriately fixed bit trains, and assigns the individual data signals, for example the digital signal DS1, a corresponding gap clock pulse, the write clock pulse TL1, by means of which the digital signal DSl is cc r o s o II Q -7 5 written into the buffer memory 6.

The task of the ramp counter 5, the timer 9 and the frequency divider 8 consists in generating an output clock pulse TA1 which is as uniform as possible and by means of which the digital signal TS1 is read out from the buffer memory 6 and output at the data output 62 of the buffer and at the digital signal output 10, while the associated clock pulse TAl is present at the clock pulse output 11. The data rate of the received digital signal and that of the digital signal read out must correspond on average.

By contrast with the known circuits for clock matching at the receiving end, the output clock signal TA.1 is not controlled by the occupancy of the buffer memory but by the stuffing information SIl (if interference from the transmission path and the connection phase are disregarded).

The aim is firstly to explain in more detail the functioning of the frequency divider 8 represented more precisely in Figure 2. The frequency divider 8 permits the aperiodically quasi-periodic frequency synthesis or frequency division as described in the journal Frequenz 27, (1973) 9, pages 249 to 214 and Frequenz 27 (1973) pages 279 to 283. It comprises a first reversible A/B divider 86, whose clock input E8 is fed with the system clock signal TS and which outputs the output clock signal TAl at the clock output 11. Connected downstream of this divider is a further C-divider 87, which counts the subperiods and whose counter reading ZC specifies via a decoder 88 the current subperiod A or B of the A/B divider 86 and control signals SAP and SEP for fixing the next subperiod.

The outputs of the decoder are led to synchronizing inputs 83 and 84 of a synchronizing circuit 09. Phase correction commands EB and AB are fed to the latter via the control inputs 81 and 82. The control output A89 is led to the control input of the C-divider 87.

Every rational division ratio can initially be realized with the aid of this divider arrangement.

o 6 An example of this: The frequency of the system clock is 129.6 MHz and the clock frequency of the output clock pulse TA is 2.048 MHz. This yields a division ratio of f, 129.6 2025 f, 2.048 32 With n 23 A-subperiods and m 9 B-subperiods, this division ratio can be realized using an A/B divider 86, which can generate the subperiod A 63 and the subperiod B 64, and a C-divider, which has a counting range of 32 A- and B-subperiods.

A suitable subperiod distribution for this purpose is: BAAA BAA BAAA BAA BAAA BAA BAAA BAA BAAA After each subperiod A or B, one pulse of the output clock signal TAl is output, by means of which the digital signal DS1 is read out. These pulses of the output clock signal and the steps (bits) of the digital 20 signal have a minimum jitter which is caused by the V •frequency division and does not need to be further reduced.

"*This exact division ratio renders adding operations superfluous whenever synchronous digital signals are transmitted. However, since it is plesiochronous signals which are concerned here, as a rule, the phase of the A/B divider must be adjusted. In the solutions to date, this is performed by gating in or out one or more Spulses of the input clock signal (system clock signal TS), with the result that the frequency divider has a shorter or longer period.

Another correction method is selected here in order to reduce the jitter further. A subperiod A or B is gated in or out via the synchronizing circuit by mneans of a synchronizing signal SY engaging in the C-divider.

The gating in or out of a subperiod can be 7 performed in equal time intervals which are fixed by the timer 9 and correspond to a normal superperiod with 32 subperiods. If this happens to be an unsuitable Bsubperiod, the next A-subperiod is gated in or out. The timer 9 can also be replaced by the dividers 86, 87 and the decoder 88. A modified storage clock signal TEC is generated, whose clock pulses, although having slightly differing intervals during gating in and out always occur, in return, at the same position of a superperiod as in the following example and pass via the dashed connection from the decoder to the synchronizing circuit 89.

In the case of the small frequency differences, correction operations are performed at longer time intervals. By contrast, the aim in the following example, which serves merely to determine the magnitude of a correction step, one correction step is to be performed in each row. This is explained in more detail with the aid of the following Table 1. The aim is, for example, to o. 20 gate in a short A-subperiod; this is the subperiod A.

Table 1 1 32 a 00) BAAABAABAAABAABAAABAABAAABAABAAA a01) BAAABAAABAAABAABAAAABAA ABAAABAABAA A *0o* b01) BAAABAAAAAABAAABABAAABAABAAABAABAA b02) ABABAAABAAABAAABAABAAAABAAABAABA b03) AABAAABAAAABAABAABAAABAABAAABAAB b04) AAABAAABAAABAAABAABAAABAABAAABAA b27) ABABBAAABAABAAABAABAAAB AAABAAABA bOO) AABAAABAABAAABAABAAABAABAAABAAAB b28) AAABAAABAABAAABAABAAABAABAAABAAA

ABAAABAAABAABAAABAABAAABAABAAABA

b31) AABAAABAA AAAAABAABAABAABAAABAABAAAJI b32) AAABAAABAAABAABAAABAABAAABAABAAA a00) BAAABAABAAABAABAAABAABAAABAABAAA 8 The first row aOO) shows the regular superperiod of the frevuency divider 8. By inserting an A subperiod, for example in the sixth position, a lengthened superperiod a01) is produced which has one short A-subperiod more, that is to say there is a slight reduction in the average subperiod duration. Starting from the inserted Asubperiod, with reference to the initial subperiod duration the period pattern is displaced to the right after each insertion of an A-subperiod. The next row b01) in the table shows only the 32 subperiods which belong to a superperiod. The last A-subperiod characterized by a preceding interspace becomes the first subperiod of the next superperiod b02) having 32 subperiods. Many of these correction steps are required in order to be able to correct the phase of the output clock pulse by an additionally inserted stuffing bit. Some of the superperiods resulting herefrom are shown referred to the initial time frame in Table 1.

The original superperiod is reconstituted after 20 32 correction steps. A total of 9 B-subperiods were replaced by 9 A-subperiods during the 32 correction steps (that is to say, in the table, after 32 successive superperiods each having 32 subperiods), and as a result the phase was corrected by 9 periods of the system clock signal. (The superperiod bOO) without correction was not included in the count). The phase correction thus obtained amounted on average per correction step (per inserted A-period) to: 9 1 1 2025: 1 A UI where UI 2 ;UI bit 3 2 fs 225 32 f T duration of the output digital signal of 2.048 Mbit/s).

It is therefore necessary to gate in N 225 of these A-subperiods in order to achieve overall a phase correction of one UI.

An extremely fine phasing of the working clock pulse is therefore possible by means of the insertion (or gating out) of subperiods, the jitter frequency being 9 virtually unchanged, and a phase correction making up only fractions of a period of the system clock signal TS.

The circuits for the A/B-divider 86, the Cdivider 87 and the decoder 88 can be realized in the most varied way by the person skilled in the art. It is also sufficient to feed a line back for the purpose of controlling the A- or B-period, if the correct instants for switching over between the periods are realized in the A/B-divider 86 itself.

Gating periods in and out is performed via the control inputs 81 and 82. At a suitable position fixed by the decoder 88 and the synchronizing circuit 89, an "insertion instruction" EB effects the gating in of a further A-period by gating out a clock pulse fed to the C-divider 87 (or a switchover of the period) by means of a corresponding synchronizing instruction SY. By contrast, a gate-out instruction" AB effects an o• •additional pulse, with the result that the C-counter :reaches its end position more rapidly, that is to say 20 requires only C-I counting pulses.

An exemplary embodiment of the ramp generator is represented in Figure 3. Said generator contains a logic unit LE5, which possibly contains the coder 4, and an up-down counter VR5 having a counting range of Zm.

The logic unit is fed either the stuffing information SI, which it then converts into a numerical value, or is already fed the appropriate numerical value, in this example +N +225) or which contains the number of the correction operations to be carried out (the A-period to be gated in or out). The logic unit LE5 serves to set the up-down counter VR5, at whose output 53 a counter reading and at whose output 54 a counter reading <0 are output. Via the logic circuit 7, which here contains two AND gates N1 and N2, the frequency divider 8 is driven, that is to say an A-period 'or B-period) is gated in or out, at the instants at which a storage pulse TE is respectively output by the timer 9.

The counter reading zero of the up-down counter is taken as the starting point for a functional 10 description, that is to say the frequency divider 8 operates with its desired division ratio (2025/32 in the example).

If a phase correction by one bit is to be performed, a specific numerical value +N 225 must be loaded into the up-down counter VR5. As a resut, the counter reading Z 0, and thus the first AND gate AND1 is released at the instant of the storage pulse TE.

Consequently, the frequency divider 8 is fed a first insertion instruction EB which in this example inserts an A-period. As a result, a minimum positive phase shift is produced at the clock output 85. The insertion instruction EB is fed back via the logic unit and effects the downward counting of the up-down counter by 1. This operation is repeated a further 224 times until the numerical value corresponding to the phase shift of 1 bit is processed and the zero position is reached again.

*If, by contrast, the counter reading is not equal 20 to zero in the case of a gating in instruction which is present, the numerical value 225 is then added to the current counter reading in the logic unit LE5. In the .case of an oppositely directed gating-out command AB, a co" corresponding negative numerical value N is input into the counter and added to the counter reading, and in :i this example a corresponding number of A-periods are gated out which act at the output 85 of frequency divider as minimum negative phase shifts.

Monitoring of the memory contents need no longer be performed in the "steady" state of the arrangement.

However, it is possible for maloperation to occur in the case of the memory occupancy during the connecting phase and in the event of transmission errors in the stuffing information. An additional phase correction of the output clock pu'se TA, and thus a normalization of the occupancy level, can therefore be performed by a first OR gate OR1 in the case of an excessively full memory, or via a second OR gate OR2 in the case of an excessively empty memory by means of appropriate phase correction signals 11 +SF and -SF, that is to say by inputting a numerical value or a plurality of numerical values.

A variable number of stuffing bits or stuffing bytes are used in some systems. This means only that the input numerical value N is appropriately increased when there is a need to correct more than one bit. If a new stuffinc' instruction is present before the old stuffing instruction has been processed, the new numerical value N (or to be stored is added to or subtracted from the counter read..ng Z, and the counter is reloaded with the result.

This control loop always operates at the correction speed prescribed by the timer 9. This speed can, of course, also be rendered variable by making the period of the storage clock pulse TE dependent on the magnitude of the stuffing criterion. Again, numerous circuit variants are conceivable for this purpose.

A possibility for realizing different phase correction speeds is represented in Figure 4. The logic 20 circuit 7* connected between the ramp generator 5 and the frequency divider 8 contains a so-called segmenter 71, to whose outputs two distributor circuits 72 and 73 are respectively connected. The timer 9* supplies four different pulse trains having the same phase spacings.

The segmenter 71 now switches through one, two or four :..storage clock pulses TE1...TE4 during one period of the timer 9* as a function of the correction signals KS determined from the counter reading Z of the ramp counter as a result of which subperiods can be multiply gated in or out during one period. In order to save connecting lines, storage pulses can be transmitted at an appropriately higher pulse repetition rate (this corresponds to the combination of the pulses TEl to TE4 via an OR circuit) to the individual distributor circuits, and the pulse trains can be generated at partially lower pulse repetition rates by frequency dividers.

The segmenter 71 can also be a part of the synchronization circuit 89 in Figure 2, which is then also fed the counter reading Z of the ramp counter via a 12 further control input E89.

A further possibility for realizing a phase correction speed dependent on the counter reading Z consists in loading the counter reading Z into a further counter having a longer counting period (or to subtract it in advance from a constant), at the final reading of which a correction pulse is output, as is the case in the prior art described at the beginning.

Claims (8)

1. Arrangement for recovering at least one plesio- chronous digital signal (DS1) which is transmitted in time slots of a synchronous signal frequency differences being compensated by stuffing, having at the receiving end a buffer memory into which the digital signal (DS1) is written by means of a write clock pulse (TL1) and is read out by means of an output clock pulse (TAl), characterized in that a ramp generator VR5) is provided in which a numerical value (for example corresponding to the magnitude of the stuffing opera- tion is stored, in that a frequency divider is provided for generating the output clock pulse (TAl), to whose control inputs (81, 82) the control outputs (53, 54) of the ramp generator LE5, VR5) are led, and in that a timer is provided which outputs at pre- determined intervals a storage clock signal (TE, TEC) which on the basis of the counter reading of the ramp generator LE5, VR5) controls a change in the super- 20 period (BAAABAA......BAAA) of the frequency divider (8) and simultaneously effects a reduction in the counter reading in the direction of the zero position of the ramp generator LE5, Arrangement according to Claim 1, characterized in that the frequency divider is constructed as an aperiodic/quasiperiodic divider (86, 87, 88) which has at least two different subperiods B).

3. Arrangement according to Claim 2, characterized in that the frequency divider las a synchronizing circuit (89) which controls the phase correction of the output clock pulse (TAl) by gating subperiods (for example A) in and out.

4. Arrangement according to Claim 2 or 3, character- ized in that the frequency divider contains a con- trollable A/B divider (86) which outputs the output clock pulse (TAl), in that connected to the output of the A/B divider (86) is a C-divider (87) which counts the number (C 32) of the subperiods B) per superperiod, in that downstream of the C-divider (87) a decoder (88) is I 14 r o o connected which decodes the associated subperiod B) from the current counter reading and outputs corres- ponding control signals (SAP, SBP) for the A/B divider and in that the synchronizing circuit (89) has correction inputs (E83, E84) for phase correction instructions (EB, AB) and control inputs (E81, E82) via which the current subperiod B) is signalled to it by the decoder and controls the counting period of the C-divider (87) via a control output (A89).

5. Arrangement according to one of the preceding claims, characterized in that the ramp generator contains an up-down counter (1rR5) which upon the occur- rence of a stuffing information signal (SII) is loaded with a numerical value (for example whose absolute value is reduced by means of each phase correction instruction (EB, AB) caused by it.

6. Arrangement according to one of the preceding claims, characterized in that a timer is provided which outputs the storage clock signal (TE, TEC) which jointly controls frequency dividers (85, 86, 87) with a phase correction instruction (EB, AB).

7. Arrangement according to Claim 6, characterized in that only one timer is provided for a plurality of digital signals and in that a logic circuit which generates a sequence of correction instructions (EB, AB) which is a function of the counter reading is inserted between ramp generator and frequency divider

8. Arrangement according to one of Claims 1 to characterized in that the decoder (88) outputs a modified storage clock signal (TEC) which jointly controls the frequency divider 86, 87) with a phase correction instruction (EB, AB) as a function of the counter reading of the ramp generator

9. Arrangement according to one of Claims 5 to 8, characterized in that a phase correction signal (+SF, -SF) dependent on the occupancy level of the buffer memory is fed to the ramp generator i0. Arrangement according to one of the preceding 15 claims, characterized in that a programmxable ramp counter and/or a programmable frequency divider is provided. DATED this TWENTY FIRST day of MARCH 1995 Siemens Aktiengesel lschaft Patent Attorneys f or the Applicant SPRUSON &FERGUSON Arrangement for Recovering a Plesiochronous Digital Signal Abstract The arrangement for the recovering a plesiochronous digital signal (DS1) contains a buffer memory a ramp generator and a controllable aperiodic quasiperiodic divider which supplies the output clock pulse (TAI) for reading out a digital signal (DS1). The counter reading of the ramp generator is reduced in accordance with the received stuffing information (SI5) until the correct phase correction is carried out. s o r r a u a DLG:9296W