JPH0951004A - Semiconductor device and fabrication of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has prevented deterioration of characteristics due to damage in the channel region occurring when a protec tion film on a high conductive region. SOLUTION: Difference ((Wgp-L) between the length Wgp of the umbrella part of a T type gate electrode 7a in the channel direction is set to 0.6μm or more but is 2.0μm or less and more preferably to 1.0μm or more but is 2.0μm or less. Thereby, damage by etching on the channel region between the high conductive regions 5a, 5b can be prevented and increase of source resistance can be controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a T-type gate electrode and a method of manufacturing the same.

[0002]

2. Description of the Related Art In field effect transistors such as MESFETs (metal-semiconductor field effect transistors) and HEMTs (high electron mobility transistors) using compound semiconductors such as GaAs, heat-resistant T-types made of refractory metal. A gate electrode is used.

A conventional method of manufacturing a semiconductor device having a T-shaped gate electrode will be described below with reference to FIGS. Here, a manufacturing method of the MESFET will be described as an example.

First, as shown in FIG. 1A, after an n layer 2 is formed on the surface of a semi-insulating GaAs substrate 1, an ECR-CVD method (electron cyclotron resonance chemical vapor phase) is formed on the n layer 2. The SiN film 3 having a film thickness of 55 nm is formed by the growth method). After that, a PMMA resist 4 having a thickness of 2 μm is formed on the SiN film 3. The width W1 of the resist 4 is 0.7 μm
It is. Highly conductive regions (n ⁺ regions) 5a and 5b are formed on the surface of the GaAs substrate 1 by Si ion implantation using the resist 4 as a mask.

Next, as shown in FIG. 1B, the resist 4 is etched by O ₂ plasma etching to set the width W2 of the resist 4 to 0.2 μm. Then, FIG.
As shown in (c), a 300 nm-thick SiO ₂ film is formed on the entire surface of the SiN film 3 and the resist 4 by the ECR-CVD method.
The film 6 is formed. After that, the SiO ₂ film 6 on the side wall of the resist 4 is selectively etched by using BHF (buffer hydrofluoric acid).

Next, as shown in FIG. 2D, the resist 4 is removed together with the SiO ₂ film 6 thereon using an organic solvent. Then, in order to activate the high conductivity regions 5a and 5b, heat treatment is performed by the RTA (short time annealing) method. Then, the central SiN film 3 on the n layer 2 is removed by the RIE method (reactive ion etching method).

Further, as shown in FIG. 2 (e), SiO
_A film thickness of 150 is formed on the ₂ film 6 and the n layer 2 by the sputtering method.
nm WSiN, thickness 350 nm Au and thickness 80
A heat resistant gate electrode layer 7 made of WSiN of nm is formed. Next, as shown in FIG. 2F, a gate etching mask 8 made of Ti and having a film thickness of 180 nm is formed on the gate electrode layer 7 above the n layer 2 by the vapor deposition method and the lift-off method. The length W3 of the gate etching mask 8 is 1 μm.

After that, as shown in FIG.
Etching the gate electrode layer 7 on both sides of the etching mask 8
Forming a T-type gate electrode 7a. Next
Then, as shown in FIG.
Etching mask 8, SiO ₂The film 6 and the SiN film 3
After removal, the T-type gate electrode 7a, the n-layer 2 and the high conductivity
A film thickness of 4 is formed on the entire surfaces of the regions 5a and 5b by the plasma CVD method.
A heat treatment protection film 9 made of a 5 nm SiN film is formed.
Then, the spatter generated during the formation of the T-type gate electrode 7a.
Heat treatment is carried out to recover damage from damage such as That
After that, as shown in FIG. 3 (i), a T-type game was performed by the RIE method.
Of heat treatment on the gate electrode 7a and the high conductivity regions 5a and 5b
The protective film 9 is removed.

Then, as shown in FIG. 4 (j), a 70 nm-thick film of AuGe, a 7-nm-thick film of Ni, and a 130-nm-thick film of Au are formed on the T-type gate electrode 7a and the high-conductivity regions 5a and 5b by vapor deposition. The electrode layer 10 made of is formed. Further, the electrode layer 10 on the high-conductivity regions 5a and 5b is made into an ohmic electrode by heat treatment.

[0010]

FIG. 10 is a schematic enlarged view of a T-type gate electrode of a conventional semiconductor device. In this semiconductor device, a channel is formed between the highly conductive regions 5a and 5b.

In FIG. 10, the interval L between the high conductivity regions 5a and 5b is determined by the width W1 of the resist 4 in the step of FIG. 1A, and is 0.7 μm in the above example.
The width (gate length) Lg of the foot portion of the T-shaped gate electrode 7a in the channel direction is determined by the width W2 of the resist 4 in the step of FIG. 1B, and is 0.2 μm in the above example.
Becomes The length Wgp of the umbrella portion of the T-shaped gate electrode 7a in the channel direction is determined by the length W3 of the gate etching mask 8 in the step of FIG. 2F, and is 1 μm in the above example. The height h of the foot portion of the T-shaped gate electrode 7a is determined by the film thickness of the SiO ₂ film 6 in the step of FIG. 1C, and is 300 nm in the above example.

In the conventional semiconductor device described above, FIG.
In the step (i), when removing the heat treatment protective film 9 on the high-conductivity regions 5a and 5b by the RIE method, the heat treatment protective film 9 near the n layer 2 is etched, and the heat treatment protective film 9 on the n layer 2 is etched. Is easily over-etched. Thereby,
As shown in FIG. 10, etching damage is given to the portion 30 of the n layer 2 near the high-conductivity regions 5a and 5b, which causes a problem that the characteristics of the semiconductor device deteriorate and the yield decreases.

An object of the present invention is to provide a semiconductor device in which characteristic deterioration due to damage of a channel region at the time of removing a protective film on a highly conductive region is prevented, and a manufacturing method thereof.

[0014]

A semiconductor device according to the present invention is a semiconductor device in which a T-type gate electrode is formed on a channel region of a semiconductor layer and high conductivity regions are formed on both sides of the channel region. In at least one highly conductive region side, the length from the end of the umbrella portion of the T-type gate electrode to the end of the one highly conductive region side channel region is 0.3.
It is set to be not less than μm and not more than 1.0 μm.

In the method for manufacturing a semiconductor device according to the present invention, a T-type gate electrode and a high-conductivity region are formed on a channel region of a semiconductor layer and on both sides of the channel region, respectively. After forming a protective film on the entire surface of the semiconductor layer, heat treatment is performed to remove the protective film in the ohmic electrode formation region on both sides of the T-type gate electrode, and a method for manufacturing a semiconductor device in which an ohmic electrode is formed in the ohmic electrode formation region The length from at least one end of the umbrella portion of the T-type gate electrode on the high-conductivity region side to the end of the channel region on the one high-conductivity region side is set to 0.3 μm or more and 1.0 μm or less. To do.

In the semiconductor device and the method of manufacturing the same according to the present invention, the length from the end of the umbrella portion of the T-type gate electrode on the side of at least one high conductivity region to the end of the channel region on the side of one high conductivity region. Is set to 0.3 μm or more, the channel region between the high conductivity regions is sufficiently protected by the umbrella portion of the T-type gate electrode. This prevents the channel region between the high-conductivity regions from being damaged by etching or the like when removing the protective film in the region where the ohmic electrode is formed. As a result, increase in source resistance due to damage to the channel region is suppressed, and deterioration of characteristics such as mutual conductance and cutoff frequency is prevented.

In addition, at least one high conductivity region side T
Since the length from the end of the cap portion of the gate electrode to the end of the channel region on the side of one of the high conductivity regions is set to 1.0 μm or less, the parasitic capacitance and the source resistance due to the increase in the size of the cap portion Is suppressed. As a result, characteristics such as mutual conductance and cutoff frequency are kept high. Therefore, the characteristics and yield of the semiconductor device having the T-type gate electrode are improved.

In particular, T on at least one high conductivity region side
The length from the end of the umbrella portion of the gate electrode to the end of the channel region on the side of one of the high conductivity regions is 0.5 μm or more and 1.0 μ
It is preferably set to m or less. In this case, damage to the channel region is sufficiently prevented, and the source resistance is stable in a low state. Therefore, the characteristics of the semiconductor device are further improved.

[0019]

First, a method of manufacturing a semiconductor device according to a first embodiment of the present invention will be described. In the first embodiment, G is used as an example of a semiconductor device having a T-type gate electrode.
The aAs-MESFET will be described. The basic manufacturing process of the semiconductor device of this embodiment is the same as that of the conventional semiconductor device, and only the conditions such as materials and dimensions are different. Therefore, refer to the process cross-sectional views of FIGS. While explaining.

First, as shown in FIG. 1A, after an n layer 2 is formed on the surface of a semi-insulating GaAs substrate 1, a 55 nm thick SiN film 3 is formed on the n layer 2 by ECR-CVD. To form. The SiN film 3 has a two-layer structure of a lower layer and an upper layer, the lower layer has a film thickness of 5 nm, and the upper layer has a film thickness of 50 nm.
nm. When forming the lower layer, Si is used as a reaction gas.
H ₄ and N ₂ are used and the gas flow rate is 18.5 s
ccm and 25 sccm. Further, the high frequency power is 300 W and the microwave current is 16.0 A. When forming the upper layer, SiH ₄ and N ₂ were similarly used as reaction gases, and the gas flow rates were 9 sccm and 2 respectively.
It is set to 5 sccm. The high frequency power is 300 W and the microwave current is 16.0 A.

After that, PM having a thickness of 2 μm is formed on the SiN film 3.
The MA resist 4 is formed. The width W1 of the resist 4 is 0.
7 μm. Then, using the resist 4 as a mask, Si
Highly conductive regions (n ⁺ regions) 5a and 5b are formed on the surface of the GaAs substrate 1 by ion implantation of. As the implantation conditions, the acceleration energy is 90 keV and the dose amount is 5 ×.
It is set to 10 ¹³ cm ^-2 .

Next, as shown in FIG. 1B, the resist 4 is etched by O ₂ plasma etching, and the width W2 of the resist 4 is set to 0.2 μm. In this case, O
The gas flow rate of ₂ is 50 sccm, and the gas pressure is 0.1 To
rr and high frequency power is 400W.

Then, as shown in FIG.
A 300 nm thick SiO ₂ film 6 is formed on the entire surface of the SiN film 3 and the resist 4 by the CVD method. in this case,
SiH ₄ and O ₂ are used as reaction gases, and the gas flow rates are 30 sccm and 30 sccm, respectively. The high frequency power is 500 W and the microwave current is 17.0 A. After that, the SiO ₂ film 6 on the side wall of the resist 4 is selectively etched by using BHF (buffer hydrofluoric acid).
A 100: 1 mixture of NH ₄ F and HF is used as BHF, and etching is performed at 20 ° C. for 1 minute.

Next, as shown in FIG. 2D, the resist 4 is removed together with the SiO ₂ film 6 thereon using an organic solvent. Then, in order to activate the highly conductive regions 5a and 5b, heat treatment is performed at 880 ° C. for 5 seconds by the RTA method. Then, the central SiN film 3 on the n layer 2 is removed by the RIE method. CF ₄ and O ₂ are used as the reaction gas.

Further, as shown in FIG. 2 (e), SiO
_A film thickness of 150 is formed on the ₂ film 6 and the n layer 2 by the sputtering method.
nm WSiN, thickness 350 nm Au and thickness 80
A heat resistant gate electrode layer 7 made of WSiN of nm is formed. As the material of the gate electrode layer 7, W, WN,
Any of WSiN and WSi, a laminated structure of any of these, or a laminated structure of any of these and Au may be used.

Next, as shown in FIG. 2F, a gate etching mask 8 made of Ti and having a thickness of 180 nm is formed on the gate electrode layer 7 above the n layer 2 by the vapor deposition method and the lift-off method. To do. Particularly, in this embodiment, the length W3 of the gate etching mask 8 is set to 2 μm. In addition,
A SiO ₂ film may be used as the material of the gate etching mask 8.

After that, as shown in FIG. 3G, the gate electrode layer 7 on both sides of the gate etching mask 8 is etched to form a T-type gate electrode 7a.
In this case, WSiN is etched by the RIE method.
CF ₄ and O ₂ are used as reaction gases, and the gas flow rates are set to 17 sccm and 3 sccn, respectively. The gas pressure is 0.1 Torr and the high frequency power is 150 W. Further, Au is removed by ion milling using Ar. Ar gas flow rate is 10 sccm, gas pressure is 2 m
Torr.

Next, as shown in FIG. 3 (h), NH ₄ F
And a HF mixture of 6: 1 using BHF, the gate etching mask 8, the SiO ₂ film 6 and the SiN.
After removing the film 3, a heat treatment protection film 9 is formed on the entire surfaces of the T-type gate electrode 7a, the n layer 2 and the high conductivity regions 5a and 5b by the plasma CVD method.

In particular, in this embodiment, a SiO ₂ film having a film thickness of 50 nm and a SiN film having a film thickness of 50 nm are used as the heat treatment protective film.
A SiO ₂ / SiN film made of a film is used. When forming the SiO ₂ film, SiH ₄ and N ₂ O were used as reaction gases, and the gas flow rates were 10 sccm and 100 s, respectively.
ccm The gas pressure is 0.30 Torr and the high frequency power is 150 W. When forming the SiN film, SiH ₄ , NH ₃ and N ₂ were used as reaction gases, and the gas flow rates were 15 sccm, 200 sccm and 10 sccm, respectively.
It is set to 0 sccm. The gas pressure is 0.75 Torr and the high frequency power is 250 W. Then, the T-shaped gate electrode 7
In order to recover damage caused by sputtering etc. when forming a,
Heat treatment is performed.

Then, as shown in FIG. 3 (i), RIE is performed.
On the T-type gate electrode 7a and the highly conductive region 5a,
The heat treatment protection film 9 on 5b is removed. In this case, CF ₄ is used as the reaction gas, and the gas flow rate is 20 sccm. Gas pressure is 0.1 Torr and high frequency power is 150
W.

Then, as shown in FIG. 4 (j), a 70 nm-thick film of AuGe, a 7-nm-thick film of Ni, and a 130-nm-thick film of Au are formed on the T-type gate electrode 7a and the high-conductivity regions 5a and 5b by vapor deposition. The electrode layer 10 made of is formed. Then, in H ₂ atmosphere, 450 ° C. for 2 minutes 30
By performing heat treatment for 2 seconds, the electrode layer 10 on the high-conductivity regions 5a and 5b becomes an ohmic electrode. For example, the ohmic electrode on the highly conductive region 5a becomes the source electrode, and the ohmic electrode on the highly conductive region 5b becomes the drain electrode.

FIG. 5 is a schematic enlarged view of the T-type gate electrode in the semiconductor device of this embodiment. In FIG. 5, the interval L between the high-conductivity regions 5a and 5b (channel region) is determined by the width W1 of the resist 4 in the step of FIG. 1A, and is 0.7 μm in the above example. Width (gate length) Lg of the foot of the T-shaped gate electrode 7a in the channel direction
Is determined by the width W2 of the resist 4 in the step of FIG. 1B, and is 0.2 μm in the above example. Also, T
The height h of the foot of the mold gate electrode 7a is determined by the film thickness of the SiO ₂ film 6 in the step of FIG. 1C, and is 300 nm in the above example.

Further, the distance L1 between the high-conductivity region 5a on the source electrode side and the foot of the T-type gate electrode 7a, and between the high-conductivity region 5b on the drain electrode side and the foot of the T-type gate electrode 7a. The interval L2 is, for example, 0.25 μm in each case
Is set to The case where the T-type gate electrode 7a is located in the center of the channel region will be described below.

Particularly, the length Wgp of the umbrella portion of the T-type gate electrode 7a in the channel direction is determined by the length W3 of the gate etching mask 8 in the step of FIG. 2F, and is 2.0 μm in the above example. Becomes The length Wgp of the umbrella portion of the T-shaped gate electrode 7a is set to satisfy the following equation.

0.6 [μm] ≦ Wgp-L ≦ 2.0 [μm] It is more preferable to set the value of Wgp-L to 1.0 μm or more for the reason described below.

In the above example, the length Wgp of the umbrella portion of the T-type gate electrode 7a in the channel direction and the high conductivity region 5a,
By setting the difference (Wgp-L) from the distance L between the 5b and 1.3 μm, the high conductivity region 5 can be formed in the step of FIG.
When removing the heat treatment protection film on a and 5b, the channel region between the high conductivity regions 5a and 5b is sufficiently protected by the umbrella portion of the T-type gate electrode 7a. Thereby, the high conductivity region 5a,
Damage to the channel region between 5b due to etching or the like is prevented, characteristic deterioration of the semiconductor device is prevented, and the yield is improved.

FIG. 6 is a schematic sectional view showing the structure of a semiconductor device according to the second embodiment of the present invention. The semiconductor device shown in FIG. 6 is a field-effect semiconductor device having both low noise operation characteristics and high output operation characteristics, and has a TMT (Two-Mode Chann).
el FET).

In FIG. 6, a semi-insulating GaAs substrate 2 is used.
1, an undoped GaAs buffer layer 22 having a film thickness of 800 nm and an undoped In _0.2 Ga _0.8 film having a film thickness of 5 nm.
An As channel layer 23 and an undoped In _x Ga _1-x As channel layer 24 having a film thickness of 7 nm are sequentially formed. The In composition ratio x of the In _x Ga _1-x As channel layer 24 gradually decreases from 0.2 to 0 from the interface with the In _0.2 Ga _0.8 As channel layer 23 toward the upper side.

On the In _x Ga _1-x As channel layer 24, an undoped GaAs spacer layer 2 having a film thickness of 5 nm is formed.
5, an n-GaAs channel layer 26 having a film thickness of 9 nm, and an undoped GaAs protective layer 27 having a film thickness of 22.5 nm are sequentially formed. The carrier concentration of the n-GaAs channel layer 26 is 7 × 10 ¹⁸ cm ⁻³ .

A T-type gate electrode 7a which is in Schottky contact with the undoped GaAs protective layer 27 is formed in the central portion on the undoped GaAs protective layer 27 by the same method as in the first embodiment. A source electrode 29 and a drain electrode 30 which are in ohmic contact with the protective layer 27 are formed respectively. Source electrode 29 and drain electrode 30
In the lower portion of the
a and 28b are formed.

In the semiconductor device of FIG. 6, when the gate potential is deep, the depletion layer extends downward, and the electrons supplied from the n-GaAs channel layer 26 are mainly In _0.2 Ga.
_{The 0.8} As channel layer 23 and the In _x Ga _1-x As channel layer 24 travel. In this case, the electrons are In _0.2 G
a _0.8 As channel layer 23 and In _x Ga _1-x As channel layer 24 are well confined in the quantum wells, so that they are less affected by impurities in the heavily doped n-GaAs channel layer 26. , Ultra low noise characteristics can be obtained. On the other hand, when the gate potential is shallow, the depletion layer shrinks, and electrons are mainly n-GaAs channel layer 26.
To travel. Therefore, highly doped n-
The GaAs channel layer 26 functions as a channel, a high and flat transconductance is obtained, and a high output characteristic is obtained.

Here, a plurality of semiconductor devices having the structure of FIG. 6 were manufactured by changing the length Wgp of the umbrella portion of the T-type gate electrode 7a from 0.8 μm to 3.6 μm, and various characteristics were measured. In these semiconductor devices, the high conductivity region 2
The interval L between 8a and 28b was 0.6 μm, and the width (gate length) Lg of the foot portion of the T-type gate electrode 7a was 0.2 μm. The distance L1 between the high conductivity region 28a and the foot of the T-type gate electrode 7a and the distance L2 between the high conductivity region 28b and the foot of the T-type gate electrode 7a are both 0.2 μm. The gate width Wg of the T-type gate electrode 7a is 100.
μm.

FIG. 7 shows the measurement result of the source resistance Rs and the calculation result of the parasitic capacitance Cgs. Further, FIG. 8 shows the measurement result of the mutual conductance gm. Further, FIG. 9 shows the measurement result of the cutoff frequency Ft. In FIGS. 7, 8 and 9, the horizontal axis represents the length Wgp of the umbrella portion of the T-shaped gate electrode 7a.
And the distance L between the high conductivity regions 28a and 28b (Wgp
-L) is represented.

As shown in FIG. 7, when the value of (Wgp-L) becomes smaller than 0.6 μm, the source resistance Rs rapidly increases. This is because when the length Wgp of the umbrella portion of the T-shaped gate electrode 7a is small, the heat treatment protective film 9 is formed in the step of FIG.
It is considered that this is because the damage due to overetching is given to the channel region between the high conductivity regions 28a and 28b when removing. In such a region where the source resistance Rs rises rapidly, it becomes difficult to control the value of the source resistance Rs in the process.

Further, there is the following relationship between the transconductance gm and the source resistance Rs. gm = gm ₀ / (1 + Rs · gm ₀ ) ... (1) In the above equation, gm ₀ represents true transconductance. From the above equation, it can be seen that when the source resistance Rs increases, the transconductance gm of the semiconductor device deteriorates.

Also in the measurement result of FIG. 8, (Wgp-
When the value of L) becomes smaller than 0.6 μm, the mutual conductance gm sharply decreases. Further, in the measurement result of FIG. 9, when the value of (Wgp-L) is smaller than 0.6 μm, the cutoff frequency Ft becomes lower than 90% of the maximum value. As a result, the value of (Wgp-L) is 0.6 μm.
It is preferable that it is above.

On the other hand, as shown in FIG. 7, (Wgp-L)
The parasitic capacitance Cgs increases as the value of increases.
Further, as shown in FIG. 7, the value of (Wgp-L) is 2.0.
When it becomes larger than μm, the source resistance Rs gradually increases. Thereby, from the formula (1), (Wgp-L)
When the value of is larger than 2.0 μm, the mutual conductance gm decreases. Further, the value of (Wgp-L) is 2.
The fact that the transconductance gm decreases when it becomes larger than 0 μm is supported by the measurement result of FIG.

Here, the cutoff frequency Ft is expressed by the following equation. Ft = gm / (2π · Cgs) (2) From the above equation, it is understood that the cutoff frequency Ft decreases due to the increase of the parasitic capacitance Cgs and the decrease of the mutual conductance gm. In addition, in the measurement results of FIG. 9, (Wgp-L)
When the value of becomes larger than 2.0 μm, the cutoff frequency Ft
Is lower than 90% of the maximum value. Therefore,
The value of (Wgp-L) is preferably 2.0 μm or less.

From these results, it is preferable that the value of (Wgp-L) satisfies the following equation. 0.6 [μm] ≦ Wgp−L ≦ 2.0 [μm] As a result, the mutual conductance gm is stably increased, and the deterioration of the cutoff frequency Ft is suppressed to 10% or less of the maximum value.

Particularly, when the value of (Wgp-L) is 1.0 μm or more, the source resistance Rs is stable at a low value. Therefore, it is more preferable that the value of (Wgp-L) satisfies the relationship of the following equation.

1.0 [μm] ≦ Wgp−L ≦ 2.0 [μm] This makes it possible to further improve various characteristics such as mutual conductance gm.

As can be seen from the above description, the length from the end of the umbrella portion of the T-type gate electrode on the side of one high conductivity region to the end of the channel region on the side of one high conductivity region is 0.3 μm or more. It may be set to 1.0 μm or less. As described above, it is most preferable to set both high-conductivity region sides as described above, but at least one high-conductivity region side to one high-conductivity region side from the end of the umbrella portion of the T-type gate electrode. It is also effective to set the length to the end of the channel region of 0.3 μm or more and 1.0 μm or less.

As can be seen from the above description, the length from the end of the umbrella portion of the T-type gate electrode on the side of one high conductivity region to the end of the channel region on the side of one high conductivity region is 0.5 μm.
It is preferable to set the thickness to m or more and 1.0 μm or less. Also,
In the above description, the case where the T-type gate electrode is located in the center of the channel region has been described, but the distance L1 on the source electrode side may be set smaller than the distance L2 on the drain electrode side, for example.

In the above embodiment, the T-type gate electrode 7
The height h of the foot portion of a is 300 nm, but since the thickness of the ohmic electrode is typically about 200 nm, the height h of the foot portion of the T-type gate electrode 7a is 200 nm or more and 500 nm or less. Is preferred.

The present invention is not limited to the above-mentioned embodiment, but may be In
It can be applied to various semiconductor devices having a T-type gate electrode, including P-based and other material-based semiconductor devices.
For example, the present invention may be applied to HEMT.

[Brief description of drawings]

FIG. 1 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention and a conventional semiconductor device.

FIG. 2 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention and a conventional semiconductor device.

FIG. 3 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention and a conventional semiconductor device.

FIG. 4 is a process sectional view showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention and a conventional semiconductor device.

FIG. 5 is a schematic enlarged view of a T-type gate electrode in the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view showing the structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 7 is a diagram showing a measurement result of a source resistance and a calculation result of a parasitic capacitance of the semiconductor device having the structure of FIG.

8 is a diagram showing a measurement result of mutual conductance of the semiconductor device having the structure of FIG.

9 is a diagram showing a measurement result of a cutoff frequency of the semiconductor device having the structure of FIG.

FIG. 10 is a schematic enlarged view of a T-type gate electrode in a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 GaAs substrate 2 n layers 5a, 5b High conductivity region 7a T-type gate electrode 9 Heat treatment protective film 21 GaAs substrate 22 GaAs buffer layer 23 In _0.2 Ga _0.8 As channel layer 24 In _x Ga _1-x As channel layer 25 GaAs spacer layer 26 n-GaAs channel layer 27 GaAs protective layer 28a, 28b High conductivity region 29 Source electrode 30 Drain electrode

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical indication location H01L 29/778 (72) Inventor Yatsuo Harada 2-5-5 Keihanhondori, Moriguchi-shi, Osaka Sanyo Electric Co., Ltd.

Claims (3)

[Claims] 1. A semiconductor device in which a T-type gate electrode is formed on a channel region of a semiconductor layer, and high-conductivity regions are formed on both sides of the channel region, wherein at least one of the T-type gate electrodes is on the high-conductivity region side. The semiconductor device is characterized in that the length from the end of the umbrella portion to the end of the channel region on the side of the one highly conductive region is set to 0.3 μm or more and 1.0 μm or less. 2. The length from the end of the umbrella portion of the T-type gate electrode on the side of the at least one high conductivity region to the end of the channel region on the side of the one high conductivity region is 0.5 μm or more. 2. The thickness is set to 0 μm or less.
13. The semiconductor device according to claim 1. 3. A T-type gate electrode and a high-conductivity region are formed on the channel region of the semiconductor layer and on both sides of the channel region, respectively, and the entire surface of the T-type gate electrode, the high-conductivity region and the semiconductor layer is formed. A method of manufacturing a semiconductor device, comprising: forming a protective film on a substrate, then performing heat treatment to remove the protective film in the ohmic electrode forming regions on both sides of the T-type gate electrode, and forming an ohmic electrode in the ohmic electrode forming region. And the length from at least one end of the umbrella portion of the T-type gate electrode on the high-conductivity region side to the end of the channel region on the one high-conductivity region side is set to 0.3 μm or more and 1.0 μm or less. A method of manufacturing a semiconductor device, comprising: