JPH0949858A - Current detection and control circuit and pattern layout method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To detect and control a current with high accuracy without being affected by irregularity or layout patterns from an aspect of production by controlling the value of the current flowing to a current passage subjected to mirroring and the value of the current flowing to load on the basis of the difference signal with a predetermined objective value. SOLUTION: A current regulating circuit is constituted of the operational amplifier (current detection signal output circuit) OP2 connected to a current passage L2 inputting an objective value to a positive terminal and subjected to mirroring at the negative terminal and the transistor (current control circuit) M0 connected across a high (low) potential power supply line and load and the value of the current flowing to the current passage L1 connected to the load is controlled by the output signal (the difference signal of the current value of a current passage L2 and the objective value) of the operational amplifier OP2. By this constitution, gate voltage sufficiently higher than threshold voltage can be supplied to the gate terminals of the transistors M1, M2 constituting a current mirror circuit 2 and, therefore, the effect of the irregularity of the threshold voltage generated in a production process or the effect of voltage drop between gate sources by layout patterns can be reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of a current detection control circuit and a pattern layout method for a plurality of transistors.

[0002]

2. Description of the Related Art Conventionally, circuits for detecting a current value flowing in a load are roughly classified into (1) a circuit for detecting an overcurrent and (2) a circuit for controlling a load current. Can be divided. In the case of a circuit for detecting overcurrent, it generally depends on the required system specifications, but in general, when a current that greatly exceeds the current value that should normally flow flows, the device itself and peripheral devices are This is to prevent destruction, and since it is sufficient to determine whether or not the current value exceeds a predetermined allowable current value, there is often no problem even with relatively low accuracy. On the other hand, in the case of a circuit for controlling the load current, although the current region varies depending on the control target, it is generally required to detect and control the current value with high accuracy from a minute current region to a large current region. Is.

FIG. 7 is a circuit diagram showing an example of a conventional current detection control circuit, which is an intelligent type power MOS IC (Metal Oxide Semiconductor In).
FIG. 4 is a circuit diagram of a main part of a semiconductor integrated device that detects a load current applied to an integrated circuit) in a lossless state. In addition,
FIG. 7A shows an example in which a load is arranged on the high-potential power supply line side, and FIG. 7B shows an example in which a load is arranged on the low-potential power supply line side. Their configurations and actions are almost the same.

In FIG. 7, the current detection control circuit 1 comprises a current mirror circuit 2, a feedback circuit 3, and a sense resistor Rs. The current mirror circuit 2 is
Two N-channel MOS with gate terminals commonly connected
・ FET (Field Effect Transistor, hereinafter simply referred to as transistor) M1 and M2, and transistor M
The load current Iload flowing in 1 is mirrored to the current path side of the transistor M2 based on the size ratio (n: 1) of the transistor M1 and the transistor M2.
Further, in this case, the driver causes the transistors M1 and M2 to
The control voltage applied to the gate terminal of the
And a voltage difference between the connection point voltage of the transistor M3 and the target value, which is a voltage near the threshold voltage Vth of the transistors M1 and M2.

The feedback circuit 3 includes a transistor M
Operational amplifier OP1 for connecting the drain terminals of 1 and M2 to the input terminals (normal input terminal and inverting input terminal), respectively
And a transistor M3 connected in series between the sense resistor Rs and the transistor M2, the output terminal of which is connected to the gate terminal of the operational amplifier OP1.
1 based on the output signal of the transistor M3 (see FIG. 7A).
The N-channel MOS.FET and the P-channel MOS.FET in FIG. 7B are controlled to make the drain-source voltage VDS of the transistors M1 and M2 constant.

The operation of the above structure will be described. The formula showing the operation of the MOS-FET is as follows: channel width W, channel length L, drain-source current IDS, drain-source voltage VDS, gate-source voltage VGS, threshold voltage Vth, structure factor Β (= μe ε / d, μ
e is the mobility, ε is the dielectric constant of the insulator, d is the thickness of the insulator)
Then, in the saturation region, IDS = (β / 2) (W / L)
(VGS-Vth) ² , while in the linear region, IDS
= Β (W / L) { (VGS-Vth) VDS- (VDS 2 /
2)}.

Generally, the current mirror circuit is used in the saturation region (the gate voltage applied to the transistors M1 and M2 is much higher than the threshold voltage) in order to suppress the influence of the drain-source voltage VDS of the transistor. In the above example, the transistors are operated in the linear region (the gate voltage applied to the transistors M1 and M2 is a voltage region near the threshold voltage) in order to design the ON resistances of the transistors M1 and M2 to be small. Therefore, the feedback circuit 3 causes the drains of the transistors M1 and M2 to
By always equalizing the source-to-source voltage VDS, the gate voltage for current control is applied to each gate terminal of the transistors M1 and M2 while suppressing the influence of the drain-source voltage VDS when operating the transistor in the linear region. By doing so, highly accurate current control can be performed.

[0008]

However, in such a conventional current detection control circuit, there is a problem that the current detection accuracy varies due to the factors described later. That is, the detection accuracy in the conventional technology is
It depends on the magnitude of the flowing current, but in the worst case ± 10
There was a detection variation of about 15%. The cause of this detection variation is various parameters (for example, threshold voltage Vth) of the semiconductor element itself such as a transistor.
Etc.), the influence of the layout pattern inside the IC chip, the influence of the circuit method, and the like.

FIG. 8 is a diagram showing a pattern layout of a general power MOS • FET, and FIG. 9 is an equivalent circuit diagram of the power MOS • FET in FIG. Normal,
Since a large current flows through the power MOS • FET, its layout pattern requires a large area as shown in FIG. Then, as shown in FIG. 9, a plurality of transistor cells MC are arranged between the signal lines wired from the pads (drain and source) which are the input / output terminals and are connected in parallel. In this case, the transistor cells MC to be arranged are inevitably arranged at positions close to the pads and those arranged at positions far from the pads.

Then, in the transistor cell MC arranged far from the pad, a voltage drop occurs due to the wiring resistance Rw × m based on the wiring length, so that the source potential increases and the drain potential decreases. It can happen. In this case, when the gate-source voltage VGS falls below the threshold voltage Vth, some transistor cells are turned off, and correct current mirroring based on the cell ratio of the transistors set at the time of design is not performed. become.

Furthermore, since the threshold voltage Vth of the transistor has a certain variation range due to variations in manufacturing due to variations in the same plane or between products, the gate voltage is close to the threshold voltage Vth.
When the source-to-source voltage VGS is controlled, the accuracy of the current mirror circuit 2 is lowered due to the influence of the variation in the threshold voltage Vth. In order to control the current with high accuracy, it is natural that high control accuracy is required by the current control circuit, but if the detection accuracy of the current value flowing in the controlled object is low, the current control circuit will have high performance. However, high-precision current control cannot be expected.

An object of the present invention is to solve the above problems and to provide a current detection control circuit and a pattern layout method capable of highly accurate current detection and current control without being affected by manufacturing variations and layout patterns. To provide.

[0013]

According to a first aspect of the present invention, there is provided a current detection control circuit in which a switch provided at each end of a load is closed to allow a current to flow through the load and to detect a current value flowing through the load. And a current detection control circuit for controlling the amount of current, the mirror circuit including a switch provided on one end side of the load and mirroring the current flowing through the load to another current path at a preset ratio. When,
A voltage control circuit for controlling the voltage applied to the current path to which the load is connected and the other current path to be constant, and a current flowing in the other current path mirrored by the mirror circuit is detected and detected. A current detection signal output circuit that outputs a difference signal between the determined current value and a predetermined target value, and a current control circuit that controls the amount of current flowing through the load based on the output signal from the current detection signal output circuit. It is configured to be equipped.

The current detection circuit according to claim 2 is
A current detection control circuit that controls the amount of current by detecting the value of the current flowing through the load while closing the switches provided at both ends of the load to allow the current to flow through the load. A switch provided on the side, a mirror circuit for mirroring the current flowing in the first current path including the load at a preset ratio to the second current path, the first current path and the second current path. Voltage control circuit for controlling the voltage applied to the constant voltage and a current flowing in the other current path mirrored by the mirror circuit, and outputs a difference signal between the detected current value and a predetermined target value. A current detection signal output circuit, a current control circuit that controls the amount of current flowing through the load based on an output signal from the current detection signal output circuit, and a current flowing through the second current path are preset. A multi-stage mirror circuit that mirrors each of a plurality of current paths corresponding to the ratio, and a selection circuit that selects an arbitrary current path from the plurality of current paths mirrored by the multi-stage mirror circuit. It is configured to be equipped.

According to another aspect of the current detection circuit of the present invention, the transistor provided on the high potential power supply line side of the load and the transistor provided on the low potential power supply line side of the load are made conductive. A current detection control circuit for controlling a current amount by detecting a value of a current flowing through the load, the current detecting control circuit being connected to a first current path common to the load at one end side of the load And a transistor pair formed by commonly connecting gates (or bases) of the transistor and a transistor that is paired with the transistor and connected to the second current path. A mirror circuit that mirrors the current flowing in the current path to the second current path, and compares the voltages applied to the first current path and the second current path,
A voltage control circuit for controlling to eliminate the differential voltage between these current paths, and a current flowing in the second current path mirrored by the mirror circuit is detected, and a difference signal between the detected current value and a predetermined target value. From the current detection signal output circuit to the gate (or the base) of the transistor, which includes a current detection signal output circuit for outputting And a current control circuit for controlling the amount of current flowing through the first current path.

According to a fourth aspect of the present invention, there is provided a pattern layout method of a plurality of transistors in a semiconductor integrated device, wherein a plurality of transistors are arranged between two power supply lines and connection points of the respective transistors are connected. Connect each transistor in parallel so that the wiring resistance between them is equal, and connect one end of one power supply line to the pad and the other end to the terminal of the final stage transistor, One end of the other power supply line corresponding to one end is connected to the terminal of the first-stage transistor, and the other end is connected to the pad.

The pattern layout method according to claim 5 is a pattern layout method for a plurality of transistors in a semiconductor integrated device, wherein a plurality of transistors are arranged between two pads and each transistor is connected from each pad. A plurality of sets of power supply lines having the same wiring resistance are wired to the terminals of, and the plurality of transistors are connected in parallel to the pad.

The current detection control circuit according to claim 6 uses a transistor realized by the pattern layout method according to claim 4 or 5 for the current detection control circuit according to claim 3. Is configured.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing an example of a current detection control circuit of the present invention. Like the conventional example shown in FIG. 7, a load current applied to an intelligent type power MOS IC is detected without loss. FIG. 3 is a circuit diagram of a main part of a semiconductor integrated device. Note that FIG.
An example in which a load is arranged on the high potential power line side corresponding to (a),
FIG. 1B shows an example in which a load is arranged on the low potential power line side corresponding to FIG. 7B, and in FIG. 1, the same elements as those of the conventional example shown in FIG. Attached.

In FIG. 1, the current detection control circuit 1 of the present invention is roughly divided into the functions of a current mirror circuit 2 which is a mirror circuit, a feedback circuit 3 which is a voltage control circuit, a current detection signal output circuit and a current control circuit. The current adjusting circuit 4 and the sense resistor Rs are included, and each of the transistors M0 to M3 acts as an electronic switch. The current mirror circuit 2 includes two transistors M1 and M2 whose gate terminals are commonly connected to each other. The current mirror circuit 2 transfers the load current Iload flowing through the first current path L1 to the transistor M1.
I based on the n: 1 size ratio between the transistor and the transistor M2.
The load / n is mirrored to the second current path L2 side. In this case, n is arbitrary, for example, n = 5
Values such as 00, n = 1000 are used.

The feedback circuit 3 is an operational amplifier OP.
1. It comprises a transistor M3 and controls the transistor M3 based on the output signal of the operational amplifier OP1 to make the drain-source voltage VDS of the transistors M1 and M2 constant. The current adjustment circuit 4 inputs a target value serving as a reference to the non-inverting input terminal, and connects the inverting input terminal to the connection point of the transistor M2 and the transistor M3 in the second current path L2.
(Current detection signal output circuit), the output terminal from the operational amplifier OP2 is connected to the gate terminal, and the transistor M0 (current control circuit) is connected in series between the high potential power supply line (or low potential power supply line) and the load. ) And controlling the transistor M0 in the linear region based on the output signal of the operational amplifier OP2, the amount of current flowing through the first current path L1 is controlled.

Next, the operation of the above embodiment will be described. As a method of controlling the load current based on the detected current, as shown in the conventional example (see FIG. 7), the gate voltage of the power MOS • FET which is the current driver is changed so that it flows between the drain and the source. A general method is to control the current IDS. In the conventional example, the amount of current is controlled by changing the gate voltage of the transistors M1 and M2 that are detecting the current, but the gate-source voltage VGS of the transistors M1 and M2 at this time is the current control. In operation, the threshold voltage V of the transistor in the linear region
It is operated near th.

The inventors have considered that the accuracy of the current mirror circuit 2 is affected by the fact that the gate voltage applied to the transistors M1 and M2 forming the current mirror is near the threshold voltage Vth. The threshold voltage Vth is applied to the gate terminals of the transistors M1 and M2 that form the
By supplying a gate voltage that is sufficiently higher than that, it is less likely to be affected by variations in the threshold voltage Vth caused by the manufacturing process, and the source potential rises and the drain potential lowers depending on the layout pattern. The influence of the decrease in voltage VGS is reduced.

Specifically, the conventional current mirror circuit 2
By performing the function of the current control performed in the inside by driving the independent transistor M0, only the on / off operation is controlled on the current detection side, and when it is in the on state, it is sufficient for the threshold voltage Vth. The current detection is performed by applying a high gate voltage (for example, when the threshold voltage Vth of the transistor is set to about 1.5V, the gate-source voltage VGS of the power MOS • FET on the current detection side is set to about 15V). I am trying to do it. In this case,
As shown in (a) and (b), the same effect can be obtained regardless of which of the current detection side transistor M1 and the current control side transistor M0 is the high potential power supply line side and which is the low potential power supply line side. .

As described above, in the present embodiment, the amount of current flowing through the load can be detected with high accuracy without being affected by the variation in the threshold voltage Vth that occurs during transistor manufacturing.

FIG. 2 is a circuit diagram showing another example of the current detection control circuit of the present invention. 2A shows an example in which a load is arranged on the high-potential power line side, and FIG. 2B shows an example in which a load is arranged on the low-potential power line side. In FIG.
The same components as those in the embodiment shown in FIG. 1 are designated by the same reference numerals. In the current detection control circuit 1 in this embodiment,
The second current path L is different from that of the above-described embodiment (see FIG. 1).
A multi-stage current mirror circuit (multi-stage mirror circuit) that further mirrors the current flowing through 2 to a plurality of current paths L3, ...
5 and an arbitrary current path L3 among the plurality of current paths L3, ...
The selection circuit 6 for selecting ... Is additionally provided.

The multi-stage current mirror circuit 5 has a P channel M at the position where the sense resistor Rs in FIG. 1 was arranged.
It is composed of three transistors M4, M5, and M6 in which the OS transistor M4 is arranged and the gate terminals are commonly connected. That is, the transistor M is connected to the second current path L2.
4 is arranged, and the transistor M5 is arranged in the third current path L3. Then, the current Iload / n flowing through the second current path L2 is calculated as Iload / (n ×) based on the size ratio of m: 1 between the transistor M4 and the transistor M5.
As m), mirroring is performed on the third current path L3 side. The selection circuit 6 is composed of a transfer gate TG1 and an inverter I1, and performs on / off control of the transfer gate TG1 based on a gain control signal. In the above-described embodiment, the transistors M1 and M
With the size ratio of n: 1 set to 2, the second current path L
The amount of current flowing in 2 is set, but in actual use,
The feedback gain during current control may be changed and used. In such a case, in the above-described embodiment, the size ratio of the transistors M1 and M2 needs to be changed.

In this embodiment, when the transfer gate TG1 is controlled to be turned off by controlling the transfer gate TG1 to be turned on / off by the gate control signal, only the transistor M5 becomes effective. A current Iload / (n × m) flows through the third current path L3 based on the size ratio of M5,
On the other hand, when the transfer gate TG1 is controlled to be turned on, both the transistors M5 and M6 are enabled, so that the total cell size of the transistors M5 and M6 is three times the cell size of only the transistor M5. , M6 // M5: M4 = 1: (m / 3), the current is mirrored. That is, even if the current Iload flowing through the load is the same, when the transfer gate TG1 is on, it is compared with when it is off.
Since the current flowing through the sense resistor Rs is tripled, the voltage appearing at the end of the sense resistor Rs becomes large, and the operational amplifier OP2 comparing with the target value narrows its output voltage to Ilo.
It operates so that the voltage appearing at the end of the sense resistor Rs as ad / 3 and the target value become equal.

Therefore, in this example, the gain with respect to the load current can be reduced to 1/3 by the on / off operation of the transfer gate TG1. Therefore, in this embodiment, in addition to the operation similar to that of the above-described embodiment. The feedback gain during current control can be changed arbitrarily to some extent. In the above embodiment, the multi-stage current mirror circuit 5 mirrors the current flowing through the second current path L2 to the third current path L3. However, the number of mirroring steps is further increased and the selection circuit 6 is added. By doing so, a desired feedback gain may be selected from a plurality of feedback gains. In the above, the present invention can be applied to the case of controlling a three-phase spindle motor for a hard disk, a voice coil motor, or a forward / reverse rotation motor incorporated in an H bridge circuit. When the H-bridge circuit is used, two current detection and control systems are used, and when controlling a three-phase motor, the circuit of FIG. 1 is used for three phases.

FIG. 3 is a diagram showing an example of the layout pattern of the present invention, and FIG. 4 is an equivalent circuit diagram of FIG. FIG.
In the layout pattern shown in FIG. 4, a plurality of transistor cells MC are arranged between the two power supply lines LH and LL, and the wiring resistances Rw between the connection points of the transistor cells MC are equal to each other. The transistor cells MC are connected in parallel, and one end of the power supply line LH (see FIG.
The left end side in the middle is connected to a pad (drain pad), the other end (the right end side in FIG. 4) is connected to the drain terminal of the final stage transistor cell, and one end of the power supply line LL (FIG. 4) is connected.
The middle and left ends are connected to the source terminals of the first-stage transistor cells, and the other ends (right ends in FIG. 4) are connected to pads (source pads).

That is, in the conventional example shown in FIGS. 8 and 9, the source potential of the transistor cell MC arranged at a position far from the pad is reduced due to the wiring resistance Rw × m based on the wiring length thereof. Although the phenomenon such that the drain potential rises and the drain potential lowers occurs, in the present embodiment, by forming the gate pad on the opposite side, when viewed from the drain pad side, the transistor cell MC arranged at a position far from the pad is formed. Since the drain potential decreases as the drain potential decreases, the drain-source voltage VDS can be maintained at a constant value. As a result, the drain-source voltage VDS is improved only by the pattern layout of the transistor, and in particular, when the transistor is operated in the linear region as shown in FIGS. 1 and 2, the current detection accuracy is improved. .

FIG. 5 is a diagram showing another layout pattern example of the present invention, and FIG. 6 is an equivalent circuit diagram of FIG.
In the layout patterns shown in FIGS. 5 and 6, a plurality of transistor cells MC are arranged between two pads, and a plurality of sets of power supply lines having the same wiring resistance Rw are provided from each pad to the terminal of each transistor cell MC. Wiring is performed and the plurality of transistor cells MC are connected in parallel to the pad.

That is, in the above-described examples shown in FIGS. 3 and 4, the drain-source voltage VDS can be maintained at a constant value, but the transistor cell MC arranged at a position far from the pad has its wiring length. Wiring resistance R based on
It is unavoidable that a voltage drop occurs due to w × m. Therefore, in this example, under the condition that the wiring resistances Rw of the respective transistor cells MC are all set to the same value, all the transistor cells MC are connected in parallel to the respective pads, and the potential is lowered in principle. It is what you lose.

In an actual pattern layout, it is impossible to wire all the plurality of transistor cells MC. Therefore, as shown in FIG.
The divided area is divided into a plurality of areas (in this case, 4 areas), and the signal lines having different wiring widths are connected so that the wiring resistance Rw for each area is equal. As a result, it is possible to suppress a decrease in drain voltage and source voltage, that is, a decrease in gate-source voltage VGS due to the wiring resistance Rw. Even when the transistor is operated near the threshold voltage Vth, the gate-source voltage VGS is reduced. It is possible to suppress the generation of the transistor cell MC which is turned off by falling below the threshold voltage Vth. In particular, when applied to the current mirror circuit as shown in FIGS. 1 and 2, it is possible to perform a correct current mirror based on the cell ratio of the transistor set at the time of design, and it is possible to detect the current with higher accuracy than before. .

[0035]

According to the present invention, highly accurate current detection and current control can be performed without being affected by variations in manufacturing of semiconductor elements and layout patterns.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a current detection control circuit of the present invention.

FIG. 2 is a circuit diagram showing another example of a current detection control circuit of the present invention.

FIG. 3 is a diagram showing an example of a pattern layout of the present invention.

FIG. 4 is an equivalent circuit diagram of FIG. 3;

FIG. 5 is a diagram showing another example of the pattern layout of the present invention.

6 is an equivalent circuit diagram of FIG.

FIG. 7 is a circuit diagram showing an example of a conventional current detection control circuit.

FIG. 8 is a diagram showing an example of a conventional pattern layout.

9 is an equivalent circuit diagram of FIG.

[Explanation of symbols]

 1 current detection control circuit 2 current mirror circuit (current detection mirror circuit) 3 feedback circuit (voltage control circuit) 4 current adjustment circuit 5 multi-stage current mirror circuit (multi-stage mirror circuit) 6 selection circuit M1, M2 N-channel MOS / FET M3 MOS • FET M4 P-channel MOS • FET M5, M6 MOS • FET M0 N-channel MOS • FET (current control circuit) Rs Sense resistor OP1 operational amplifier OP2 operational amplifier (current detection signal output circuit) TG1 Transfer gate I1 inverter

Claims (6)

[Claims] 1. A current detection control circuit for controlling a current amount by detecting a value of a current flowing through the load while controlling a switch provided at both ends of the load to make a current flow through the load. A mirror circuit that includes a switch provided on one end side of the load, and mirrors a current flowing through the load to another current path at a preset ratio; a current path to which the load is connected and the other current path. A voltage control circuit for controlling the voltage applied to the path to a constant value, and a current flowing in the other current path mirrored by the mirror circuit is detected, and a difference signal between the detected current value and a predetermined target value. And a current control circuit that controls the amount of current flowing through the load based on an output signal from the current detection signal output circuit. Flow detection control circuit. 2. A current detection control circuit for controlling the amount of current by detecting the value of the current flowing through the load while closing the switches provided at both ends of the load to allow the current to flow through the load. A mirror circuit that includes a switch provided on one end side of the load, and that mirrors a current flowing through a first current path including the load to a second current path at a preset ratio; A voltage control circuit for controlling the voltage applied to the second current path to be constant, and a current flowing in the other current path mirrored by the mirror circuit is detected, and the detected current value and a predetermined target value A current detection signal output circuit that outputs a differential signal of, a current control circuit that controls the amount of current flowing to the load based on an output signal from the current detection signal output circuit, and a current flowing to the second current path. A multi-stage mirror circuit that mirrors a current at a plurality of preset ratios to a plurality of current paths corresponding to the ratio, and a selection that selects an arbitrary current path from the plurality of current paths mirrored by the multi-stage mirror circuit. A current detection control circuit comprising: a circuit. 3. A transistor provided on the high-potential power supply line side of the load and a transistor provided on the low-potential power supply line side of the load are electrically connected to each other to cause a current to flow through the load and A current detection control circuit for detecting a value of a current flowing through a load to control an amount of current, wherein a transistor connected to a first current path common to the load on one end side of the load and a pair of the transistor. Includes a transistor pair in which a gate (or a base) of the transistor and a transistor connected to the second current path are commonly connected, and the current flowing through the first current path is based on the size ratio of each transistor. Voltage control circuit for comparing the voltage applied to the first current path and the voltage applied to the second current path and controlling to eliminate the voltage difference between these current paths. A current detection signal output circuit that detects a current flowing in the second current path mirrored by the mirror circuit and outputs a difference signal between the detected current value and a predetermined target value; and the other end of the load. A current connected to a first current path common to the load, the output signal from the current detection signal output circuit is applied to the gate (or base) of the transistor, and the current flowing through the first current path A current control circuit for controlling the amount, and a current detection control circuit. 4. A pattern layout method of a plurality of transistors in a semiconductor integrated device, wherein a plurality of transistors are arranged between two power supply lines, and wiring resistances between connection points of the respective transistors are equal to each other. Each of the transistors is connected in parallel to one of the power supply lines, and one end of the power supply line is connected to the pad, and the other end is connected to the terminal of the final-stage transistor, and the other power supply line corresponding to one end of the one power supply line is connected. The pattern layout method is characterized in that one end of is connected to a terminal of a first-stage transistor and the other end is connected to a pad. 5. A method for pattern layout of a plurality of transistors in a semiconductor integrated device, wherein a plurality of transistors are arranged between two pads and wiring resistance is equal from each pad to each transistor terminal. A pattern layout method comprising wiring a set of power supply lines and connecting the plurality of transistors in parallel to the pad. 6. The current detection control circuit according to claim 3, wherein the transistor in the current detection control circuit is realized by the pattern layout method according to claim 4 or 5.