JPH0946228A - Integrated circuit device incorporating a/d converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To hold the precision of an A/D converter by means of operating it at high speed even if a central processing unit operates at low speed for reducing power consumption current. SOLUTION: When the central processing unit 2 operates by a low speed clock signal outputted from a low speed oscillation circuit 4, it outputs a low speed operation signal to a logic circuit 6. The A/D converter 1 is operated by a high speed clock signal outputted from a high speed oscillation circuit 5, and it outputs an A/D conversion operation signal to the logic circuit 6 during an operation. The logic circuit 6 outputs an oscillation stop signal to the high speed oscillation circuit 5 only when the low speed operation signal is outputted from the central processing unit 2 and the A/D conversion operation signal is not outputted from the A/D converter 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device such as a microcomputer containing an A / D converter.

[0002]

2. Description of the Related Art In recent years, the degree of integration of semiconductor devices has improved, and main functions and peripheral functions have been integrated into one integrated circuit. For example, an integrated circuit device in which an A / D converter is mounted on a microcomputer having a CPU has been realized.

FIG. 2 is a block diagram showing the configuration of a conventional integrated circuit device having an A / D converter. The integrated circuit device shown in FIG. 2 includes an A / D converter 1, a central processing unit (C
PU) 2, a selection circuit 3, a low-speed oscillation circuit 4, and a high-speed oscillation circuit 5. The A / D converter 1 performs A / D conversion of a given analog voltage into a digital signal, and has a sampling circuit 11 for sampling the analog voltage. Sampling circuit 11
Is "closed" during the sampling period, while A / D
It has a switch 12 that is “open” during the conversion period and a capacitor 13 that holds the analog voltage input during the sampling period.

The low speed oscillator circuit 4 outputs a low speed clock signal, while the high speed oscillator circuit 5 outputs a high speed clock signal. The selection circuit 3 selects either the low speed clock signal or the high speed clock signal and uses the CPU as the system clock.
Feed to 2. The CPU 2 operates by the system clock, but outputs an oscillation stop signal to the high-speed oscillation circuit 5 when operating by the low-speed clock signal in order to reduce current consumption. The high-speed oscillator circuit 5 stops the oscillation when the oscillation stop signal is input.

The A / D converter 1 also operates according to the system clock supplied to the CPU 2. A /
The analog voltage input to the D converter 1 is held by the capacitor 13 because the switch 12 is “closed” during the sampling period. Next, during the A / D conversion period, the switch 12 becomes “open” and the capacitor 13
A / D conversion is performed on the basis of the analog voltage held at.

[0006]

However, the conventional integrated circuit device with an A / D converter has the following problems.

In the conventional integrated circuit device with a built-in A / D converter, when the CPU 2 operates by the low-speed clock signal and the high-speed oscillation circuit 5 is stopped in order to reduce the current consumption, the A / D converter 1 also operates at the low-speed clock. It will be operated by signals.

However, the sampling circuit 11 of the A / D converter 1 has a parasitic resistance 1 which causes the voltage held by the capacitor 13 to escape across the capacitor 13.
There are four. The influence of the parasitic resistance 14 is not a problem during high speed operation, but the capacitor 13 is affected during low speed operation.
The analog voltage held at is lost by the parasitic resistance 14 during the A / D conversion period. That is, when the CPU 2 is operated at a low speed to reduce the current consumption, there is a problem that the accuracy of the A / D converter 1 deteriorates.

In view of the above problems, it is an object of the present invention to provide an A / D converter built-in integrated circuit device capable of maintaining the accuracy of the A / D converter even when the CPU is operating at a low speed.

[0010]

To achieve the above object, the present invention provides a high-speed oscillation circuit when the A / D converter operates even when the CPU operates at a low speed in order to reduce current consumption. Oscillates the high-speed clock signal to A /
By supplying the D / D converter, the A / D conversion accuracy is prevented from being lowered.

Specifically, the solving means taken by claim 1 is A
A first oscillating circuit for oscillating and outputting a first clock signal for an integrated circuit device with a built-in / D converter;
Second oscillation circuit that oscillates and outputs a second clock signal having a frequency higher than that of the second clock signal, a central processing unit that operates by the first clock signal or the second clock signal, and the second clock signal A / operated by
When the D converter and the central processing unit are operating by the second clock signal, the second oscillator circuit is activated, and when the central processing unit is operating by the first clock signal. And a control circuit that operates the second oscillation circuit when the A / D converter operates, and stops the second oscillation circuit when the A / D converter does not operate. It is a thing.

According to the configuration of the first aspect of the present invention, in order to reduce the current consumption, the second oscillator circuit operates when the A / D converter operates even when the central processing unit operates at a low speed by the first clock signal. Since it operates, the A / D converter has a second frequency higher than that of the first clock signal.
Can be operated by the clock signal. Therefore, since the A / D converter can always operate at high speed, the A / D conversion can be performed before the input analog voltage is lost by the parasitic resistance in the sampling circuit.

Specifically, a solution means taken by the invention of claim 2 is directed to an integrated circuit device with a built-in A / D converter, and a first oscillating circuit for oscillating and outputting a first clock signal, and the first oscillating circuit. A second oscillating circuit for oscillating and outputting a second clock signal having a frequency higher than that of the clock signal; a central processing unit which operates by the first clock signal or the second clock signal; and a first clock signal Also includes a third oscillation circuit that oscillates and outputs a high-frequency third clock signal, and an A / D converter that operates according to the third clock signal.

According to the second aspect of the present invention, the A / D converter has a frequency higher than that of the first clock signal even when the central processing unit operates at a low speed by the first clock signal in order to reduce current consumption. Can be operated by a high third clock signal. Therefore, since the A / D converter can always operate at high speed, the A / D conversion can be performed before the input analog voltage is lost by the parasitic resistance in the sampling circuit.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an integrated circuit device with an A / D converter according to an embodiment of the present invention. The integrated circuit device shown in FIG. 1 includes an A / D converter 1,
A central processing unit (CPU) 2, a selection circuit 3, a low-speed oscillation circuit 4 as a first oscillation circuit, a high-speed oscillation circuit 5 as a second oscillation circuit, and a logic circuit 6 as a control circuit. The A / D converter 1 performs A / D conversion of the input analog voltage into a digital signal, and has a sampling circuit 11 for sampling the analog voltage. The sampling circuit 11 includes a switch 12 that is “closed” during the sampling period and is “open” during the A / D conversion period, and a capacitor 13 that holds an analog voltage input during the sampling period. In addition, at both ends of the capacitor 13, the capacitor 13
There is a parasitic resistance 14 that escapes the voltage held by.

The low speed oscillator circuit 4 outputs a low speed clock signal, while the high speed oscillator circuit 5 outputs a high speed clock signal. The selection circuit 3 selects either the low speed clock signal or the high speed clock signal and uses the CPU as the system clock.
Feed to 2. The CPU 2 operates according to the system clock, but outputs a low speed operation signal to the logic circuit 6 when operating according to the low speed clock signal.

The A / D converter 1 also performs A / D conversion with a high-speed clock signal output from the high-speed oscillator circuit 5. This is because when operating with a low-speed clock signal, the accuracy of A / D conversion is reduced due to the influence of the parasitic resistance 14. The A / D converter 1 outputs an A / D conversion operation signal to the logic circuit 6 during A / D conversion.

The logic circuit 6 outputs an oscillation stop signal to the high-speed oscillation circuit 5 when the CPU 2 outputs a low speed operation signal and the A / D converter 1 does not output an A / D conversion operation signal. The high-speed oscillator circuit 5 stops oscillation when the oscillation stop signal is output from the logic circuit 6.

The operation of the integrated circuit device with a built-in A / D converter configured as shown in FIG. 1 will be described.

First, it is assumed that the CPU 2 operates at a low speed in order to reduce current consumption, and the A / D converter does not perform A / D conversion. At this time, the CPU 2 is operating by the low speed clock signal output from the low speed oscillation circuit 4. Since the CPU 2 outputs the low speed operation signal and the A / D converter 1 does not output the A / D conversion operation signal, the oscillation stop signal is output from the logic circuit 6 and the high speed oscillation circuit 5 stops the oscillation.

When the A / D converter 1 starts the A / D conversion, the A / D converter 1 outputs the A / D conversion operation signal, so that the logic circuit 6 does not output the oscillation stop signal and the high speed is achieved. The oscillation circuit 5 starts oscillating. The high-speed clock signal output from the high-speed oscillator circuit 5 is supplied to the A / D converter 1. Since the switch 12 is “closed” during the sampling period, the input analog voltage is held in the capacitor 13. Next, since the switch 12 is “open” in the A / D conversion period, the analog voltage held in the capacitor 13 is A / D converted. At this time, since the operation is performed by the high-speed clock signal, it is not affected by the parasitic resistance 14. A / D
When the conversion is completed, the A / D converter 1 does not output the A / D conversion operation signal, so that the logic circuit 6 outputs the oscillation stop signal and the high-speed oscillation circuit 5 stops the oscillation.

When the CPU 2 operates at high speed, the CPU 2 does not output a low speed operation signal, so that the logic circuit 6 does not output an oscillation stop signal and the high speed oscillation circuit 5 starts oscillation. The high-speed clock signal is selected as the system clock by the selection circuit 3, and the CPU 2 operates according to the high-speed clock signal.

As described above, according to this embodiment,
Since the high-speed clock signal can be supplied to the A / D converter even when the CPU is operating at a low speed in order to reduce the current consumption, the A / D converter does not lose the sampled analog voltage due to parasitic resistance. To A
The A / D conversion can be completed with high accuracy.

Although the high-speed clock signal used by the CPU is used as the operation clock of the A / D converter here, it is output from another high-speed oscillation circuit such as a CR oscillation circuit, an inverter chain circuit, or a multiplication circuit. Alternatively, a high speed clock signal may be used.

[0026]

According to the integrated circuit device with a built-in A / D converter according to the first aspect of the present invention, even if the central processing unit is operating at a low speed by the first clock signal in order to reduce current consumption, Since the D converter can operate at high speed by the second clock signal, the A / D conversion can be performed before the input analog voltage is lost by the parasitic resistance in the sampling circuit. It is possible to prevent a decrease in accuracy.

According to the integrated circuit device with a built-in A / D converter according to the invention of claim 2, the A / D converter is operated even when the central processing unit is operating at a low speed by the first clock signal in order to reduce current consumption. Since the third clock signal enables high-speed operation, the A / D conversion can be performed before the input analog voltage is lost by the parasitic resistance in the sampling circuit. You can prevent the decline.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an integrated circuit device with an A / D converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional integrated circuit device with a built-in A / D converter.

[Explanation of symbols]

 1 A / D Converter 2 Central Processing Unit (CPU) 3 Selection Circuit 4 Low Speed Oscillation Circuit (First Oscillation Circuit) 5 High Speed Oscillation Circuit (Second Oscillation Circuit) 6 Logic Circuit (Control Circuit) 11 Sampling Circuit 12 Switch 13 Capacitor 14 Parasitic resistance

Claims (2)

[Claims] 1. A first device for oscillating and outputting a first clock signal
Oscillator circuit, a second oscillator circuit that oscillates and outputs a second clock signal having a higher frequency than the first clock signal, and a central processing unit that operates by the first clock signal or the second clock signal. An A / D converter that operates according to the second clock signal; and a central processing unit that operates the second oscillation circuit when the central processing unit operates according to the second clock signal. Is operating according to the first clock signal, the second oscillator circuit is activated while the A / D converter is operating while the A / D is operating.
And a control circuit for stopping the second oscillation circuit when the converter does not operate.
Integrated circuit device with built-in D converter. 2. A first circuit for oscillating and outputting a first clock signal
Oscillator circuit, a second oscillator circuit that oscillates and outputs a second clock signal having a higher frequency than the first clock signal, and a central processing unit that operates by the first clock signal or the second clock signal. And a third oscillation circuit that oscillates and outputs a third clock signal having a frequency higher than that of the first clock signal, and an A / D converter that operates according to the third clock signal. An integrated circuit device with a built-in A / D converter.