JP2003076437A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device allowing reducing consumed current of an oscillation and amplification circuit. SOLUTION: This semiconductor device contains a frequency band detection circuit 4 for detecting a frequency band of internal working frequency of the semiconductor device and the oscillation and amplification circuit 5 for selecting optimum oscillating current capacity according to the frequency band detected by the frequency band detection circuit 4. The semiconductor device detects its internal working frequency band inside a system containing the semiconductor device and optimizes the oscillating current capacity of the oscillation and amplification circuit 5, and thereby excess current capacity when frequency of an internal working clock is low is restricted low and accordingly low consumption of current can be realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a built-in oscillation amplifier circuit and operating in a wide frequency band such as a general-purpose microcontroller.

[0002]

2. Description of the Related Art Conventionally, in a semiconductor device which operates in a wide frequency band, the oscillation current capability of an oscillation amplifier circuit incorporated in the semiconductor device is designed with a high numerical value so that stable oscillation can be performed even in a high frequency band. , Was able to operate in a wide frequency band.

[0003]

A semiconductor device which operates in a wide frequency band is designed with a high numerical value for the oscillation current capability of the oscillation amplifier circuit incorporated in the semiconductor device, and therefore, in the oscillation amplifier circuit in a low frequency band. There was a problem that the inverter's capacity was too strong and the current consumption was large.

Therefore, an object of the present invention is to provide a semiconductor device capable of reducing current consumption.

[0005]

SUMMARY OF THE INVENTION The present invention provides a frequency band detection circuit for detecting the frequency band of the internal operating frequency of a semiconductor device, and an optimum oscillation current capability according to the frequency band detected by the frequency band detection circuit. By incorporating an oscillation amplifier circuit that selects a. In the semiconductor device, the semiconductor device detects the frequency band of its internal operation clock in the system including the semiconductor device, and optimizes the oscillation current capability of the oscillation amplifier circuit. This makes it possible to realize low current consumption.

Specifically, in the semiconductor device according to the first aspect, an oscillation amplifier circuit capable of selecting an oscillation current capability and outputting an internal operation clock, and a frequency band detection for detecting a frequency band of the internal operation clock. Circuit, and the oscillation current capability of the oscillation amplification circuit is selected according to the detection result of the frequency band detection circuit.

A semiconductor device according to a second aspect is the semiconductor device according to the first aspect, wherein the frequency band detection circuit generates an output after a lapse of a fixed time from the count start signal as a starting point regardless of an internal operation clock. The generation circuit, the counter that starts counting the internal operation clock in response to the count start signal, and ends the counting of the internal operation clock in response to the output of the absolute time generation circuit, and the count value at the end of counting And a band discriminating means for discriminating the frequency band of the internal operation clock.

According to a third aspect of the present invention, in the semiconductor device according to the second aspect, the absolute time generation circuit has a charge / discharge circuit which starts charging in response to a counting start signal and a voltage level of the charge / discharge circuit. It is composed of an A / D converter for converting the output result of the A / D converter and a decoder whose output becomes active when the output result of the A / D converter reaches a predetermined value.

According to a fourth aspect of the present invention, in the semiconductor device according to the first aspect, the frequency band detection circuit includes a delay element for delaying the counting start signal for a fixed time regardless of the internal operation clock, and a counting start signal. Determines the frequency band of the internal operation clock based on the counter that starts counting the internal operation clock in response and ends the counting of the internal operation clock in response to the output of the delay element and the count value at the end of counting by the counter And a band discriminating means.

A semiconductor device according to a fifth aspect is the semiconductor device according to the second aspect.
In the semiconductor device described in 3 or 4, the count start signal is an oscillation stabilization wait completion signal output from the internal circuit.

A semiconductor device according to a sixth aspect is the semiconductor device according to the first aspect, wherein the frequency band detection circuit has a plurality of filters having different pass frequency bands for selectively passing the internal operation clock for each frequency band, It is composed of a plurality of information holding means for holding information on the presence or absence of passage of the internal operation clock in the plurality of filters, and a band discriminating means for discriminating the frequency band of the internal operation clock based on the held contents of the plurality of information holding means.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION (First Embodiment) A semiconductor device according to a first embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a configuration of a semiconductor device according to an embodiment of the present invention. In FIG.
Reference numeral 1 denotes a semiconductor device integrated into an integrated circuit. Reference numeral 2 is an oscillation capacity optimization circuit. Reference numeral 3 is an internal circuit of the semiconductor device 1. Reference numeral 4 is an internal operation clock 1 used in the semiconductor device 1.
01, the oscillation stabilization wait completion signal 102 output from the internal circuit 3 of the semiconductor device 1 and the reset signal 105 of the semiconductor device 1 are input, the frequency band of the internal operation clock 101 is detected, and the band detection signal 10 is detected as the detection result.
A frequency band detection circuit for outputting 3, 104. 5 outputs the internal operation clock 101, and the band detection signal 10
3, 104 is an oscillation amplifier circuit that selectively controls the oscillation current capability according to the detection result of the frequency band detection circuit 4.

The term "oscillation current capability" as used herein refers to the current capability of a transistor that amplifies the waveform amplitude.
If the current capability of this transistor is small, it is not possible to amplify high frequency waveforms. On the contrary, when the current capacity is high, it means that there is an extra capacity to oscillate at a low frequency.

Reference numeral 21 is a reset terminal provided in the semiconductor device 1, 22 is an oscillation input terminal provided in the semiconductor device 1, and 23 is an oscillation output terminal provided in the semiconductor device 1. 24 is an external oscillator connected between the oscillation input terminal 22 and the oscillation output terminal 23; 25 is an external capacitor connected between the oscillation input terminal 22 and the ground; 26 is the oscillation output terminal 23
It is an external capacitor connected between the and ground.

The reset signal 105 is a signal applied from the reset terminal 21 of the semiconductor device 1, and is set to "1" at reset and "0" at reset release.
The oscillation stabilization wait completion signal 102 is the internal operation clock 10
It is a signal indicating that the oscillation stabilization wait of 1 is completed, and is set to "1" only during one cycle period of the internal operation clock when the oscillation stabilization wait is completed, and to "0" in other cases.
Band detection signals 103 and 104 are signals for controlling the capacity of the oscillation inverter of oscillation amplification circuit 5.

FIG. 5 shows an internal circuit of the oscillation amplifier circuit 5. The oscillation amplifier circuit 5 is composed of oscillation inverters 17, 18, 19 having the oscillation input terminal 22 as a gate and the oscillation output terminal 23 as a drain, and a feedback resistor 232. 220 and 221 are inverters. 222-226
Are P-channel transistors 227 to 231 forming the oscillation inverters 17, 18, and 19 are N-channel transistors.

Three oscillating inverters 17, 18 and 19 exist in parallel between the oscillating input terminal 22 and the oscillating output terminal 23. Among them, the oscillating inverters 17 and 18 are operated / not operated by the band detection signals 103 and 104. The operation is selectively controlled.

Specifically, when the internal operation clock 101 is high-speed, that is, when the band detection signals 103 and 104 are both "1", the oscillation inverters are all three stages, that is, the oscillation inverters 17, 18, and 19. All used.

When the internal operation clock 101 is at a medium speed, that is, when the band detection signals 103 and 104 are "1" and "0", respectively, the oscillation inverters have only two stages, that is, only the oscillation inverters 18 and 19. used.

When the internal operation clock 101 is low speed, that is, when the band detection signals 103 and 104 are both "0", only one oscillation inverter, that is, only the oscillation inverter 19 is used.

Next, a specific configuration and operation of the frequency band detection circuit 4 will be described with reference to FIGS. 2 and 6. FIG. 2 is a block diagram showing a specific configuration of the frequency band detection circuit 4. FIG. 6 shows the frequency band detection circuit 4
3 is an operation timing chart of the above.

The functional role of each element constituting the frequency band detection circuit 4 and the operation of the frequency band detection circuit 4 will be described below with reference to FIGS. 2 and 6.

In FIG. 2, 6 is an A / D converter, 7 is a decoder, 8 is a counter, 9 is a decoder, and 16 is an absolute time generation circuit. 201 and 202 are flip-flops,
203 is a resistor, 204 is a capacitor, 205, 206, 207.
Is a flip-flop, and 208 and 209 are AND circuits.

The absolute time generation circuit 16 generates an output after a lapse of a certain time, regardless of the internal operation clock 101, starting from the oscillation stabilization wait completion signal 102 which is a counting start signal. The counter 8 starts counting the internal operation clock 101 in response to the oscillation stabilization wait completion signal 102, and responds to the output of the absolute time generation circuit 16 in the internal operation clock 1
The counting of 01 is completed. The decoder 9 functions as a band discriminating unit that discriminates the frequency band of the internal operation clock 101 based on the count value of the counter 8 at the end of counting.

The absolute time generation circuit 16 described above has a resistor 204 which starts charging in response to the oscillation stabilization wait completion signal 102.
And a capacitor 204, an A / D converter 6 for encoding the voltage level of the charge / discharge circuit (203, 204), and an output result of the A / D converter 6 for decoding A / D
It has a decoder 7 whose output becomes active when the output result of the D converter 6 reaches a predetermined value as a main component.

It should be noted that all the flip-flops 201, 202, 205, 20 constituting the frequency band detection circuit 4
The outputs of 6, 207 and the count value of the counter 8 are initialized to "0" at reset.

In the semiconductor device 1, when the oscillation stabilization wait completion signal 102 changes from "0" to "1" after reset release (after the reset signal 105 changes to "0"), the output of the flip-flop 201 becomes "1". 0 ”to“ 1 ”
The counter 8 starts counting.
The counter 8 counts the clocks appearing on the signal line 111. Here, the counter 8 is a counter whose count value increases by 1 at the rising edge of the internal operation clock 101, and the operation time of the counter 8 is generated by the absolute time generation circuit 16.

Next, the operation of the absolute time generation circuit 16 will be described. The flip-flop 202 is an element for charging the capacitor 204 with electric charge, and outputs “1” upon receiving the output of the flip-flop 201.
The positive charge is charged via the, and the potential level of the signal line 106 rises with the passage of time. The time when the charging of the electric charge is completed is determined by the resistor 203 and the capacitor 204.

A / D converter 6 having M-bit conversion accuracy
Measures the potential level of the signal line 106, encodes it, and outputs it to the signal line 107 with M bits. The decoder 7 (signal line 108) outputs “0” after reset release, but the signal line 107 changes from “0” to “0” when all the M bits of the signal line 107, that is, when charging of the capacitor 204 is completed. "1"
Changes to.

At the rising edge of the signal line 108, the output of the flip-flop 205 changes from "0" to "1", and the counting operation of the counter 8 is completed. Counter 8 within the time generated by the absolute time generation circuit 16
The count value of changes according to the speed of the operation clock 101, and the numerical value is large when the internal operation clock 101 is high speed and small when the internal operation clock 101 is low speed.

In this example, the frequency band is classified into three by the decoder 9 based on the count value of the counter 8, but the decoding result can be further subdivided.

The flip-flops 206 and 207 are for controlling the decoding of the decoder 9 to be started after the count of the counter 8 is completed, and have a function of starting the decoding of the decoder 9 after the count value of the counter 8 is fixed. Hold. The oscillation amplifier circuit 5 receives the band detection signals 103 and 104, which are the decoding results of the decoder 9, as input, and controls the oscillation output current capability. In FIG. 6, the band detection signals 103 and 104 are both “1”,
The state changes according to the count value of the counter 8.

The band detection signal 103 is an input signal to the transistors 223 and 231 of the oscillation amplification circuit 5, and controls the operation of the inverter 18. The band detection signal 104 is an input signal to the transistors 222 and 230 of the oscillation amplification circuit 5 and controls the operation of the inverter 17.

By controlling the operation of the inverters 17 and 18, it is possible to change the oscillation current capability of the oscillation amplification circuit 5 depending on the frequency band. The oscillation current capability of the oscillation amplifier circuit 5 can be controlled in three stages of level 1, level 2 and level 3, assuming that level 1 is the minimum oscillation current capability and level 3 is the maximum oscillation current capability.
3, 104 and transistors 222, 223, 230, 2
The relationship of 31 will be described below.

First, a case where the count value of the counter 8 is large will be described. When the count value is large, the semiconductor device 1 is operating in the high frequency band, and therefore the inverters 17 and 18 inside the oscillation amplification circuit 5 are controlled to operate. Therefore, the decoder 9 uses the band detection signal 1
The oscillation amplifier circuit 5 outputs "1" to both 03 and 104.
The transistors 222, 223, 230, and 231 of FIG.
To

Next, a case where the count value of the counter 8 is medium will be described. When the count value is medium, the semiconductor device 1 is operating in the medium frequency band.
Control is performed to operate the inverter 18 inside the oscillation amplification circuit 5. Therefore, the decoder 9 uses the band detection signal 1
"1" to 03 and "0" to the band detection signal 104,
The transistors 223 and 231 of the oscillation amplification circuit 5 are operated to set the capacity of the inverter of the oscillation amplification circuit 5 to level 2.

Finally, a case where the count value of the counter 8 is small will be described. When the count value is small, the semiconductor device 1 is operating in the low frequency band, and therefore the inverters 17 and 18 inside the oscillation amplification circuit 5 are controlled not to operate. Therefore, the decoder 9 outputs “0” to both the band detection signals 103 and 104, does not operate the transistors 222, 223, 230 and 231 of the oscillation amplification circuit 5, and sets the inverter capability of the oscillation amplification circuit 5 to level 1. To

According to this embodiment, the internal operation clock 101 is counted by the counter 108 for the time defined by the absolute time generation circuit 16, and the frequency band of the internal operation clock 101 is determined based on the count result. Since the oscillation current capability of the oscillation amplification circuit 5 is optimally selected and controlled according to the determination result, it is possible to detect the oscillation frequency band of the system and automatically set the optimal oscillation current capability for the system. The system consumption can be reduced while taking advantage of the semiconductor devices used for various purposes.

(Second Embodiment) Next, a semiconductor device according to a second embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. This embodiment is different from the first embodiment in the specific configuration and operation of the frequency band detection circuit 4, but is otherwise the same as the first embodiment.

The specific structure and operation of the frequency band detection circuit 4 in this embodiment will be described with reference to FIGS. 3 and 7. FIG. 3 is a block diagram showing a specific configuration of the frequency band detection circuit 4. FIG. 7 is an operation timing chart of the frequency band detection circuit 4.

The functional role of each element constituting the frequency band detection circuit 4 and the operation of the frequency band detection circuit 4 will be described below with reference to FIGS. 3 and 7.

In FIG. 3, 10 is a delay element, 11 is a counter, and 12 is a decoder. 210 to 213 are flip-flops, and 214 and 215 are AND circuits.

The delay element 10 outputs the oscillation stabilization wait completion signal 102, which is a counting start signal, to the internal operation clock 10
It is delayed for a fixed time regardless of 1. Counter 11
The counting of the internal operation clock 101 is started in response to the oscillation stabilization wait completion signal 102, and the counting of the internal operation clock 101 is ended in response to the output of the delay element 10. The decoder 12 functions as a band discriminating means for discriminating the frequency band of the internal operation clock 101 based on the count value of the counter 11 at the end of counting.

The outputs of all the flip-flops 210 to 213 and the count value of the counter 11 which constitute the frequency band detection circuit 4 are initialized to "0" at reset.

In the semiconductor device 1, when the oscillation stabilization wait completion signal 102 changes from "0" to "1" after reset release (after the reset signal 105 changes to "0"), the output of the flip-flop 210 becomes "1". 0 ”to“ 1 ”
And the counting operation of the counter 11 is started. The counter 11 counts the clocks appearing on the signal line 112. Here, the counter 11 is a counter whose count value increases by 1 at the rising edge of the internal operation clock 101.

The output of the flip-flop 210 propagates to the signal line 113 through the delay element 10, but at this time, the delay element 10 delays for a predetermined time. This time is the count operation time of the counter 11. Signal line 11
At the rising edge when 3 changes from "0" to "1", the output of the flip-flop 211 changes from "0" to "1", and the counting operation of the counter 11 ends. Counter 11 within time generated by delay element 10
The count value of changes according to the speed of the operation clock 101, and the numerical value is large when the internal operation clock 101 is high speed and small when the internal operation clock 101 is low speed.

In this example, the frequency band is divided into three by the decoder 12 based on the count value of the counter 11, but the decoding result can be further subdivided.

The flip-flops 212 and 213 are for controlling the decoding of the decoder 12 to be started after the counter 11 has finished counting, and have a function of starting the decoding of the decoder 12 after the count value of the counter 11 is fixed. Hold. The oscillation amplifier circuit 5 receives the band detection signals 103 and 104, which are the decoding results of the decoder 12, as input, and controls the oscillation output current capability. In FIG. 7, both the band detection signals 103 and 104 are “1”, but the state changes according to the count value of the counter 11.

The band detection signal 103 is an input signal to the transistors 223 and 231 of the oscillation amplification circuit 5, and controls the operation of the inverter 18. The band detection signal 104 is an input signal to the transistors 222 and 230 of the oscillation amplification circuit 5 and controls the operation of the inverter 17.

By controlling the operations of the inverters 17 and 18, it is possible to change the oscillation current capability of the oscillation amplification circuit 5 according to the frequency band. The oscillation current capability of the oscillation amplifier circuit 5 can be controlled in three stages of level 1, level 2 and level 3, assuming that level 1 is the minimum oscillation current capability and level 3 is the maximum oscillation current capability.
3, 104 and transistors 222, 223, 230, 2
The relationship of 31 will be described below.

First, the case where the count value of the counter 11 is large will be described. If the count value is high,
Since the semiconductor device 1 operates in the high frequency band, it controls the operation of the inverters 17 and 18 inside the oscillation amplification circuit 5. Therefore, the decoder 11 outputs “1” to both the band detection signals 103 and 104, operates the transistors 222, 223, 230, and 231 of the oscillation amplification circuit 5 to set the capacity of the inverter of the oscillation amplification circuit 5 to level 3. To

Next, a case where the count value of the counter 11 is medium will be described. When the count value is medium, the semiconductor device 1 is operating in the medium frequency band.
Control is performed to operate the inverter 18 inside the oscillation amplification circuit 5. Therefore, the decoder 11 outputs "1" to the band detection signal 103 and "0" to the band detection signal 104 to operate the transistors 223 and 231 of the oscillation amplification circuit 5 to check the capability of the inverter of the oscillation amplification circuit 5. Set to level 2.

Finally, the case where the count value of the counter 11 is small will be described. If the count value is small,
Since the semiconductor device 1 operates in the low frequency band, control is performed so that the inverters 17 and 18 inside the oscillation amplification circuit 5 are not operated. Therefore, the decoder 11 outputs “0” to both the band detection signals 103 and 104, and the transistors 222, 223, 230 and 231 of the oscillation amplifier circuit 5 are output.
Is not operated, and the capacity of the inverter of the oscillation amplification circuit 5 is set to level 1.

According to this embodiment, the internal operation clock 101 is counted by the counter 11 for the time defined by the delay element 10, and the frequency band of the internal operation clock 101 is determined based on the count result. Since the oscillation current capability of the oscillation amplification circuit 5 is optimally selected and controlled according to the determination result, it is possible to detect the oscillation frequency band of the system and automatically set the optimal oscillation current capability for the system. It is possible to reduce the system consumption while taking advantage of the semiconductor device used for various purposes.

(Third Embodiment) Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS.
Will be described with reference to. This embodiment is different from the first embodiment in the specific configuration and operation of the frequency band detection circuit 4, but is otherwise the same as the first embodiment.

The specific structure and operation of the frequency band detection circuit 4 in this embodiment will be described with reference to FIGS. 4 and 8. FIG. 4 is a block diagram showing a specific configuration of the frequency band detection circuit 4. FIG. 8 is an operation timing chart of the frequency band detection circuit 4.

The functional role of each element constituting the frequency band detection circuit 4 and the operation of the frequency band detection circuit 4 will be described below with reference to FIGS. 4 and 8.

In FIG. 4, 13 is a low-pass filter,
Reference numeral 14 is a medium-pass filter, and 15 is a decoder. 21
Reference numerals 6, 218 and 219 are flip-flops and 217 is an AND circuit.

The low-pass filter 13 has a function of selectively passing the internal operation clock 101 only when the internal operation clock 101 is low speed. The medium-speed pass filter 14 has a function of selectively passing the internal operation clock 101 only when the internal operation clock 101 is at a medium speed. The flip-flops 218 and 219 function as a plurality of information holding units that hold information regarding whether or not the internal operation clock 101 has passed through the low speed pass filter 13 and the medium speed pass filter 14. Decoder 15
Functions as a band discriminating means for discriminating the frequency band of the internal operation clock 101 based on the contents held in the flip-flops 218 and 219.

The values of all the flip-flops 216, 218 and 219 which constitute the frequency band detection circuit 4 are
It shall be initialized to "0" at the time of reset.

In the semiconductor device 1, when the oscillation stabilization waiting completion signal 102 changes from "0" to "1" after reset release (after the reset signal 105 changes to "0"), the output of the flip-flop 216 becomes "1". 0 ”to“ 1 ”
, And the internal operation clock 101 propagates to the signal line 117. The low-pass filter 13 is a filter that passes only the low-speed clock, and the medium-speed filter 14 is a filter that passes only the low-speed clock.

The flip-flop 218 is connected to the signal line 117.
Is for judging that the internal operation clock 101 propagated through the low-pass filter 13 has passed through the low-speed filter 13, that is, the clock appears on the signal line 118. 1 ", and if it does not pass," 0 "is output.

The flip-flop 219 is connected to the signal line 117.
This is for determining that the internal operation clock 101 that has propagated through the medium speed pass filter 14 has been passed, that is, that a clock has appeared on the signal line 119. If it does not pass, it outputs "0".

FIG. 8 shows that the internal operation clock 1 has passed through the low-pass filter 13, the output of the flip-flop 218 is "1", and the flip-flop 21 is
The output of 9 is "0", and the band detection signal 103,
Both 104 are “0”.

In this example, the flip-flops 218 and 21
From the result of No. 9, the description will be made by classifying the frequency band into three by the decoder 15, but by adding a bandpass filter,
It is also possible to subdivide the frequency band.

The band detection signal 103 is an input signal to the transistors 223 and 231 of the oscillation amplifier circuit 5, and controls the operation of the inverter 18. The band detection signal 104 is an input signal to the transistors 222 and 230 of the oscillation amplification circuit 5 and controls the operation of the inverter 17.

By controlling the operations of the inverters 17 and 18, it is possible to change the oscillation current capability of the oscillation amplification circuit 5 depending on the frequency band. The oscillation current capability of the oscillation amplifier circuit 5 can be controlled in three stages of level 1, level 2 and level 3, assuming that level 1 is the minimum oscillation current capability and level 3 is the maximum oscillation current capability.
3, 104 and transistors 222, 223, 230, 2
The relationship of 31 will be described below.

First, when only the flip-flop 218 changes from "0" to "1", the semiconductor device 1 is operating in the low frequency band, so that the inverters 17 and 18 in the oscillation amplification circuit 5 are operated. Perform control not to allow.
Therefore, the decoder 15 uses the band detection signals 103 and 104.
"0" is output to the transistor 22 of the oscillation amplifier circuit 5.
The level of the inverter of the oscillation amplification circuit 5 is set to level 1 without operating 2, 223, 230 and 231.

Next, when only the flip-flop 219 changes from "0" to "1", since the semiconductor device 1 is operating in the medium frequency band, the inverter 18 inside the oscillation amplification circuit 5 is operated. Take control. Therefore, the decoder 15 outputs “1” to the band detection signal 103 and “0” to the band detection signal 104, operates the transistors 223 and 231 of the oscillation amplification circuit 5, and determines the capacity of the inverter of the oscillation amplification circuit 5. Set to level 2.

Finally, flip-flops 218 and 219
If the value does not change from “0”, the semiconductor device 1 is operating in the high frequency band, and therefore the inverters 17 and 18 in the oscillation amplification circuit 5 are controlled to operate. Therefore, the decoder 15 outputs “1” to the band detection signals 103 and 104, and the transistor 22 of the oscillation amplification circuit 5
The level of the inverter of the oscillation amplification circuit 5 is set to level 3 without operating 2, 223, 230, and 231.

According to the semiconductor device of this embodiment, the low-pass filter 13 and the medium-speed pass filter 14 are provided to detect whether the internal operation clock 101 passes through the low-pass filter 13 and the medium-speed pass filter 14. , The frequency band of the internal operation clock 101 is determined based on the result, and the oscillation amplification circuit 5 is determined according to the result of the determination.
Since the oscillation current capacity of the system is optimally selected and controlled, it is possible to detect the oscillation frequency band of the system and automatically set the optimal oscillation current capacity for the system. It is possible to reduce the system consumption while making the most of the advantage.

[0073]

According to the semiconductor device of the present invention, the frequency band determination circuit determines the frequency band of the internal operation clock, and the oscillation current capability of the oscillation amplifier circuit is optimally selected based on the determination result. It is possible to automatically set the optimum oscillation current capacity for the system by detecting the oscillating frequency band of the system, and to achieve the low power consumption of the system while taking advantage of the semiconductor devices used in various applications. Is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a frequency band detection circuit according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a configuration of a frequency band detection circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a configuration of a frequency band detection circuit according to a third embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an oscillation amplifier circuit according to the first embodiment of the present invention.

FIG. 6 is a time chart in the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a time chart in the semiconductor device according to the second embodiment of the present invention.

FIG. 8 is a time chart in the semiconductor device according to the third embodiment of the present invention.

[Explanation of symbols]

1 Semiconductor device 2 Oscillation capacity optimization circuit 3 Internal circuit 4 Frequency band detection circuit 5 Oscillation amplifier circuit 6 A / D converter 7 decoder 8 counter 9 decoder 10 Delay element 11 counter 12 decoder 13 Low-pass filter 14 Medium speed filter 15 decoder 16 Absolute time generation circuit 17,18,19 Inverter 21 Reset terminal 22 Oscillation input terminal 23 Oscillation output terminal 24 oscillator 25,26 External capacity 101 Internal operation clock 102 Oscillation stabilization wait completion signal 103, 104 band detection signal 105 reset signal 106 Input signal of A / D converter 6 107 Output signal of A / D converter 6 108 Decoder 7 output signal 111 Count clock of counter 8 112 Count clock of the counter 11 113 Output signal of delay element 10 117 Internal operation clock after passing through the gate 217 118 Output signal of low-pass filter 13 119 Output signal of the medium-speed pass filter 14 120 Input signal of decoder 9 121 Input signal of the decoder 12 201,202 flip-flop 203 resistance 204 capacity 205-207 flip-flops 208,209 AND circuit 210-213 flip-flops 214,215 AND circuit 216 flip-flops 217 AND circuit 218 and 219 flip-flops 220,221 logic circuit 222-226 P-channel transistor 227-231 N-channel transistor 232 Feedback resistor

Claims (6)

[Claims] 1. An oscillation amplifier circuit which can select an oscillation current capacity and outputs an internal operation clock, and a frequency band detection circuit which detects a frequency band of the internal operation clock. A semiconductor device, wherein the oscillation current capability of the oscillation amplifier circuit is selected according to a detection result. 2. The frequency band detection circuit includes an absolute time generation circuit that generates an output after a lapse of a predetermined time regardless of the internal operation clock, starting from the counting start signal, and the internal operation clock in response to the counting start signal. Start counting
A counter for ending the counting of the internal operation clock in response to the output of the absolute time generation circuit; and a band discriminating means for discriminating the frequency band of the internal operation clock based on the count value at the end of counting by the counter. The semiconductor device according to claim 1, wherein 3. An absolute time generation circuit, a charge / discharge circuit that starts charging in response to a count start signal, an A / D converter that encodes the voltage level of the charge / discharge circuit, and the A / D converter. 3. The semiconductor device according to claim 2, further comprising: a decoder that decodes the output result of 1. and the output of which becomes active when the output result of the A / D converter reaches a predetermined value. 4. The frequency band detection circuit includes a delay element that delays the counting start signal for a fixed time regardless of the internal operation clock, and starts counting the internal operation clock in response to the counting start signal, and delays the delay. 2. A counter comprising: a counter for ending counting of the internal operation clock in response to an output of an element; and a band discriminating means for discriminating a frequency band of the internal operation clock based on a count value at the end of counting by the counter. The semiconductor device described. 5. The semiconductor device according to claim 2, 3 or 4, wherein the counting start signal is an oscillation stabilization wait completion signal output from an internal circuit. 6. The frequency band detection circuit includes a plurality of filters having different pass frequency bands for selectively passing the internal operation clock for each frequency band, and information on whether or not the internal operation clock passes through the plurality of filters. 2. The semiconductor device according to claim 1, comprising a plurality of information holding means for holding and a band discriminating means for discriminating a frequency band of the internal operation clock based on the held contents of the plurality of information holding means.