JPH0946185A - Flip-flop, sequential circuit and semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] Input data is held at both levels of the clock signal, and the stored contents are held stably. [Structure] Static storage elements 11 and 12 for holding input data DI, and static storage element 1
1, transfer gates 13 and 15 connected to the input terminal and the output terminal, respectively, and transfer gates 14 and 1 connected to the input terminal and the output terminal of the static memory element 12, respectively.
6, the data input ends of the transfer gates 13 and 14 are connected to each other, the data output ends of the transfer gates 15 and 16 are connected to each other, and the transfer gates 13 and 16 are turned on or off. When transfer gates 15 and 14
Is turned on and off.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop that holds input data at both levels of a clock signal, a sequential circuit in which the flip-flops are cascade-connected, and the flip-flop or the sequential circuit. The present invention relates to a semiconductor device including.

[0002]

2. Description of the Related Art A double edge trigger type flip-flop is disclosed in, for example, Japanese Unexamined Patent Publication No. 6-152336, and has two storage elements and holds input data in one storage element at the rising edge of a clock signal. However, it is configured to be held in the other storage element at the falling edge of the clock signal.

[0003]

However, in the conventional flip-flop, since each storage element is composed of one dynamic inverter, the stored contents become unstable due to the leakage of the retained charges. Further, since the input data can be held only at the timing of the edge of the clock signal, the shift of the clock signal supplied to the clock input terminal of each flip-flop is a problem in the sequential circuit in which the flip-flops are connected in cascade. Therefore, the improvement of the clock frequency for high speed operation is limited.

The object of the invention is to solve the above problems.
A flip-flop capable of holding input data at any of both levels of a clock signal and capable of stably holding storage contents, a sequential circuit using the flip-flop, and the flip-flop or the order It is to provide a semiconductor device including a circuit.

[0005]

In the flip-flop of the first invention, as shown in FIG. 1A, for example, first and second static type memory elements 11 for holding input data DI are provided. And 12, first and second transfer gates 13 and 15 connected to the input terminal and the output terminal of the first static memory element 11, respectively, and the input terminal and the output terminal of the second static memory element 12. Third and fourth transfer gates 14 and 1 respectively connected to
6 and the first and third transfer gates 13 and 14
Data input terminals are connected to each other, data output terminals 15 and 16 of the second and fourth transfer gates are connected to each other, and control input terminals of the first to fourth transfer gates are connected to the first and The second and third transfer gates 1 and 4 when the fourth transfer gates 13 and 16 are turned on or off.
The clock signal CLK is supplied so that 5 and 14 are turned on and off.

FIG. 1B is a timing chart showing an example of the operation of this flip-flop. When the clock signal CLK is at high level, the first and fourth transfer gates 1
3 and 16 are turned on and the second and third transfer gate 1
5 and 14 are turned off, the input data DI is held in the first static memory element 11, and at the same time, the data DB held in the second static memory element 12 is output as data DO.

When the clock signal CLK is low level, the second and third transfer gates 15 and 14 are turned on and the first and fourth transfer gates 13 and 16 are turned off,
The input data DI is held in the second static memory element 12, and at the same time, the data DA held in the first static memory element 11 is output as data DO.

Therefore, according to this flip-flop, the input data can be held at both of the levels of the clock signal, and the stored contents can be held stably. In the first aspect of the first aspect of the invention, as shown in FIG. 3, for example, both the first and second static storage elements have a setting input terminal, and a storage value is set by a signal supplied to the setting input terminal. Is forced to one of two values.

In the sequential circuit according to the second aspect of the invention, the flip-flops are cascaded in a plurality of stages. According to this sequential circuit, since the flip-flop can hold the input data at both of the levels of the clock signal, the deviation margin of the clock signal supplied to the clock input terminal of each flip-flop has a double edge trigger type. This is larger than the case where a flip-flop is used, and the clock frequency can be further improved.

A semiconductor device of a third invention has the above flip-flop or a sequential circuit. According to this semiconductor device, the operation of the semiconductor device is speeded up.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. [First Embodiment] FIG. 2 shows a flip-flop 10A of the first embodiment. Component 11 of flip-flop 10A
A to 16A correspond to the constituent elements 11 to 16 of FIG. 1, respectively.

The static type memory element 11A and the static type memory element 12A have the same structure, and in the static type memory element 11A, the output terminal of the inverter 111 is connected to the input terminal of the inverter 112, and the output of the inverter 112 is the inverter. Connected to the input end of 111,
The input / output terminal of the inverter 111 is the input / output terminal of the static memory element 11A. In the static memory elements 11A and 11B, the output is a signal obtained by inverting the logic level of the input, so the inverter 19 is connected to the data output terminals of the transfer gates 15A and 16A, and the inverter 1
Data DO is output from 9.

The transfer gates 13A to 16A have the same structure, and each of them has an nMIS transistor and a pMIS.
The transistors are connected in parallel, and clock signals whose logic levels are opposite to each other are supplied to the gates of both transistors. Clock signal CLK
Is a gate signal of the pMIS transistor of the transfer gates 13A and 16A and the nMI of the transfer gates 14A and 15A as the clock signal CLK1 via the inverter 17.
It is supplied to the gate of the S transistor. Clock signal C
LK1 further receives the clock signal CL via the inverter 18.
As K2, the gates of the nMIS transistors of the transfer gates 13A and 16A and the transfer gates 14A and 15A
Is supplied to the gate of the pMIS transistor.

The operation of the flip-flop 10A is the same as the operation shown in FIG. 1 (B) described above, and its explanation is omitted. [Second Embodiment] FIG. 3 shows a flip-flop 10B of the second embodiment. This flip-flop 10B uses static storage elements 11B and 12B instead of the static storage elements 11A and 12A of FIG. 2, respectively. The static memory elements 11B and 12B have the same configuration as each other, and
The output terminal of the NAND gate 113 is connected to the input terminal of the inverter 112, the output terminal of the inverter 112 is connected to one input terminal of the NAND gate 113, and the NAND gate 1
The input end and the output end of 13 are static memory elements 1
It becomes the data input / output terminal of 1B, and the other input terminal of the NAND gate 113 is the input terminal of the clear signal CLR (setting input terminal).
It has become.

When the clear signal CLR is at high level, the NAND gate 113 functions as an inverter and operates in the same manner as the flip-flop 10A shown in FIG. Clear signal CL
When R is at a low level, the outputs DA and DB of the static memory elements 11B and 12B are both at a high level, and the output data DO is "0" regardless of which of the transfer gates 15A and 16A is on.

[Third Embodiment] FIG. 4 shows a general sequential circuit of a third embodiment using the flip-flop of the present invention. In this sequential circuit, the combinational circuit 201 is connected between the flip-flop 101 and the flip-flop 102, and the flip-flop 102 and the flip-flop 1 are connected.
03 is connected to the non-inverting buffer gate 3 at the Q output terminal of the flip-flop 103.
0 is connected. Flip-flops 101-103
1 has the same configuration as the flip-flop 10 shown in FIG. 1A, and the clock signal CLK is supplied to each clock input terminal CK. Combination circuits 201 and 202
In addition to the outputs of the flip-flops 101 and 102, the data DP and DQ are supplied to each.

At each of both levels of the clock signal CLK, the input data DI is held in the flip-flop 101, the output of the combination circuit 201 is held in the flip-flop 102, and the output of the combination circuit 202 is held in the flip-flop 103. Therefore, the deviation margin of the clock signal CLK supplied to the clock input terminal CK of each of the flip-flops 101 to 103 becomes larger than that in the case of using the double edge trigger type flip-flop, and the clock frequency can be further improved. .

The present invention includes various modifications other than the above. For example, the flip-flops of the present invention are various FEs.
Either T or bipolar transistor may be used. Further, the flip-flop or the sequential circuit of the present invention is used in various semiconductor devices for holding data.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit and an operation of a flip-flop of the present invention.

FIG. 2 is a logic circuit diagram showing a flip-flop according to the first exemplary embodiment of the present invention.

FIG. 3 is a logic circuit diagram showing a flip-flop according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a sequential circuit of a third embodiment using a flip-flop of the present invention.

[Explanation of symbols]

10, 10A, 10B, 101-103 Flip-flop 11, 11A, 11B, 12, 12A, 12B Static type memory element 13-16, 13A, 14A, 15A, 16A Transfer gate 17-19, 111, 112 Inverter 113 NAND gate 201 , 202 Combination circuit

Claims (4)

[Claims] 1. A first and a second static memory element for holding input data, and first and second transfer gates respectively connected to an input terminal and an output terminal of the first static memory element. And third and fourth transfer gates respectively connected to an input terminal and an output terminal of the second static memory element,
Data input terminals of the first and third transfer gates are connected to each other, data output terminals of the second and fourth transfer gates are connected to each other, and control input terminals of the first to fourth transfer gates are connected to each other. Is supplied with a clock signal such that when the first and fourth transfer gates are turned on or off, the second and third transfer gates are turned on or off. A flip-flop characterized by the following. 2. The first and second static memory elements each have a setting input terminal, and a signal supplied to the setting input terminal forces a memory value to one of two values. The flip-flop according to claim 1, wherein: 3. A sequential circuit comprising a plurality of flip-flops according to claim 1 connected in cascade. 4. A semiconductor device comprising the flip-flop according to claim 1 or 2 or the sequential circuit according to claim 3.