JPH0944464A - Ring bus multiprocessor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ring bus multiprocessor which has more flexibility and is capable of high speed data transfer. SOLUTION: The transfer instruction issued in a processor node 1-1 is selected by the selector node 2-1 to which the instruction reaches first and is sent to a poststage. In other selector nodes 2-2 to 2-8, the inputs from bypass connection lines 3-2 to 3-8 are selected and are sent to the poststage. The same transfer instruction which reaches the selector nodes 2-2 to 2-8 later is recognized as the same instruction is rejected by the comparison of the message ID and the contents of the message ID register in the interior where the message ID of the transfer instruction transferred previous time is stored. The transfer instruction returning after making a round is rejected in the processor node 1-1 issuing the instruction and the selector node 2-1 where the instruction reaches first.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ring bus multiprocessor device in which a plurality of processors are coupled in a ring shape, and more particularly to data transfer in the ring bus multiprocessor device.

[0002]

2. Description of the Related Art Conventionally, when data is transferred between multiprocessors connected by a ring bus, in order to reduce a delay related to the data transfer, for example, Japanese Patent Publication No. 58-58.
It has been devised to use a bypass connecting wire as described in Japanese Patent Publication No. 29550.

FIG. 6 is a block diagram showing an example of a conventional multiprocessor device using a bypass connection line. In the figure, 40-1 to 40-6 are processors, and 41-1 to 41
-3 is a selector, and 42-1 and 42-2 are selector control circuits. The processors 40-1 to 40-3 and the processors 40-4 to 40-6 are each configured as one processor block. Each processor operates in three modes regarding data transfer: a data transmission state, a data shift state, and a data through state.

For each block, selectors 41-1 to 41-3 are provided at the output end of the block. Then, from the input end of the block, selectors 41-1 to 4-4
Bypass connection lines for bypassing 1-3 are provided in parallel.

Selector control circuits 42-1 and 42-2
Means that when any processor in the corresponding block is in the data transmission state or the data shift state, the corresponding selectors 41-2 and 41-3 do not use the bypass.
Control. Further, when all the processors in the corresponding block are in the data through state, the corresponding selectors 41-2 and 41-3 are controlled to use the bypass. Therefore, the use or non-use of the bypass is uniquely determined by the state of data transfer of the processor.

The route determination method using such a bypass has the following problems. First, in order to determine the data transfer path, it is necessary to change the data transfer mode of each processor. Data transfer is
Since it is desirable to flexibly perform various forms according to the situation at each time, changing the data transfer mode relating to all the processors each time causes a large overhead in the data transfer. Next, in the data transfer in the multiprocessor device, the scheduling of the transfer path and the like is centrally performed using the node ID and the group ID. Introducing the concept of the data transfer mode of the processor here leads to overhead from a software point of view. Due to such overheads, there is a problem that the data transfer rate decreases.

[0007]

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object thereof is to provide a ring bus multiprocessor device which is more flexible and is capable of high-speed data transfer. It is what

[0008]

According to the present invention, in a ring bus multiprocessor device, a plurality of processors coupled by a ring bus for outputting transfer data, and some of the processors are arranged in parallel and one end thereof is connected to the ring bus. The output line of the processor or the bypass connection line is selected on the basis of predetermined information contained in the transfer data with one or more connected bypass connection lines and the output line of the processor and the bypass connection line as inputs. Output 1
It is characterized by having the above selection means.

According to a second aspect of the present invention, in the ring bus multiprocessor device according to the first aspect, each processor sends a transfer instruction for outputting new transfer data unique to the transfer data to be output in the entire device. And outputs a message ID indicating the order of issue of the message, the selecting means stores the message ID, the content of the message ID register, and the ID in the transfer data output by the processor at the preceding stage. A first comparator for comparing messages, a second comparator for comparing the contents of the message ID register and an ID message in transfer data input from the bypass connection line, an output of the bypass connection line and processor Based on the outputs of the first comparator and the second comparator. It is characterized in that it has a control means for controlling the selection in the update and the selection circuit message ID register.

[0010]

By simply connecting the bypass connecting line and the output line from the processor located immediately before to the selecting means, whether the transfer data to be processed is issued by the processor located before the selecting means or not. It is not possible to determine whether the transfer data that came via the processor was delayed and sent from the processor. Therefore, when the transfer data which has been once transferred is input to the selecting means with a delay, it is necessary to configure so that the transfer data is not sent again first.

According to the present invention, the selecting means detects predetermined information contained in the transfer data, selects the output line of the processor or the bypass connection line based on the information, and outputs the selected information. Neither is selected for the transfer data that has been transferred. As a result, it is possible to suppress the selection and retransfer of transfer data without having to have a data transfer mode in each processor as in the conventional case, and more flexible and high speed data transfer becomes possible.

At this time, as in the invention described in claim 2, each processor adds the message ID to the transfer data to be output and outputs it, and the selecting means outputs this message I.
It can be configured to select the data based on D. In the selection means, the message ID of the transfer data from the bypass connection line and the message ID in the message ID register are compared by the second comparator, and if different, the transfer circuit selects the transfer data from the bypass connection line in the selection circuit. It is selected by the circuit and output, and the contents of the message ID register are updated. If the comparison result of the second comparator is the same, the transfer data has returned in one cycle and is discarded. In addition, the message ID in the transfer data output from the processor is compared with the message ID in the message ID register by the first comparator, and if different, the transfer newly output from the processor in this block is compared. Since it is data, the transfer data from the processor is selected and output by the selection circuit. At the same time, the contents of the message ID register are updated. If the comparison results of the first comparator are the same, the same transfer data has already been transferred from the bypass connection line, and is therefore rejected.

[0013]

1 is a block diagram showing one embodiment of a ring bus multiprocessor device of the present invention. In the figure, 1-1 to 1-32 are processor nodes, and 2-
1 to 2-8 are selector nodes, and 3-1 to 3-8 are bypass connection lines. Processor nodes 1-1 to 1-32
Is a processor that performs each processing. When a transfer command transferred from another processor node is input, if the transfer command is not addressed to that processor, it is output as it is. At this time, it takes a processing time to input / output the transfer instruction, and the output is sequentially delayed in synchronization with the clock signal as if it were a shift register.

Each of the selector nodes 2-1 to 2-8 inputs the bypass connection lines 3-1 to 3-8 corresponding to the output of the immediately preceding processor node, selects one of them and outputs it. To do. The selection method is performed by decoding a transfer instruction by a circuit provided inside the selector node itself, and the processor nodes 1-1 to 1-
This is done completely independently of the 32 states.

The bypass connection lines 3-1 to 3-8 are arranged so as to bypass some processor nodes, respectively. In the example shown in FIG. 1, the processor nodes 1-1 to 1-32 are divided into eight blocks of four, and bypass connection lines 3-1 to 3-8 are provided for each block. For example, the bypass connection line 3-1 is provided corresponding to the processor nodes 1-1 to 1-4,
It is connected to the input end of the processor node 1-1 and the selector node 2-1 provided corresponding to this block. The same applies to the other bypass connection lines 3-2 to 3-8. Of course, the number of processor nodes in one block is arbitrary in each block, and the number of blocks is also arbitrary. Further, there may be a processor node in which bypass connection lines are not provided in parallel.

The transfer instruction is transferred so as to pass through all the processor nodes. For a transfer instruction issued by one of a plurality of processor nodes located in front of the selector node of interest, that is, a processor node of the block corresponding to the selector node of interest, the bypass connection line is not selected only in that selector node, Bypass connection lines are selected at all other selector nodes.

For example, for the selector node 2-1:
For the transfer instruction issued by the processor node 1-2, the bypass connection line 3-1 is not selected only by the selector node 2-1 and the bypass connection line 3-is generated by all the other selector nodes 2-2 to 2-8. 2 to 3-8 are selected. At this time, for example, in the processor nodes 1-9 to 1-12,
The transfer command transferred via the bypass connection line 3-2 is received. In this way, by selecting the bypass in all the selector nodes except one selector node, the transfer instruction is input to all the processor nodes at high speed.

A transfer instruction that has passed through the ring bus is erased without being propagated any further in the processor node that issued it and the selector node of interest.

FIG. 2 is an explanatory diagram showing an example of transfer instructions handled in one embodiment of the ring bus multiprocessor device of the present invention. In the example shown in FIG. 2, the transfer command is composed of a part including a command instructing transfer and a part of data to be transferred.

The instruction code field is for identifying one of a plurality of ring bus transfer instructions. The data length field is for notifying the length of data handled by the data transfer instruction. The source node ID field and the destination node ID field are for identifying the node ID that issued the command and the node ID that receives the data, respectively. The destination node ID field specifies a unique node ID when the transfer is a single cast, and a group ID when the transfer is a multicast or a broadcast. A unique message ID is assigned to the message ID field for each transfer instruction issued for each processor node that issues the transfer instruction. For example, each time the processor node issues a transfer instruction, the incremented message ID is given. The N data fields following the message ID field are fields for storing data to be transferred.

FIG. 3 is an internal block diagram showing an example of the selector node. In the figure, 11 is a first selection circuit, 12 is a delay circuit, 13 is a second selection circuit, and 14 is a message ID.
A register, 15 is a first comparison circuit, 16 is a second comparison circuit, 17 is a control circuit, 21 is a first input signal line, 22 is a second input signal, 23 is an output signal, and 24 is a first A selection signal, 25 is a second selection signal, 26 is a load signal, 27 is a first comparison signal, and 28 is a second comparison signal.

The first input signal 21 is a transfer command output from the processor node located immediately before the selector node, and the second input signal 22 is a transfer command sent via the bypass connection line. . The comparator 15 and the comparator 16 respectively compare the value of the message ID register 14 with the value of the message ID field of the transfer command input from the first input signal 21 or the second input signal 22, and input the result. If the message ID is larger than the value of the message ID register 14, that is, the message I
If D is new, the control circuit 17 is notified of the first comparison signal 27 or the second comparison signal 28.

When the control circuit 17 knows that the transfer instruction having the new message ID is input by the first comparison signal 27 or the second comparison signal 28, the first selection circuit 11 receives the first transfer instruction. The selection signal 24 is output. When a transfer command with a new message ID is input,
The second selection signal 25 is sent to the second selection circuit 13 and the load signal 26 is sent to the message ID register 14.

The first input signal 21 and the second input signal 22 are input to the first selection circuit 11, which receives the first selection signal 24 from the control circuit 17 and receives the first selection signal 24. The input signal corresponding to is selected and output to the delay circuit 12. This selection is valid while the corresponding transfer instruction is being executed. The delay circuit 12 delays its input by one clock in synchronization with the CLK signal and outputs it as the output signal 23 of the selector node.

The second selection circuit 13 receives the comparison signal 25 from the control circuit 17, and the comparison signal 26 causes the first selection circuit 13 to receive the first comparison signal 25.
Of the input signal 21 or the second input signal 22 is output to the message ID register 14. The message ID register 14 receives the load signal from the control circuit 17 and stores the message ID in the signal selected by the second selection circuit 13.

FIG. 4 is a circuit diagram showing an example of the control circuit 9 in the selector node. In the figure, parts similar to those in FIG. 31 is the first
Is a decoding circuit, 32 is a second decoding circuit, 33 is a first AND gate, 34 is a second AND gate, 35 is an OR gate, and 36 is an SR flip-flop.

First and second decoding circuits 31 and 32
When a transfer command is input to the first input signal 21 and the second input signal 22 of the selector node,
Activate output. The output of the first decoding circuit 31 and the first comparison signal 27 from the first comparison circuit 15 are input to the first AND gate 33. The output of the second decoding circuit 32 and the second comparison signal 28 from the second comparison circuit 16 are input to the second AND gate 34.

The S input of the SR flip-flop 36 is
The output of the first AND gate 33 and the R input are
The outputs of the second AND gates 34 are input respectively. Therefore, as the first selection signal 24 which is the output signal of the SR flip-flop 36, the transfer instruction is input to the first input signal 21 of the selector node, and the message ID accompanying this instruction is the current message ID register 14
The output becomes active when it is newer than the value stored in. At this time, in the first selection circuit 11,
The first input signal 21 is selected. On the contrary, the transfer command is input to the second input signal 22 of the selector node, and the message ID accompanying this command is the current message I.
The output becomes inactive when it is newer than the value stored in the D register 14. At this time, the second input signal 22 is selected in the first selection circuit 11.

The output of the first AND gate 33 is directly output to the selection circuit 13 as the second selection signal 25. When the output of the first AND gate 33 is active, that is, when the transfer instruction is input to the first input signal 21 and the message ID accompanying this instruction is newer than the value currently stored in the message ID register 14. Then, the first input signal 21 is selected and the message I
It is supplied to the D register 14. On the contrary, when the output of the first AND gate 33 is inactive, the second input signal 22 is selected.

Furthermore, the output of the first AND gate 33 and the output of the second AND gate 34 are input to the OR gate 35, and the transfer instruction is sent to the first input signal 21 or the second input signal 22. When the input signal ID associated with either instruction is newer than the value currently stored in the message ID register 14, the load signal 26 is sent from the OR gate 35 to the message ID register 1
4, the message ID is fetched in the message ID register 14, and the message ID in the message ID register 14 is updated.

The configuration of the selector node shown in FIGS. 3 and 4 is an example, and other configurations may be used as long as they have the same function.

FIG. 5 is an explanatory diagram of a specific example of the operation in one embodiment of the ring bus multiprocessor device of the present invention. Reference numerals in the figure are the same as those in FIG. Here, it is assumed that the processor node 1-15 issues a transfer instruction. At this time, the route through which the transfer instruction passes is indicated by a thick line. The transfer instruction issued by the processor node 1-15 is given the latest message ID.
The transfer instruction issued by the processor node 1-15 is input to the processor node 1-16 and further transferred to the selector node 2-4.

In the selector node 2-4, the message ID of the transfer instruction transferred last time is held in the message ID register 14. The transfer command input from the processor node 1-16 has the newest message ID. This is judged by the first comparison circuit 15 of FIG.
The first comparison signal 27 is input to the control circuit 17. In the control circuit 17, the output of the first decoding circuit 31 in FIG. 4 is activated by the input of the transfer instruction from the processor node 1-16, and the first AND gate 33 is input by the input of the first comparison signal 27. Becomes active,
The first selection signal 24, the second selection signal 25, and the load signal 26 become active. Therefore, the transfer instruction from the processor node 1-16 is selected by the first selection circuit 11, passes through the delay circuit 12, and the output signal 23 is output.
At the same time, the empty transfer instruction of the processor node 1-16 is selected by the second selection circuit 13, and the message ID in the transfer instruction is held in the message ID register 14.

The output from the selector node 2-4 is input to the selector node 2-5 via the processor node 1-17 and the bypass connection line 3-5. At the selector node 2-5, the transfer command input from the selector node 2-4 via the bypass connection line 3-5 arrives first.
Since this instruction is accompanied by a new message ID, the second comparison circuit 16 in FIG. 3 detects this and the control circuit 17
The second comparison signal 28 is transmitted to the. In the control circuit 17, the second decoding circuit 32 detects the arrival of the transfer command from the bypass connection line 3-5, and the second comparison signal 28
Input activates the second AND gate 34, inactivates the first selection signal 24, which is the output of the SR flip-flop 36, and activates the load signal 26. At this point, processor node 1-2
Since the transfer command from 0 has not been input, the first AN
The output of the D gate 33 is inactive and is output as it is as the second selection signal 25. First
Selection circuit 11 selects the second input signal 22 according to the first selection signal 24, and the transfer command input via the bypass connection line 3-5 outputs the output signal 2 via the delay circuit 12.
It is output as 3. The second selection signal 13 causes the second selection circuit 13 to select the transfer command input from the bypass connection line 3-5, and the message ID in the selected transfer command.
The message ID register 14 according to the load signal 26
Loaded in. In this way, the bypass connection line 3-
The transfer command input via the selector node 5
5 is output.

The transfer instruction input to the selector node 2-5 is also input to the processor node 1-17 at the same time, and the processor nodes 1-17, 1-18, and 1 in that order.
-19, 1-20. Then, it is transferred from the processor node 1-20 to the selector node 2-5. From processor node 1-20 to selector node 2-
At the time when the transfer command is input to 5, the same transfer command has already been input and transferred via the bypass connection line 3-5 due to the delay time in each processor node. Therefore, the first comparison circuit 15 in FIG. 3 detects that the message IDs match and does not send the first comparison signal 27 to the control circuit 17. Therefore, the first and second input signals 21 and 22 are both the first selection circuit 11
The transfer instruction output from the processor node 1-20 that is not selected in step 1 is rejected without being output.

Similarly, selector nodes 2-6 and 2-6
In 2-7, 2-8, 2-1, 2-2, 2-3, bypass connection lines 3-6, 3-7, 3-8, 3-1, respectively.
3-2 and 3-3 are selected and output. The transfer instruction is also transferred to the processor nodes 1-21 to 1-32 and 1-1 to 1-14.

When a transfer instruction that has passed through the ring bus returns to the processor node 1-15, the processor node 1
-15 examines the source node ID in the transfer instruction and finds that it is an instruction issued by itself, so it discards it without sending it forward. Also, from the selector node 2-3 through the bypass connection line 3-4, the selector node 2-4
A transfer command is input to. However, since the message ID of the input transfer instruction is held in the message ID register 14 when the transfer instruction that has passed through the ring bus returns to the selector node in this way, the second comparison circuit of FIG. 16 detects a message ID match,
The second comparison signal 28 is not output. As a result, the transfer command input from the bypass connection line 3-4 is rejected without being sent first.

In the above example, the processor nodes 1-15
Has described the case where the transfer instruction is issued, the operation is performed as described above regardless of which of the other processor nodes 1-1 to 1-14 and 1-16 to 1-32 issues the chastity instruction. Instructions are transferred to each processor node.

As described above, the transfer instruction needs to be input to all the processor nodes because the transfer includes multicast and broadcast. In the case of single cast, it is not necessary to input to all processor nodes, but the circuit configuration is simplified,
Further, in order to reduce the overhead of circuits and software, it may be more efficient to always input the transfer instruction to all the processor nodes, and in the above-described embodiment, such a configuration is adopted.

In the above embodiment, the message ID is used as a means for distinguishing the transfer command in the selector node, but instead, for example, information such as a time stamp managed for each processor node is used. Any information may be used as long as the information can uniquely identify the transfer instruction.

[0041]

As is apparent from the above description, according to the present invention, it is not necessary to change the data transfer mode in each processor as in the prior art in order to determine the data transfer path, and the processor status can be changed. Independently of the above, since the data transfer path is determined by the coded information in the transfer data, more flexible and high speed data transfer can be performed. Also, the node ID and group I that have been conventionally used in the multiprocessor transfer method are used.
Since it is possible to support broadcast communication and selective broadcast communication using D, there is an effect that the efficiency of data transfer is improved.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing an embodiment of a ring bus multiprocessor device of the present invention.

FIG. 2 is an explanatory diagram showing an example of transfer instructions handled in one embodiment of the ring bus multiprocessor device of the present invention.

FIG. 3 is an internal configuration diagram showing an example of a selector node.

FIG. 4 is a circuit configuration diagram showing an example of a control circuit 9 in a selector node.

FIG. 5 is an explanatory diagram of a specific example of the operation in one embodiment of the ring bus multiprocessor device of the present invention.

FIG. 6 is a configuration diagram showing an example of a conventional multiprocessor device using a bypass connection line.

[Explanation of symbols]

1-1 to 1-32 ... Processor node, 2-1 to 2-8
... selector node, 3-1 to 3-8 ... bypass connection line,
11 ... First selection circuit, 12 ... Delay circuit, 13 ... Second selection circuit, 14 ... Message ID register, 15 ... First
Comparing circuit, 16 ... Second comparing circuit, 17 ... Control circuit,
21 ... 1st input signal line, 22 ... 2nd input signal, 23
... output signal, 24 ... first selection signal, 25 ... second selection signal, 26 ... load signal, 27 ... first comparison signal, 28
... second comparison signal, 31 ... first decoding circuit, 32 ...
Second decode circuit 33 ... First AND gate 34
... second AND gate, 35 ... OR gate, 36 ... SR
flip flop.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Nobuaki Miyagawa 2274 Hongo, Ebina City, Kanagawa Prefecture Fuji Xerox Co., Ltd. (72) Reiji Aihara 1-4-2, Kagamiyama, Higashi Hiroshima City, Hiroshima Prefecture 72 ) Inventor Mitsumasa Koyanagi Aoba, Aoba-ku, Sendai City, Miyagi Prefecture, Aoba (No house number), Tohoku University

Claims (2)

[Claims] 1. A plurality of processors coupled by a ring bus for outputting transfer data, one or more bypass connection lines arranged in parallel with some of the processors and having one end connected to the ring bus, and an output of the processor. Line and the bypass connection line as input, and one or more selection means for selecting and outputting the output line of the processor or the bypass connection line based on predetermined information contained in the transfer data. Ringbus multiprocessor device. 2. Each processor adds a message ID indicating the order of issue of transfer instructions for sending out new transfer data unique to the entire device to the output transfer data, and outputs the transfer data. A message ID register for storing the message ID, a first comparator for comparing the content of the message ID register with the ID message in the transfer data output from the processor at the previous stage, the content of the message ID register and the bypass A second comparator for comparing the ID message in the transfer data input from the connection line, a selection circuit for selecting one of the bypass connection line and the output of the processor, the first comparator and the first comparator. Control means for controlling the update of the message ID register and the selection in the selection circuit based on the output of the second comparator. The ring bus multiprocessor device according to claim 1, wherein: