JPH07107680B2 - Interprocessor data transfer device for parallel processor - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a particularly efficient inter-processor data transfer device for a parallel processor composed of a plurality of processors.

[Conventional technology]

In a parallel processor composed of multiple processors, a message transfer method is known as a data transfer method between processors, in which a message is composed by combining destination information such as a destination processor number and data to be transferred, and the message is transferred. ing. Here, the data to be transferred means data in a broad sense, and is all except the destination information in the message (for example, including tag information, data identification information, etc.).

As the message format, for example, a hardware design of sigma 1, a dataflow computer for scientific scientists computer comprehensions, proceedings ICP (1984), pages 524 to 531 (A hardware design
of Sigma-1, A Data-flow computer for scientific com
putations, Proc. ICPP, 524-531, 1984), page 525.

The message transfer method actively moves toward the transfer destination processor on the transfer path between the processors based on the transfer destination information that the message itself has. Therefore, the message transfer method is an effective method in which the arithmetic processing on the processors and the message transfer between the processors can be independently performed, and thus the transfer processing can be omitted.

Further, generally, the transfer path between the processors is provided with redundancy in terms of reliability or efficiency. That is,
A plurality of routes are prepared without uniquely defining the route on the transfer route to the destination processor.

[Problems to be solved by the invention]

In the above-mentioned conventional technique, all the messages are composed of the sender processor, and the transfer route only sends the message to the destination processor based on the destination information in the message.

Therefore, it is not considered to add the information generated in the transfer route to the message, and the information that the sender processor cannot incorporate into the message (for example, the transfer route has redundancy, that is, there are multiple routes through which the message can pass,
The route information of the message when it is dynamically determined which route to take, or the number of times the message was forced to wait when the route conflicted with other messages during the network)
It was impossible to inform the destination processor of the message.

The object of the invention is to allow adding new information to a message in the transfer path.

[Means for Solving Problems] In order to achieve the above object, the transfer path is configured by a multi-stage switch module, and the message indicates whether the message is from which processor or which switch module. With the transfer route information shown,
Each switch module is provided with means for adding, when a message is input, information indicating that the message has passed through the switch module to the transfer route information of the message. Further, the message also includes transfer route information indicating that the message conflicts with another message, and each switch module updates the transfer route information indicating that the message conflicts when the message conflicts with another message. It is equipped with.

Specifically, as the transfer route information, (1) the input position when the message is input to the switch module, or (2) information such as the waiting time when the switch module waits due to message competition. There is.

The above example (1) is used when the transfer path has redundancy. When the source processor composes a message from the destination processor number + transfer data and sends this message to the transfer route, the message sent from the transfer route to the destination processor is output as dynamic route information added. .

In the above example (2), the competition occurs in the switch module and the waiting time is written in the message. Therefore, when the competition occurs again in the switch module after that, the priority of the message is determined based on this waiting time. can do.

[Action]

In a message passing through a transfer route having a redundant route, the means for replacing the destination information such as the destination processor number in the transfer route with the transfer route information operates after the route through which the message passes is determined. Therefore, the message reaches the destination processor without hesitation on the transfer route, and at that time, the message obtains the route information that has passed through instead of the unnecessary information of the destination processor.

Also, when waiting occurs due to competition of messages in the switch module, the number of times of waiting increases, so that the priority becomes high, and when the next competition occurs, it is easier to pass preferentially.

〔Example〕

 An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is an embodiment of a parallel processor system in which processors are connected by a redundant transfer path (having a plurality of paths) according to the present invention. 1-1 to 1 in the figure
-4 is a processor that executes instructions independently,
Reference numeral 2 denotes a message transfer path between processors, which is composed of a plurality of switch modules 2-1 to 2-6.
10 to l25 are message transfer routes, and l30 to l45 are busy signal lines for stopping the message transmission in the previous stage when message competition occurs in the switch module and a message wait occurs. 3 to 6
Is a destination processor number field, a data field containing data and transfer information (for example, an identifier of the transfer data, a command to the transfer destination processor, a storage destination of the transfer data in the transfer destination processor), a field holding the transfer path, and (Waiting) An inter-processor transfer message (hereinafter abbreviated as message) composed of a field holding count data.

The processor numbers are shown in binary for convenience. Further, the processor on the data transmitting side and the processor on the data receiving side are shown separately, but the substance is the same.

In the parallel processor of this embodiment, four processors are assumed, but the number of processors may be any number. Also,
The switch module constituting the inter-processor transfer path 2 is assumed to have 2 inputs and 2 outputs, but a switch module having n inputs and n outputs (n2) may be used.
Further, although one redundant stage is provided, the redundant stage may not be provided, and conversely, more multiple stages may be provided.

As a specific example, consider the case where a message is sent from processor # 00 to processor # 11.

First, the message 3 is constructed in the processor # 00 1-1. The address field 3-1 of the message 3 consists of 2 bits (because there are 4 processors),
Binary number 11 is set. Data to be transferred and transfer information are set in the data field 3-2. The route field 3-3 secures 3 bits including the redundant stage. The count data field 3-4 is set to 0.

From switch module 2-1 to l30 unless a busy signal comes in, switch module 2 to 10
Send message 3 to -1.

Here, the general operation specifications of the switch modules 2-1 to 2-6 are shown. Each switch module performs switching with an address of 1 bit. Redundant stages 2-1 to 2
2 is an arbitrary address, the second stage 2-3 to 2-4 uses the upper bit of the in-message address field, and the third stage 2-5 to 2-6 uses the lower bit of the in-message address field as the switch information. . Whether the switch module uses the upper bits of the address field, the lower bits, or neither of them is set in each switch module which is determined when the parallel processor system is configured.

When the message 3 is sent to the switch module 2-1 as in the present embodiment, since the switch module 2-1 is a redundant stage, there is no switching information and it is output to an output destination without contention. In the present embodiment, it is output to 15. At this time, since the message 3 is input from 10,
0 is written in the first bit of the path field 4-3. Further, since this switch module is a redundant stage, contention does not occur, and the count data field 4-4 remains 0.

Message 4 above 15 is the input of switch module 2-4. This time, the upper bit of the address field 4-1 is used as the switching information. As a result, message 5 is output on l21. At this time, since the message 4 is an input from 15, 0 is written in the second bit of the path field 5-3. If a message is sent from the other input at the same time with this switch module and the output destinations match and the message from 15 is in a waiting state, the count data field 5-4
Becomes 1. Then, it is sent to l21 at the next timing.

Message 5 on l21 is input to switch module 2-6. This time, the lower bit of the address field 6-1 is used as the switching information. As a result, message 6 is output on l25. At this time, since the message 5 is an input from l21, 1 is written in the third bit of the path field 6-3. In addition, even if a message is sent from the other input at the same time with this switch module and the output destinations match, the input message from l21 is put in the waiting state once in the previous stage, and the count data field 6-4 counts. Since the data is 1, it is sent to l25 with priority. Of course, if the value of the count data in the message from the other is 2 or more, l21
The input message from is placed in a waiting state, the count data is counted up from 1 to 2, and is sent to l25 at the next timing.

The message on l25 is taken up by processor # 11 1-4. At this time, the route field 6-3 is 001, and the passing switch module can be discriminated. In addition, the count data field shows the number of times a wait occurred due to message competition.

Next, the details of the switch module will be described with reference to FIG.

In the figure, 7 to 8 are message input registers, 50 to 51 are decoders, 52 is an address bit instruction for instructing a bit to cut out from an address field, and 53 to 54.
Is an incrementer, 55 is a comparator, 58 to 59 are NOT gates, 62 to 63 are OR gates, 56 is a brightness information generation circuit, 64, 65 to 90 are selectors, and 68 to 69 are message outputs. Registers 66 and 67 are input registers for busy signals.

The messages fetched from 19 to l21 are stored in the input registers 7 to 8. During the message, the address fields 7-1 to 8-1 are transferred to the decoder 50 to
Send to 51. At this time, the address bit instruction 52 knows that the switching of the switch modules 2-6 uses the lower bit of the address field, and instructs the decoder to decode the target bit.

In addition, the messages on registers 7-8 are sent to selectors 64-65, respectively. The information decoded by the decoders 50 to 51 is sent to the message selection circuits 60 to 61 via l72, l74 and l73, l75. The message selection circuits 60 to 61 also include input registers 66 to
Priority information is input information via the busy signal coming through 67 or l83.

The message selection circuit 60 selects which of the messages in the input registers 7 to 8 is to be output, and sends it to the next 2 × 2 switch or transfer destination processor via the output register 68, l24. To decide.

First, the output a indicates which message of the input registers 7 to 8 is selected, and controls the selector 64. Write part of the path field 68-3 in the message on the output register. The output b ₀ or b ₁ is then set when a busy signal comes from l44 or when there is contention in the transfer of a message, and the input register 7 or 8
Make the above message wait. This busy signal activates the incrementers 53 to 54 and counts up the values of the counter data fields 7-4 to 8-4 by one count.

Here, generation of priority information will be described.

First, the count data fields 7-4 and 8-4 in the input registers 7 and 8 are sent to the comparator 55. If either one is larger, that information is used as priority information and the message selection circuit is operated via selectors 90 to 91.
Send to 60 to 61. If the values of the count data fields match, the information generated by the priority generation circuit 56 is sent to the message selection circuits 60 to 61 via the selectors 90 to 91. Priority generation circuit 56
Is composed of a register 57 and a NOT circuit 58, and is configured so that the cycle priority changes.

〔The invention's effect〕

According to the present invention, new information can be added to a message within the transfer path. By using this invention, for example, the following effects can be obtained. It is possible to notify the destination processor of the transfer route information through which the message has passed. As the transfer route information, (1) information indicating which route has been passed when the transfer route has redundancy, that is, has a plurality of routes, and (2) information that has been waited for once on another message on the transfer route. Time waiting information,
(3) When a message makes an error detection / correction on the transfer route, its position in the transfer route may be considered and used as data for improving the performance or reliability of the transfer route by using these information. To use.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel processor, and FIG. 2 is a transfer path selection circuit. 1-1 to 1-4 ... Processor, 2-1 to 2-
4 …… 2 inputs and 2 outputs switch module, 60 to 61…
... Message selection circuit, 63 ... Priority information generation circuit, 2 ... Transfer path.

Claims (2)

[Claims] 1. An interprocessor data transfer device for a parallel processor, comprising: a plurality of processors and a plurality of the processors, and a transfer path for transferring a message including a transfer destination processor number and data to be transferred. The transfer path includes a multi-stage switch module, and the message includes transfer path information indicating which processor or which switch module the message is from, and each switch module receives the message. An interprocessor data transfer device of a parallel processor, characterized by further comprising means for adding information indicating that the switch module has been passed to the transfer path information of the message. 2. An interprocessor data transfer device of a parallel processor, comprising a plurality of processors and a plurality of said processors, and a transfer path for transferring a message including a processor number and a data to be transferred to a transfer destination, The transfer route includes a multi-stage switch module, and the message conflicts with other messages and first transfer route information indicating which processor or which switch module the message is from. Each of the switch modules includes means for adding information indicating that the message has passed through the switch module to the first transfer path information of the message when the message is input. , If the above message conflicts with other messages, Data transfer device between the processors of a parallel processor, characterized in that it comprises means for updating the second transfer path information.