JPH0944447A - Interface circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To preferentially process even a command transferred later by providing a means for reading the commands/data from a buffer for queuing the commands in a reverse order. SOLUTION: A CPU 107 receives and takes out the data of a fixed length at the head of the command and takes out and receives remaining command length information. The CPU 107 analyzes the command, counts a data amount and takes it out. It is assumed that the commands/the data transferred from an interface 101 are automatically queued in FIFO. In this case, they are not queued in the FIFO and the command to be preferentially processed is defined as a preferentially processing command. Information transferred first immediately after reset is defined as the command and the CPU 107 takes out the command from a queue and checks it. Then, whether or not it is the preferentially processing command is judged, and in the case of the preferentially processing command, a command processing is started as it is when data transfer is not required and it is processed before the commands already in the queue.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit of a device connected to a host computer, and more particularly to a mechanism for preferentially processing a received command.

[0002]

2. Description of the Related Art FIG. 15 shows a conventional example of the interface circuit configuration of a device connected to a host computer (hereinafter, also simply referred to as a host). In this conventional example, a printer is assumed as the device. 101 is an interface circuit connected to the host, which is at the physical level,
Control the interface protocol. Here, it is assumed that the interface protocol cannot distinguish the data / command of the transfer information from the host. That is, the transfer information from the host is simply received by the device as "data" on the interface, and the data / command is distinguished in the subsequent processing. The information transferred from the host is accessed from the access control logic 10 by the operation of the transfer logic 102 from the interface circuit 101.
3 is stored in the RAM 104. I is provided between the interface circuit 101 and the access control logic 103.
/ FBus (interface bus). When information is transferred from the host to the interface circuit 101, a transfer request is sent to the transfer logic 102, and the transfer logic 102 receives the request and writes the information in the interface circuit to the access control logic. This processing is performed at high speed by hardware logic and does not require software processing by a CPU or the like. Access control logic 1
03 converts the control signal of the transfer logic into the access signal of the RAM 104 and writes the information.

The CPU 107 operates according to the contents of the program ROM 108 and controls various devices. Whether or not information is transferred from the host is regularly input to the RAM 10
Check 4 and do. Immediately after the reset state, the CPU
107 assumes that the information from the host is a command,
Check its effectiveness. If it is valid, the corresponding process is performed. At this time, if the command is accompanied by data, the information following the command is received as data,
The command is processed.

When the data is the print data of the printer, the DMAC (DMA controller) 109 DMAs the data from the RAM 104 to the printer engine 110.
(Direct memory access) Transfer. RAM1
04 is a buffer of transfer information from the interface,
The access control logic 103 has both functions of the work area of the CPU 107, and the access control logic 103 is an I / FB bus to the RAM 104.
And arbitration of access from both CPU Bus.

As described above, the information transferred from the host is once stored in the RAM 104, and then the CPU 107
However, the access control logic controls this buffer area like a FIFO (First In First Out). That is, the transfer logic transfers the information from the interface circuit 101 to the FIFO.
Is transferred to the FIFO, and the CPU 107 transfers the FIFO.
The information is read from and processed in the order in which it was transferred. This F
The IFO capacity is the access control logic 103 and the CPU 10
It is configured to be different from the work area of No. 7. Further, with such a configuration, the CPU can sequentially process the information without having to manage the buffer address of the RAM 104.

[0006]

However, the above-mentioned conventional example has the following problems. The command / data transferred from the host is put into a buffer as it is and queued, and then is asynchronously read and processed by the CPU. Since this buffer has a FIFO structure, the CPU performs processing in the order in which it arrives first, but it may take some time for processing due to some trouble. In this state, commands that arrive later will continue to be queued in the FIFO, and the time to execute the processing becomes uncertain. That is, if a command such as device reset or cancellation of a command being executed is received, it may be uncertain when the command will be executed.

Even if the information in the FIFO is taken out in reverse order, the interface does not distinguish between data and command, so it cannot distinguish whether it is command or data. Therefore, the interface circuit cannot fundamentally notify the CPU of the reception of the command by means such as an interrupt.

Therefore, an object of the present invention is to identify the information of the command included in the information even if the interface cannot distinguish the command / data of the information, and the CPU
The notification is sent to the user and priority processing can be performed if necessary.

[0009]

In order to achieve the above object, the present invention detects the completion of command transfer and the completion of data transfer associated with the command from the transfer information consisting of a single data stream from the interface circuit. By providing a means, a transfer stopping means for stopping the operation at the time of this detection, a means for notifying the CPU of the transfer completion, and a means for reading the command / data from the buffer for queuing the command in reverse order, Even if there is, priority processing is possible.

As a transfer completion identifying means for this command,
A transfer information counting means is provided to notify the CPU of the completion of transfer of a predetermined count number as the transfer sequence starts from a command, and the counter is reset based on the information amount of the remaining command included in the transfer sequence to complete the transfer of the command. It is characterized by detecting.

Alternatively, a command end code (delimiter) detection circuit is provided as the transfer completion identifying means for the command, the transfer sequence starts from a command, the delimiter is detected, and this is notified to the CPU. .

As a data transfer completion identifying means, a transfer information counting means is provided to count and detect the amount of data contained in the command.

A means for holding the transfer mode is provided, a priority processing / non-priority processing mode is provided in the command / data transfer mode, and the data transfer mode. When data transfer is completed in the non-priority processing mode of the data mode, the CPU is notified. The feature is that the mode shifts to the command mode without notifying. As a result, it becomes possible to efficiently perform the standardized processing without depending on the CPU.

[0014]

EXAMPLES Next, examples of the present invention will be described.

(Embodiment 1) Embodiment 1 of the present invention is shown in FIG. The same components as those of the conventional example described above are indicated by the same numbers. Reference numeral 101 is an interface circuit that is connected to a host machine (not shown) to transfer information, 102 is a transfer logic that controls signals for information transfer, and 103 is R
It is an access control logic that controls access to the AM 104. It is assumed here that the interface does not distinguish data / command on the protocol. RA
I / FB of the interface circuit 101 side is provided in M104.
Since both us and CPUBus on the side of the CPU 107 access, the access control logic 103 performs the arbitration. A counter 105 counts the amount of transfer information, and counts down every transfer of the interface circuit 101. That is, the remaining amount of information is retained. The transfer stop logic 106 detects that the counter 105 is 0, stops the transfer logic 102, and causes the CPU 107 to generate an interrupt in accordance with the operation mode. CPU10
7 detects the completion of data or command transfer by this interrupt, and R via the access control logic 103.
Information is retrieved from the AM 104 and processed. 108 is C
The program ROM of the PU 107, 109 is a DMA controller, and 110 is a printer engine.

A configuration example of the transfer stop logic 106 is shown in FIG. The stop determination circuit 201 detects the counter = 0 and the operation mode, gives an instruction to stop the transfer, and generates an interrupt to the CPU. At this time, the contents of the load register 204 are loaded into the counter 105 by the counter loader 203 as needed. The CPU 107 can set a value in the load register 204 via the CPUBus or load the value in the counter 105 by the counter log 203. A mode holding circuit 202 switches the operation algorithm according to the mode. This mode information may be referenced or changed by the stop determination circuit 201 depending on the operation sequence, or may be referenced or changed by the CPU 107 by software processing.

A configuration example of the access control logic 103 is shown in FIG. The function of the access control logic is to perform access arbitration on the I / FBus side and the CPUBus side as described above, and to cause part of the RAM 104 to function as a buffer for transfer information from the interface. Specifically, this is to function as a FIFO using the input / output pointer. As a result, the command / data transferred from the interface will be queued in this FIFO. RAM address is CPU
It is assumed to be in the address space.

The core of the operation is the arbiter 701.
/ RA for arbitrating control signals of both FBus and CPUBus
It is operated as a control signal for M104. Input pointer 7
02 is a write address of the FIFO, and an output pointer 70
3 generates a read address. The buffer state detection circuit 704 compares the values of the pointers 702 and 703 and F
Determine if the IFO is full, free, or empty. RA
There are the following modes to access M. (1) Write from I / FBus Access with input pointer and increment input pointer after access (2) FIFO read from CPUBus Access with output pointer and increment output pointer after access (3) Reverse FIFO read from CPU Access by decrementing the input pointer (4) Write from FIFO by CPU Access with input pointer, increment input pointer after access (5) Normal access from CPU Directly access RAM by CPU address and affect input / output pointer do not do.

The operation switching at the time of access from these CPUs can be realized by mapping a part other than the normal access (5) as a part of the RAM address or a port other than the RAM address as a separate port and switching the operation by the decoder 707. The switches 705 and 706 switch the bus connected to the RAM 104 according to these modes. This switching is performed according to the output of the decoder 707.
1 does.

Next, the basic flow of information will be described with reference to FIG. FIG. 3 shows a summary of both software and hardware processing. After reset, the host starts the transfer from the command. The information transferred by the host is a command and data associated with the command. Therefore, the transfer content is a combination of command M (no data) or command N + command N data.

It is assumed that the command includes a fixed length, or a length determined from the beginning, which includes information capable of determining the remaining data amount. The CPU first receives and fetches the fixed length data of the command, extracts the remaining command length information from this, and receives it (S301). By this operation, the entire command can be taken out by counting the transfer information. As for the data amount, the information of the data amount is included in the command. This allows the CPU to analyze the command, count the amount of data, and take out the command. The command / data transferred from the interface shall be automatically queued in the FIFO as described above. Here, a command that is desired to be preferentially processed without being queued in the FIFO is called a priority processing command.

Immediately after reset, the information transferred first is a command. The CPU takes out this command from the queue and checks it (S302). This reading may be performed by reading in the reverse order of the FIFO, or by directly accessing the RAM address space and reading. next,
It is determined whether the command is a priority processing command (S303),
If this is not a priority processing command, it is returned to the FIFO queue (S308). If this command involves data transfer, information on the amount of data contained in the command is received and queued (S310). After that, it returns to command reception again.

In the case of the priority processing command, if the data transfer is not required, the command processing is directly performed (S30
7), the processing is performed before the command queued first. When data transfer is involved, after the transfer of the amount of data described in the command is completed, the data is taken out from the queue as in the case of the command (S306), and command processing is performed. After this, the process returns to command reception again.

The processing of the priority processing command described with reference to FIG. 3 is executed in synchronization with the command / data input / output. On the other hand, the normal command processing is executed as another task for reading the FIFO asynchronously with the processing on the interface side, as shown in FIG. Therefore, if the queue is busy, the execution time will be uncertain.

Further detailed transfer stop logic 106 and the algorithm of the CPU synchronized therewith will be described with reference to FIGS.

First, the transfer operation mode will be described. The operation modes are first classified into command modes and data modes. The command mode is a command transfer mode, and the data mode is a data transfer mode. Apart from this, there is a priority flag. This holds a mode relating to information transfer which is preferentially processed in each command / data mode. These are held in the mode holding circuit 202 of FIG.

The operation algorithm of the transfer stop logic 106 will be described with reference to FIG. Immediately after reset, the mode becomes the priority flag negate and command mode (S501, S
502). After that, the contents of the load register 204 are loaded into the counter 105 by the counter loader 203 (S50
3) Release the transfer stop and transfer (S504). At this time, the contents of the load register 204 are set in advance so that the CPU 1
07 shall be set. When a predetermined amount of information is transferred from the host, the counter 105 becomes 0 and the transfer is stopped (S505, S506). At this time, if the command mode or the priority flag is asserted (S50
7, S510), an interrupt is generated for the CPU 107 (S508), and a loop is waited for the CPU 107 to issue a transfer stop release request (S509).

If the data mode is in effect when the transfer is stopped and the priority flag is negate, it is determined that the priority processing is not necessary, the mode is returned to the command mode and the reception of the beginning of the command is started. The CPU 107 processes the transfer contents check and processing in response to the occurrence of the interrupt in S508. At this time, the CPU 107 performs the processing of the mode, the priority flag, and the next transfer information amount set as needed. When the CPU 107 issues a transfer stop release request, the transfer stop logic 106 loads the load register into the counter again and waits for the completion of information reception.

The algorithm of the interrupt processing of the CPU 107 will be described with reference to FIG. First, the interrupt request from the transfer stop logic 106 is negated (S601), and the transfer content is taken out from the queued buffer (S60).
2). The operation of taking out from the buffer is the input pointer 702.
Includes the operation of returning to before receiving the information. At this time, if it is the command mode (S603), it is checked that the transfer content is a command (S604). At this time, if the command transfer is not completed, the transfer amount of the remaining part of the command is calculated from the information received just now to the load register 204.
Is set (S618), a transfer stop cancellation request is issued (S611), and the interrupt processing is ended. There are the following four operations when the command transfer is completed. (1) Priority command and no data transfer Command processing is immediately performed (S615). The next command transfer amount is set in the load register 204 (S61
7) Then, a transfer stop cancellation request is issued (S611), and the process ends. (2) Priority command and data transfer present The priority flag is asserted (S608) and the data mode is entered (S609). The next data transfer amount is set in the load register 204 (S610), a transfer stop cancellation request is issued (S611), and the process ends. (3) A non-priority command and no data transfer command is returned to the queue, the next command transfer amount is set in the load register 204 (S617), a transfer stop cancellation request is issued (S611), and the process ends. (4) Non-priority command and data transfer enabled Enter data mode (S609). The next data transfer amount is set in the load register 204 (S610), a transfer stop cancellation request is issued (S611), and the process ends.

The priority flag is always asserted when the interrupt processing is in the data mode. This is because no interrupt is generated in the data mode and the priority flag negate as shown in the algorithm of FIG.

In this case, the CPU 107 sets the mode to the command mode for receiving the command and processes the command using the data. After that, the priority flag is negated, the next command transfer amount is set in the load register 204, a transfer stop cancellation request is issued, and the process ends. By the operation described above, it is possible to generate an interrupt to the CPU when the transfer of the data accompanying the command and the command for performing the priority processing is completed, and to perform the priority processing.

(Embodiment 2) Embodiment 2 of the present invention is shown in FIG. FIG. 8 is a circuit block diagram of the transfer stop logic 106 of the second embodiment, and the same components as those of FIG. 2 are indicated by the same numbers. In the first embodiment, the completion of command transfer is detected by counting with the counter 105, but in the second embodiment, it is assumed that the command has an indefinite length and thereafter is separated by a specific code (delimiter). A command buffer 801 and a delimiter check circuit 802 detect a delimiter in the command mode. As the transfer stop signal, the switch 803 switches between the stop determination circuit 201 and the signal from the delimiter check circuit according to the mode. Basically, the delimiter check is performed in the command mode, and the transfer is stopped with the counter = 0 in the data mode.

The operation algorithm of the transfer stop logic 106 will be described with reference to FIG. Immediately after reset, the priority flag is negated (S901), and the command mode is entered (S90).
2) The transfer stop is released (S903). In this state, a loop for detecting a delimiter in the transfer information is entered (S90
4). When the delimiter is detected, it is determined that the command transfer is completed, transfer is stopped (S905), and an interrupt is generated in the CPU 107 (S906). When the transfer stop release request is issued by processing the mode and priority flags in the interrupt processing (S
907), the mode is checked (S908), and if it is the command mode, the command transfer completion waiting state is entered again. When the data mode is designated in the interrupt processing, the load register 204 is set to the counter 1 by the counter loader 203.
05 is loaded (S910) and the transfer stop is released (S
911). In the data mode, counter = 0 is detected (S912), and a transfer stop signal is generated (S91).
3), the priority flag is checked (S914). If it is asserted, since the data transfer of the priority command is completed, an interrupt is generated after the transfer is stopped (S90
5, S906). If the gate is negated, the next command mode is entered with the data queued (S902), and the command transfer completion waiting state is resumed.

The interrupt processing algorithm of the CPU 107 will be described with reference to FIG. Cancel interrupt request (S10
After 01), it is checked whether or not it is the command mode (S1002), and if it is the command mode, the transfer contents are taken out from the command buffer 801 (S1003) and checked (S1004). The processing contents are classified as follows. Here, the correction of the input pointer is to correct the input pointer 702 in the access control logic 103 and return it to the state before the command transfer. (1) Priority command and no data transfer After input pointer correction (S1006), command processing is performed immediately (S1015). After that, a transfer stop cancellation request is issued (S1011) and the process ends. (2) With priority command and data transfer After input pointer correction (S1006), the priority flag is asserted (S1008) and the data mode is entered (S100).
9). The next data transfer amount is set in the load register 204 (S1010), and a transfer stop release request is issued (S1).
011) Finish. (3) Non-priority command and no data transfer Immediately, a transfer stop cancellation request is issued (S1011) and the process ends. (4) Non-priority command and data transfer available Enter data mode (S1009). The next data transfer amount is set in the load register 204 (S1010),
A transfer stop cancellation request is issued (S1011), and the process ends.

When it is checked in step S1002 whether it is the command mode or not, if the mode is the data mode, the data is taken out from the FIFO in the RAM 104 (S1013). This also includes input pointer modification. This data is the data of the priority processing command, and the priority flag is asserted. Return to the command mode (S1014), and process the priority command (S101).
5). After this, the priority flag is negated (S101
6) Then, a transfer stop cancellation request is issued (S1011), and the process ends. With the configuration described above, it is possible to detect a priority command and perform priority processing even if the command has an indefinite length.

(Embodiment 3) Embodiment 3 of the present invention is shown in FIG. FIG. 11 shows a configuration example of the transfer stop logic 106 and the access control logic 103, and the same configuration examples as those in FIGS. 2, 7, and 8 indicate the same numbers. The feature of this embodiment is that it has a priority command check circuit 1101 and an input pointer save register 1102, controls the input pointer by the input pointer control signal generated from the input pointer save register 1102, and the CPU 107, and corrects the input pointer when processing the priority command. It is to do it automatically.

In this embodiment, the same command format as in the first embodiment is assumed, and it is assumed that the fixed length or the length determined from the beginning includes information that can determine the remaining data amount. Further, it is assumed that the fixed length or the set length includes information indicating that the command is a priority processing command.

Priority command pattern check circuit 110
1 detects the priority command pattern in the command mode, and when the transfer is stopped, the input pointer save register 1102
Is restored to the input pointer 702 to restore the state before the command transfer. The command itself is the command buffer 80
1 is read by the CPU and processed.

The algorithm of the transfer stop logic 106 is shown in FIG. This is a modification of the algorithm of FIG. 5 with an operation for the input pointer save register. After reset, the priority flag is negated (S1201), the command mode (S1202), the content of the input pointer 702 is saved in the input pointer save register 1101 (S1203),
The contents of the load register 204 are loaded into the counter 105 (S1204), and the transfer stop is released (S120
5) Enter a command transfer waiting loop (S1206).
When the counter = 0, the transfer is stopped (S1207) and the priority flag is checked (S1208). If it is asserted, the priority command or the data transfer of the priority command is completed, so the input pointer save register 1101 is restored to the input pointer (S1212), and an interrupt is generated (S1213). As a result, the CPU does not need the processing of the input pointer in the interrupt processing. When a transfer stop cancellation request is generated (S1214), the contents of the input pointer are saved in the input pointer save register at that time (S1203), and the command or data reception process is performed.

In summary, if the priority flag after transfer is negated, the following processing is roughly performed. (1) Command mode and priority command detection The front end of the command is received, and since it is detected that the command is a priority command, the priority flag is asserted, the contents of the input pointer save register are restored to the input pointer, and an interrupt is generated. (2) Command mode and non-priority command non-detection A non-priority command is received and an interrupt is generated as it is. (3) Data mode After the data reception of the non-priority command is completed, the next command reception process starts.

In the first embodiment, the priority flag is asserted only during the data transfer of the priority command, but in the present embodiment, if it is detected that the priority command is received after the head portion of each command is received, the command is detected. The remaining commands are received in the mode and with the priority flag asserted. The interrupt processing on the CPU side is almost the same as in FIG. However, S606
The priority flag command check is replaced with the priority flag check, and the command is read from the command buffer 801 instead of the FIFO of the RAM 104.
It is not necessary to return the command to the buffer. As described above, in this embodiment, the specific pattern at the beginning of the command is detected, the priority processing command is identified, and the access control circuit 1
Since the input pointer 702 of No. 03 is controlled, the FIFO pointer processing becomes unnecessary even when the CPU processes the priority command.

(Embodiment 4) Embodiment 4 of the present invention is shown in FIG. FIG. 13 shows an example of the configuration of the transfer stop logic 106, and the same elements as those in FIGS. 2, 8 and 11 have the same numbers. In this embodiment, a priority command pattern check circuit 1101 is added to the configuration example of FIG. 8 which is the configuration example of the second embodiment, and even when a command delimited by delimiters is used, the FIFO is processed at the time of processing of the priority processing command.
The feature is that the input pointer is restored automatically.

In this embodiment, as in the second embodiment, the command has an indefinite length, and the rear end is separated by a specific code (delimiter). The delimiter check circuit 802 generates a transfer stop signal when the delimiter is detected in the command mode, but the priority command pattern check circuit 1101 outputs the input pointer control signal when the delimiter of the command is detected when the pattern of the priority processing command is detected. It is operated to control the input pointer save register of the input pointer 702.

The algorithm of the transfer stop logic 106 is shown in FIG. FIG. 14 shows an addition of the input pointer save operation and the priority command detection operation to the algorithm of FIG. The operations of steps S1401 to S1406 are the same as those of FIG. 12 of the third embodiment. After that, when the priority command pattern check circuit 1101 detects a priority processing command, the priority flag is asserted (S1408), the contents of the input pointer save register 1102 are restored to the input pointer 702 (S1409), and the priority processing command before reception is received. Return to the value and generate an interrupt (S14
10).

After the transfer stop cancellation request is issued from the CPU 107 (S1411), in the command mode (S1).
412) and returns to the next command input process. In the data mode, the contents of the load register 204 are counted by the counter 105.
(S1413) and cancel the transfer stop (S1413).
14) Enter a counter = 0 (data transfer completion) waiting loop (S1415). If the data transfer completion priority flag is asserted (S1417), the contents of the input pointer save register 1102 are restored to the input pointer 702 (S1409), the value before the priority processing command transfer is restored, and an interrupt is generated. If the priority flag is negate, the process returns to the reception process of the next command.

The interrupt processing on the CPU side is almost the same as in FIG. However, the priority processing command check in step S1005 is replaced with the priority flag check, and the input pointer correction operation in step S1006 is unnecessary. As described above, in the present embodiment, the priority processing command is identified by the delimiter-delimited command and the input pointer 7 of the access control circuit 103 is identified.
02 is controlled, the FIFO pointer processing is not required even when the CPU processes the priority command.

[0047]

As described above, according to the present invention, even in a device having an interface that handles information as a single data stream, a command can be identified from commands / data continuously sent from a host. It becomes possible to take out the command and data to be preferentially processed without being put in the queue. Further, the command format may be fixed length, an indefinite length having command length information inside the command, or an indefinite length separated by a delimiter.

[Brief description of drawings]

FIG. 1 is a configuration example of a transfer stop logic according to a first embodiment of the present invention.

FIG. 2 is a configuration example of a transfer stop logic according to the second embodiment of the present invention.

FIG. 3 is a basic algorithm of command / data reception processing.

FIG. 4 is a basic algorithm of normal command processing.

FIG. 5 is an operation algorithm of a transfer stop logic in the first embodiment.

FIG. 6 is a CPU interrupt processing algorithm according to the first embodiment.

FIG. 7 is a configuration example of an access control logic according to the first embodiment.

FIG. 8 is a configuration example of a transfer stop logic according to the second embodiment.

FIG. 9 is an operation algorithm of a transfer stop logic according to the second embodiment.

FIG. 10 is a CPU interrupt processing algorithm according to the second embodiment.

FIG. 11 is a configuration example of a transfer stop logic and an access control logic according to the third embodiment.

FIG. 12 is an operation algorithm of a transfer stop logic according to the third embodiment.

FIG. 13 is a configuration example of a transfer stop logic according to the fourth embodiment.

FIG. 14 is an operation algorithm of a transfer stop logic according to the fourth embodiment.

FIG. 15 is a configuration diagram of a conventional example.

[Explanation of symbols]

 101 Interface Circuit 102 Transfer Logic 103 Access Control Logic 104 RAM 105 Counter 106 Transfer Stop Logic 107 CPU 108 ROM 109 DMA Controller 110 Printer Engine 201 Transfer Stop Circuit 202 Mode Holding Circuit 203 Counter Loader 204 Load Register 701 Arbiter 702 Input Pointer 703 Output Pointer 704 buffer state detection circuit 705 data bus changeover switch 706 address bus changeover switch 801 command buffer 802 delimiter check circuit 803 transfer stop signal changeover switch 1101 priority command pattern check circuit 1102 input pointer save register

Claims (6)

[Claims] 1. In an interface circuit arranged between a host computer and a controlled device controlled by the host computer, (A) the interface does not distinguish transfer information from command and data, It is handled as a stream, and (B) between the interface circuit and the buffer is a hardware transfer logic CPU
Data is transferred without intervention, (C) the host computer transfers commands and commands and their accompanying data to the device continuously, and (D) buffer is a FIFO.
Commands / data having a structure and transferred from the host computer are queued in this, and (E) C
PU is F asynchronous with the information transfer from the host computer.
It is configured to read information from a buffer having an IFO structure in the order of transfer, and the information to be transferred now or next is identification information holding means for holding identification information of command / data, and the identification information is priority information. The judgment holding means for judging and holding whether or not there is, the command transfer completion detecting means for detecting the command transfer completion from the host computer, the data transfer completion detecting means for detecting the data transfer completion, and the both detecting means. Transfer stop means for stopping the transfer of the interface circuit at the time of detection, interrupt generating means for generating an interrupt to the CPU at the time of detecting the completion of command transfer, and a buffer for reading the command / data transferred last in the interrupt processing by the interrupt generating means Interface circuit having access means . 2. When the data transfer is completed, if the identification information is not the priority information, the next information to be transferred is identified as a command, and transfer stop means for restarting the transfer is provided. The interface circuit according to claim 1, further comprising an interrupt generation unit that generates an interrupt. 3. In the interrupt processing after the completion of command or data transfer, the last transferred command / data is read from the buffer and detected, and if the command / data is prioritized processing, the input pointer of the buffer having the FIFO structure 3. The interface circuit according to claim 2, further comprising a buffer access unit for returning the value to the value before the information transfer and holding the value after the transfer if the priority information is not the priority information. 4. A transfer completion detecting means is provided which has a counting means for counting transfer information, and which has a command / data transfer completion when the count value reaches a preset transfer amount in the counting means. The interface circuit according to claim 2. 5. A code identifying means for identifying a specific code from the transfer information and a transfer information counting means,
3. The interface circuit according to claim 2, further comprising transfer completion detecting means for detecting transfer completion at the time of code identification at the time of command transfer, and at completion of a predetermined count at the time of data transfer. 6. A command holding means for holding a command transferred at the time of command transfer, a specific pattern detecting means for detecting a specific pattern from a command input to this command holding means, and an input pointer of a FIFO buffer are saved. It has a pointer save register
3. The input pointer is saved in the save register at the start of data transfer, and the contents of the save register are restored to the input pointer at the time of specific pattern detection at the completion of command transfer or priority information at the completion of data transfer. The described interface circuit.