JPH0944116A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide technology which can reduce the area of a frame part by decreasing data lines for transferring display data to a dry driving circuit. SOLUTION: Of the liquid crystal display device equipped with a TFT liquid crystal display panel 101 which has a plurality of thin film transistors(TFT) provided in matrix, a drain driving circuit 104 which drives the drain signal line 108 of the TFT liquid crystal display panel 101, a signal converting circuit 102 which converts control signals and display data inputted from a computer part into the control signals and display data of the liquid crystal panel 101, and a transfer means 103 which transfers the display data outputted from the signal converting circuit 102 to the drain driving circuit 104, the transfer means 103 is equipped with a common transfer means which transfers display data of blue and red by a common data line and the drain driving circuit 104 is equipped with a data separating means which separates the display data transferred by the common data line into display data of blue and red.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device,
In particular, the present invention relates to a technique for reducing the number of data lines that transfer display data from a signal conversion circuit that converts display data for a CRT to display data for an active matrix liquid crystal display device to a drain drive circuit.

[0002]

2. Description of the Related Art FIG. 8 is an exploded perspective view showing a schematic structure of a conventional liquid crystal display device (MDL). SHD is a frame-shaped shield case (metal frame) made of a metal plate, and LCW.
Is a display window, PNL is a liquid crystal display panel, SPB is a light diffusing plate, LCB is a light guide, and RM is a reflecting plate. Each member is stacked in a vertical arrangement as shown in FIG. Is assembled.

The drive circuit board PCB1 is a liquid crystal drive IC
A drive circuit board in which the chip is mounted by tape automated bonding (TAB), divided into two parts, one for the video signal drive circuit (drain drive circuit) and one for the scan signal drive circuit (gate drive circuit). There is.

On the drive circuit board PCB2, a common electrode drive circuit (common drive circuit) of the liquid crystal display panel PNL, a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and a host ( C from the host processor)
A circuit including a signal conversion circuit for converting RT (cathode ray tube) information into information for a TFT liquid crystal display device is mounted. Further, the drive circuit board PCB2 has a connector connecting portion (not shown) for connecting to the outside.

Since the liquid crystal display device MDL displays 260,000 colors, red (R), green (G), and blue (in order to transfer a video signal (segment signal) from the signal conversion circuit to the drain driver. Since a bus width of 6 bits is required for each color in B), 18 data lines are connected from the drive circuit board PCB2 to the drive circuit board PCB1 with only data lines.

[0006]

SUMMARY OF THE INVENTION As a result of studying the above prior art, the present inventor has found the following problems.

In the conventional liquid crystal display device MDL, 6 bits × 3 colors = 18 data lines are required to display 260,000 colors, and in order to realize 16.7 million color display which is currently called full color display. , 8 bits for each color are required, and therefore, 8 bits × 3 colors = 24 data lines are required, and the area occupied by the data lines is increased by 33%.

On the other hand, in the current liquid crystal display device, the frame portion, which is a non-display area, is reduced in order to increase the screen size, the number of colors, and the number of gradations, and also to reduce the size of the device equipped with the liquid crystal display device. It is requested to make it.

An object of the present invention is to reduce the number of data lines for transferring display data to the drain driving circuit while enabling the data transfer speed and the multi-color / multi-gradation, thereby reducing the area of the frame portion. It is to provide a technology capable of reducing

Another object of the present invention is to reduce the apparent reduction in image quality with respect to the horizontal resolution deterioration of the liquid crystal display device caused by reducing the number of data lines.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) A TFT liquid crystal display panel having at least a plurality of thin film transistors arranged in a matrix, a drain drive circuit for driving a drain signal line of the TFT liquid crystal display panel, a control signal input from a computer section, and A liquid crystal display including at least a signal conversion circuit for converting display data into a control signal of the liquid crystal display panel and display data, and a transfer unit for transferring the display data output from the signal conversion circuit to the drain drive circuit. In the device, the transfer means includes common transfer means for transferring blue and red display data having less luminance components to green through a common data line, and the drain drive circuit transfers through the common data line. Data separation means for separating the displayed data to be displayed in blue and red. Characterized in that it Bei.

(2) The common transfer means includes a changing means for changing the transfer order of the blue and red display data.

[0015]

According to the above-mentioned means (1), the transfer means transfers the green display data having many luminance components by the dedicated data line (bus) as in the conventional case, and the blue and red display data are transferred. Uses a common data line and alternately transfers the display data.

On the other hand, the drain driving circuit which receives the display data latches the green display data for one line and outputs a drive voltage corresponding to the latch value to a predetermined drain line. .

In the drain drive circuit which has received the blue and red display data, the data separating means transfers the blue and red display data transferred at the same transfer rate as the green display data to the respective color data. And latches the same, and outputs a drive voltage corresponding to the latch value to a predetermined drain line.

That is, as is well known, for the green display data which has a large number of luminance components and is sensitive to human vision, the transfer means has the same bit width of the data line according to the number of display colors as in the conventional case, and the panel. The display data corresponding to all the above green pixels is transferred to the drain drive circuit.

On the other hand, for the display data of blue and red, which have less luminance components than that of green, the shared data line having the same bit width as that of green is used, and the display data of half the number of pixels on the panel is used. Are transferred to the drain drive circuit at the same transfer speed as the green display data.

Upon receiving the display data, the drain driving circuit outputs a voltage corresponding to the green display data to a predetermined drain line as in the conventional case.

On the other hand, regarding the blue and red display data, first, the data separation means of the drain drive circuit transfers the same data lines in a time division manner, so that the display data is displayed in blue and red. Then, the drain drive circuit outputs a voltage corresponding to the separated data to a predetermined drain line.

At this time, since the transferred blue and red display data is half of the green display data, the drain driving circuit drives the drain lines of two pixels with the display data of one pixel.

As described above, when the display data is transferred from the control means to the drain drive circuit, the display data for the color most sensitive to human vision, that is, for driving the green pixel having many luminance components is used. The display data is transferred to the drain driving circuit as usual, and the display data for driving the blue and red pixels is the same as the display data for half the number of green pixels, which are displayed in green on the same data line. The data is transferred at the same transfer rate as that for the display data, and the drain drive circuit drives the corresponding drain line based on this data for the green display data as in the conventional case, and the separating means for the blue and red display data. By driving every two pixels based on the separated display data, the display data for three colors of green, red, and blue are drained from the signal conversion circuit by the data lines for two colors. Since can be transferred to the driving circuit, it is possible to reduce the data line without raising the transfer speed.

As a result, the area of the frame portion, which is the non-display area of the liquid crystal display device, can be reduced.

According to the above-mentioned means (2), when the changing means alternately transfers the blue and red display data, the order of the display data to be transferred is exchanged for each line, for example, the first line. When transferring in the order of blue, red, and blue in the transfer, the second line transfers red,
By transferring the display data in the order of blue, the resolution in the horizontal direction can be reduced, so that the apparent deterioration of the image quality can be suppressed.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail with reference to the drawings together with embodiments.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

FIG. 1 is a block diagram showing a schematic configuration of the liquid crystal display device of the first embodiment. 101 is a TFT liquid crystal display panel (TFT-LCD, active matrix type liquid crystal display panel), and 102 is a controller (signal conversion circuit). 1
Reference numeral 03 is a transfer circuit (transfer means), 104 is a drain driver (drain drive circuit), 105 is a gate driver, 1
06 is a thin film transistor (TFT), 108 is a drain line, 109 is a gate line, 110 is a common signal line, and 111
Is a green subpixel, 112 is a blue subpixel, 113 is a red subpixel, 114 is a liquid crystal capacitor, and 115 is a storage capacitor.

In FIG. 1, a TFT liquid crystal display panel 10 is provided.
1 is a known device in which a liquid crystal (not shown) is sandwiched between a substrate (not shown) on which a transparent electrode (pixel electrode) is formed and a substrate (not shown) on which a counter electrode is formed, and the liquid crystal is driven by a voltage applied to the transparent substrate. This is a vertical electric field type TFT liquid crystal display panel, which is composed of 640 × 3 × 480 pixels.

The controller 102 receives a T signal from a video signal and a sync signal input from an information processing device (not shown).
A signal, such as an M signal, which is a reference signal necessary for causing the FT liquid crystal display panel 101 to perform a display, for example, for inverting the polarity of the voltage applied to each pixel of the TFT liquid crystal display panel 101 in a predetermined cycle. make.

The transfer circuit 103 includes green (G), red (R), and blue (B) sub-pixels 11 of the TFT liquid crystal display panel 101.
The display data is transferred to the drain driver 104 that drives 1-113.

The drain driver 104 generates a drive voltage based on the display data on a predetermined drain line 108,
Output.

The gate driver 105 is the controller 1
On the basis of the data No. 02, a predetermined gate signal line is driven for each frame (in this embodiment, 1/60 Hz≈16 milliseconds) of the liquid crystal display device to drive the pixels 111 to 11 to be driven. "ON" / "OFF" of the TFT 106 connected to 113 is controlled.

The TFT 106 includes the sub-pixels 111 to 113.
To the sub-pixels 111 to 113, which are connected to the drain drive voltage output to the drain signal line 108 based on the output of the gate driver 105.
Apply to.

The liquid crystal capacitance 114 is equivalent to the capacitance generated by the liquid crystal layer sandwiched between the transparent electrode side substrate (not shown) and the counter electrode side substrate (not shown) for each pixel, and one terminal is It is connected to the TFT 106 and the other terminal is connected to the common signal line 110.

As is well known, the storage capacitor 115 is a TFT.
When the 106 is switched, the change in the gate potential applied to the gate of the TFT 106 is changed by the sub-pixels 111 to 113.
Has a function of reducing the influence on the potential applied to the pixel, and a function of prolonging the discharge time by accumulating image information (voltage applied to each sub-pixel) after the TFT 106 is “OFF” for a long time. There is also.

FIG. 2 is a circuit diagram showing a schematic configuration of the transfer circuit 103. 201 is a buffer, 202 and 203 are well-known exclusive OR circuits (hereinafter referred to as "XOR", change means), and 204 is. A switch (common transfer means) is shown.

However, FIG. 2 shows a circuit configuration for one bit of the transfer circuit 103. In this embodiment, the same number of buffers 201 and switches as the data lines (data buses for display) corresponding to the number of display colors are provided. 203 is provided.

In FIG. 2, a buffer 201 is an output buffer which performs buffering when the display data latched in a register (not shown) of the controller 102 is output to the drain drive circuit 104.

The switch 203 is a 2-input 1-output digital switch. When the output of the XOR 203 is Low, the data of the R signal line (the signal line connected to the register for latching the display data of the red pixel) is set to R, Output to the B signal line (common signal line), and when the output of the XOR 203 is High, the data of the B signal line (the signal line connected to the register that latches the display data of the blue pixel) is the R and B signal lines. Output to.

FIG. 3 is a circuit diagram showing a schematic structure of the drain driver 104 for driving the red and blue drain lines. 301 is a shift register, 302 is a changeover switch (data separating means), and 303 is a digital / analog ( D / A) converter, 304 a buffer amplifier, and 305 R, B signal lines.

The shift register 301 includes R and B signal lines 3
The display data corresponding to the 640 red (R) and blue (B) sub-pixels 112 and 113 output from the transfer circuit 103 are sequentially fetched at 05 and output to Qn which is an output terminal.
(However, it is a natural number of n ≧ 1).

The change-over switch 302 is a 2-input 2-output switch. When the S input terminal is Low, the signal input from I ₁ is O ₁ and the signal input from I ₂ is O _2.
Are output respectively.

On the other hand, when the S input terminal is High, I
_The signal input from _{1 is} output to O ₂ , and the signal input from I ₂ is output to O ₁ .

The D / A converter 303 is a well-known 8-bit input D / A converter that converts an 8-bit digital signal into a 256-level analog signal.

The buffer amplifier 304 is the D / A converter 3
The output of No. 03 is buffered, and the amplified signal is output as an AC signal with the reference voltage as the center level based on an AC signal (M signal) not shown.

When the upper left of the TFT liquid crystal display panel 101 is considered as the origin, the connection destinations indicated by R1, B1 and the like showing the drain line to which the output of the buffer amplifier 304 is connected are, for example, R1 is a red sub line. The leftmost drain line connected to the pixel 113, B1 is the leftmost drain line connected to the blue subpixel 112, and the alphabet is the subpixel color, and the number following it is the subpixel of the target color. It shows the position of the drain line connected to the pixel from the left.

Further, the R / B drain driver 104
It is assumed that the display data transferred and output from the transfer circuit 103 is sequentially input to the shift register 301 every 8 bits and shifted.

Therefore, Q _{1 of the} shift register 301,
The numbers of the latch data indicated by Q ₂ ... Q ₆₄₀ and the numbers of the transfer data shown in FIG.

FIG. 4 is a diagram showing a relationship between control signals output from the controller 102 to the drain driver 104 and the gate driver 105. FIG. 4 (1) shows a frame signal in which High and Low are inverted every frame. , A well-known alternating signal, which is a reference signal for preventing deterioration of the liquid crystal by inverting the voltage applied to the liquid crystal at a predetermined cycle, and a vertical synchronization signal output as one shot pulse for each frame. Show the relationship.

FIG. 4B is an enlarged view of the start portion of the first frame. The horizontal synchronizing signal output as one shot pulse for each line and the data being transferred are in odd lines of the liquid crystal display device. The relationship with an odd line signal indicating whether the data is data or even line data is shown.

When the odd line signal is Low, it means that the display data output from the register (not shown) is the data of the odd line of the liquid crystal display device. On the other hand, when it is High, the display data of the even line. Indicates that the data.

FIG. 4C is an enlarged view of the start portion of the first frame and the first line. The 1/2 dot clock is the output cycle of the display data transferred and output from the register (not shown) of the controller 102 (display The output is inverted at the data transfer speed), and the output is started from Low when the transfer of each line data is started.

That is, it becomes Low in the case of display data corresponding to odd-numbered pixels from the left side, and becomes High in the case of display data of even-numbered pixels.

FIG. 5 is a diagram showing the relationship between the display data transferred from the transfer circuit 103 to the drain driver 104 and the 1/2 dot clock. FIG. 5A shows the case of odd frames and odd lines. , And the display data output from the transfer circuit 103. FIG. 5B shows the case of odd frames and even lines.

FIG. 5C shows the display data transferred and output in the case of an even frame and an odd line, and FIG.
Indicates the transfer output for even frames and even lines.

Next, the operation of the transfer circuit 103 shown in FIG. 2 will be described with reference to FIGS. 4 and 5. First, in the case of transferring the display data of the odd-numbered frame and the first line, FIG.
As is clear from (1) and (2), since the frame signal becomes High and the odd line signal becomes Low, XO
The output of R202 becomes High, and the output of XOR203 becomes an output obtained by inverting the 1/2 dot clock.

Therefore, the output O of the switch 204 at the time of outputting the data of the first pixel is connected to the input terminal a and outputs the display data R1 of the red sub-pixel to the R / B signal line 305.

On the other hand, when outputting the data of the second pixel, XOR
The output of 203 (S terminal input of the switch 204) is Low
Therefore, the output O of the switch 204 is connected to the input terminal b, and as a result, the display data B2 of the blue sub-pixel is output to the R / B signal line 305.

FIG. 5 showing even frames and the first line
In the case of (3), the frame signal is Low, and the odd line signal at this time is also Low.
The output of 202 becomes Low.

Therefore, since the output of the XOR 203 is in phase with the 1/2 dot clock signal, the output O of the switch 204 becomes the display data of the red sub-pixel input from the input terminal a, and 1/2 at the second pixel of
Since the dot clock becomes High, the switch 204
Output O and input terminal b are connected, and the data of the second pixel becomes display data for the blue sub-pixel connected to the b input terminal and is transferred and output to the R and B signal lines 305.

When the display data for the second line of the even frame shown in FIG. 5 (4) is transferred, the frame signal is Low, and since the data transfer is for the second line, the odd line signal is High. Therefore, the output of the XOR 202 is High, and the output of the XOR 203 is the inverted signal of the 1/2 dot clock signal.

Therefore, as in the case of FIG. 5B, the switch 20 is used when the display data of the first pixel is transferred.
The output O of 4 outputs the display data (B1) of the blue sub-pixel connected to the input terminal b.

At the time of transferring the next display data of the second pixel, the S terminal of the switch 204 becomes Low, and the display data (R2) of the red sub-pixel is output to the output O.

Next, FIG. 6 is a diagram showing the relationship between the display data and the display line output to the drain line 108 in the odd frame, and FIG. 7 is the drain line 108 in the even frame.
3 is a diagram showing the relationship between the display data and the display line output to the display line. The drain lines connected to the red and blue subpixels of the drain driver 104 shown in FIG. 3 based on FIGS. Drain driver 10 driving 108
The operation of No. 4 (hereinafter, referred to as “RB drain driver”) will be described.

However, the operation of the drain driver 104 for driving the drain line 108 connected to the green sub-pixel is the same as that of the conventional drain driver 104, and therefore the description of the operation will be omitted.

When the R / B drain driver 104 outputs the drive voltage corresponding to the display data of the first line of one frame, the transfer circuit 103 in the order shown in FIG. 5 (1).
The display data output from the shift register 30 is sequentially output.
1 is stored and shifted, the shift register 301
The output terminal number and the transfer data transfer order number match. That is, the display data (B1) for the first blue pixel is stored in Q1, and the display data (R2) for the second red pixel is stored in Q2.

At this time, the frame signal and the odd line signal are high as shown in FIG.
Since the odd line signal is Low, the output of the XOR 306 is High (odd frame, odd line).

Therefore, the digital switch 302 outputs the display data input from the input terminal I ₁ to the output terminal O ₂ .
The display data input to the input terminal I ₂ is output to the output terminal O ₁ , the display data is converted into a drive voltage (analog signal) by the D / A converter, and the buffer amplifier 303 buffers the data to be respectively converted. The drive voltage is supplied to the drain line 108 connected to the sub-pixel.

For example, the display data for the blue first sub-pixel stored in Q ₁ is converted into an analog signal (driving voltage) by the D / A converter 303, and this signal is converted by the buffer amplifier 303. 1 for supplying the driving voltage of the first and second blue sub-pixels that are buffered
It is output to the second and second blue drain lines 108 (601). The display data for the second red sub-pixel stored in Q ₂ is converted into an analog signal (driving voltage) by the D / A converter 303, and this signal is buffered by the buffer amplifier 303. First and second
It is output to the first and second red drain lines 108 for supplying the driving voltage of the second red sub-pixel (6
02).

On the other hand, the R / B drain driver 104 is set to 1
When the drive voltage corresponding to the display data of the second line of the frame is output, the display data output from the transfer circuit 103 in the order shown in FIG.
01 is stored and shifted in order from the upper side (Q ₆₄₀ ), so that the display data (R ₁ ) of the red first pixel is displayed in Q _1, and the display data (R ₁ ) of the blue second pixel is displayed in Q _2. B ₂ ) is stored.

At this time, the frame signal and the odd line signal are both Low as shown in FIG. 4, so the output of the XOR 306 is L.
ow (even frames, odd lines).

Therefore, the digital switch 302 outputs the display data input to the input terminal I ₁ to the output terminal O ₁ .
The display data input to the input terminal I ₂ is output to the output terminal O ₂ , the display data is converted into a drive voltage (analog signal) by the D / A converter, and the buffer amplifier 303 buffers the data to be respectively converted. The drive voltage is supplied to the drain line 108 connected to the sub-pixel.

For example, the display data for the red first sub-pixel stored in Q ₁ is the D / A converter 303.
Is converted into an analog signal (driving voltage) by the buffer amplifier 303, and this signal is buffered by the buffer amplifier 303 to supply the driving voltage for the first and second red subpixels. It is output to the drain line 108 (701). The display data for the second blue subpixel stored in Q ₂ is converted into an analog signal (driving voltage) by the D / A converter 303, and this signal is buffered by the buffer amplifier 303. 1 for supplying the driving voltage of the first and second blue sub-pixels.
The second and second blue drain lines 108 are output (702).

When the frame signal is Low and the odd line signal is High, that is, in the case of even frames and odd lines, the output of the XOR 306 is High as in the case where the frame signal is High and the odd line signal is Low. , The same operation as when the frame signal is High and the odd line signal is Low (in the case of an odd line of an odd frame, for example, 601 and 602 in FIG. 6).

When both the frame signal and the odd line signal are High, that is, when the odd line of the even frame, the output of the XOR 306 becomes Low as in the case where the frame signal is Low and the odd line signal is Low. Therefore, the frame signal is Low and the odd line signal is Lo
The operation is the same as in the case of w (in the case of even frames and odd lines, for example, 701 and 702 in FIG. 7).

As described above, the controller 102
Is a drain line that transfers display data input from a computer main body (not shown) from the transfer circuit 103 to the drain driver 104, and the drain driver 104 connects a drive voltage (analog signal) based on the display data to the corresponding subpixel. In the case of outputting to 108, the green display data having many luminance components is transferred through the signal line (G signal line) dedicated to green as in the conventional liquid crystal display device, and the drain driver 104 for green displays this display data. The drive voltage based on the above is output to the drain line 108.

On the other hand, for the red and blue display data, the switch 204 of the transfer circuit 103 uses the frame signal, the odd line signal, and the 1/2 dot clock to generate the red display data at the same transfer rate as the green display data. And blue display data are alternately output to the R / B signal line 305, and the red and blue drain drivers shown in FIG. 3 are driven by the drive voltage based on the display data for one pixel to generate two drain lines. By driving 108, the number of signal lines for transferring display data from the transfer circuit 103 to the drain driver 104 can be reduced to 2/3 without increasing the data transfer rate.

As a result, the area of the frame portion which is the non-display area of the liquid crystal display device can be reduced.

Further, in the case of red display data, for example, even in the case of display data for generating an applied voltage for displaying the red first pixel, the first display data is The display data of the red and blue pixels are arranged so that the second display data is transferred alternately and the first display data and the second display data are transferred alternately for each frame. Transfer order,
That is, by changing the transfer order of the display data for each line, it is possible to suppress an apparent decrease in resolution.

In this embodiment, a vertical electric field type TFT liquid crystal display panel is used as the liquid crystal display panel.
Although the operation and effect of the present invention have been described, it is needless to say that the present invention can be applied to a lateral electric field type TFT liquid crystal display panel as described in Japanese Patent Application No. 7-105862 relating to the same applicant, “Liquid Crystal Display Device”. Yes.

Furthermore, in this embodiment, an amorphous silicon thin film transistor element is used as the TFT (thin film transistor) 106, but the present invention is not limited to this, and a polysilicon thin film transistor element or M on a silicon wafer is used.
OS type transistor, organic TFT, or MIM (M
It is also possible to use a two-terminal element (strictly not an active element, but an active element in the present invention) such as an et al-insulator-metal) diode.

As described above, the invention made by the present inventor
Although the present invention has been specifically described based on the above-mentioned embodiments, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0084]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) To reduce the number of signal lines required for transferring display data by alternately transferring red and blue display data, which have less luminance components than green, through the same signal line. Therefore, the area of the frame portion through which the signal line passes can be reduced.

(2) By changing the transfer order of the display data for each line, it is possible to suppress the apparent deterioration of the resolution.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device which is an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a schematic configuration of a transfer circuit.

FIG. 3 is a circuit diagram showing a schematic configuration of a drain driver that drives red and blue drain lines.

FIG. 4 is a diagram showing control signals output from a controller to a drain driver and a gate driver.

FIG. 5 is a diagram showing a relationship between display data transferred from a transfer circuit to a drain driver and a 1/2 dot clock.

FIG. 6 is a diagram showing a relationship between display data output to a drain line in an odd frame and a display line.

FIG. 7 is a diagram showing a relationship between display data output to a drain line and a display line in an even frame.

FIG. 8 is an exploded perspective view showing a schematic configuration of a conventional liquid crystal display device.

[Explanation of symbols]

101 ... Liquid crystal display panel, 102 ... Controller, 10
3 ... Transfer circuit, 104 ... Drain driver, 105 ... Gate driver, 106 ... TFT, 108 ... Drain line,
109 ... Gate line, 110 ... Common signal line, 111 ... Green subpixel, 112 ... Blue subpixel, 113 ... Red subpixel, 114 ... Liquid crystal capacity, 115 ... Storage capacity, 201 ...
Buffers, 202, 203, 306 ... XOR, 204 ...
Switches, 301 ... Shift register, 302 ... Changeover switch, 303 ... D / A converter, 304 ... Buffer amplifier, 305 ... R, B signal lines.

 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Yoichi Igarashi 3300 Hayano, Mobara-shi, Chiba Hitachi, Ltd. Electronic Device Division

Claims (2)

[Claims] 1. A plurality of pixel electrodes arranged in a matrix, active elements connected to each of the pixel electrodes, and a plurality of pixel elements formed in a column direction and applying a signal voltage to each active element in the column direction. An active matrix liquid crystal display panel having at least a drain signal line, a drain drive circuit for driving the drain signal line, and a signal for converting a signal input from a computer unit into a control signal for the liquid crystal display panel and display data. In a liquid crystal display device including at least a conversion circuit and a transfer unit that transfers display data output from the signal conversion circuit to the drain drive circuit, the transfer unit includes a blue color having a smaller luminance component than a green color, The drain is provided with a common transfer means for transferring the display data in red through a common data line. Dynamic circuit, a liquid crystal display device characterized by comprising a data separating means for separating the display data transferred by the common data lines in the blue and red display data. 2. The liquid crystal display device according to claim 1, wherein the common transfer unit includes a changing unit that changes a transfer order of blue and red display data.