JPH0936670A - Power amplifier - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power amplifier which can suppress the nonlinear distortions and also can reduce the power consumption. SOLUTION: The source of a pulse dope type GaAs FET Q is connected to a ground terminal, and an impedance matching circuit Ain consisting of a coil L1 and a capacitor C1 and an impedance matching circuit Aout consisting of a coil L2 and a capacitor C3 are connected to the gate and the drain of the FET Q respectively. Then a DC bias (operating point) is set so that an AB-class amplifying operation is secured. At the same time, the input signal supplied to an input contact is outputted to an output contact after power amplification.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power amplifier for power amplification of a high frequency signal or the like, and more particularly to a power amplifier for suppressing nonlinear distortion and reducing power consumption.

[0002]

2. Description of the Related Art Such a power amplifier has a circuit configuration in which active elements such as bipolar transistors and field effect transistors (FETs) are combined with passive elements such as resistors, capacitors and inductors. Due to the non-linearity, the harmonic distortion and the intermodulation distortion such as the second harmonic wave and the third harmonic wave of the fundamental wave of the input signal appear in the output signal.

For example, in a wireless communication device such as a mobile phone, when multi-carrier signals are amplified by wide band power, third-order intermodulation distortion that is difficult to remove occurs in a channel band or outside the channel band. Second-order intermodulation distortion occurs and causes problems such as interference between adjacent channels.

That is, the spectra P _f1 , P _f2 and P of FIG.
_{2f1 + f2} and P _2f1-f2 show different frequencies f
Assuming that the modulated signal by the two carriers of ₁ and f ₂ is power-amplified, third-order intermodulation distortion of frequencies 2f ₁ + f ₂ and 2f ₁ −f ₂ occurs, and this third-order intermodulation distortion is within the channel band. Since it occurs, it cannot be easily removed by a filter or the like. On the other hand, the secondary modulation distortion has a frequency f ₁
Since the second-order intermodulation distortion that occurs in + f ₂ and f ₁ -f ₂ is likely to occur outside the channel band, for example, 50
This is a problem in the field of broadband communication such as a cable television system (CATV) using the band of MHz to 1 GHz. Further, even in a digital communication system such as π / 4 shift QPSK and QAM, a similar problem due to digital modulation distortion is brought about, and therefore, strict regulation is set.

By the way, comparing a silicon bipolar transistor used in such a high frequency power amplifier with a field effect transistor, it is said that the field effect transistor has a smaller nonlinear distortion.

That is, the characteristic function of the collector current Ic with respect to the base applied voltage Vb of the silicon bipolar transistor can be expressed by the following equation (1), and the characteristic function of the drain current Id with respect to the gate applied voltage Vg of the field effect transistor can be represented by the following equation (1). Since it is represented by (2), the second-order distortion and third-order distortion of each transistor can be obtained by the higher-order differentiation of these equations (1) and (2). That is, the second-order distortion IM2Bi and the third-order distortion IM3Bi of the silicon bipolar transistor, and the second-order distortion IM2FET and the third-order distortion IM3FET of the field effect transistor are
It is expressed by the following equations (3) to (8). Therefore, as is apparent from the following equations (7) and (8), it is considered advantageous to use the field effect transistor in the communication field.

Ic = A · exp (kVb −1) {where A and k are constants} (1) Id = A · (Vg −Vp) ² {where A is a constant and Vp is a pinch-off voltage} ( 2) IM2Biδ ² Ic / δVb ² (3) IM3Biδ ³ Ic / δVb ³ (4) IM2FET δ ² Id / δVg ² (5) IM3FET δ ³ Id / δVg ³ ... (6) IM2Bi> 7IM2FET ) IM3Bi> IM3FET (8) Furthermore, by using a field effect transistor having a large saturation output power, non-linear distortion can be reduced, and at the same time, always operate with an output power smaller than the maximum allowable output power of the field effect transistor. Therefore, a method of further reducing the non-linear distortion (called a back-off method) is generally applied.

[0008]

Since this back-off technique uses the field-effect transistor within a small input / output power range where its linearity can be obtained, nonlinear distortion can be reduced. On the other hand, however, the operating voltage range set by the power supply voltage is not effectively used, which causes a problem of relatively increasing power consumption.

Therefore, for example, about one-third of the total power consumption, such as a battery-operated mobile phone handset.
If the back-off method is simply applied to the electronic device in which the power amplifier occupies, the battery consumption will be accelerated, so that the back-off method cannot be simply applied.

Also in the communication base station and the fixed station, it is an important issue to reduce the power consumption of the power amplifier from the viewpoints of the efficiency of the power supply system and the heat radiation measures.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a power amplifier which can reduce the generation of harmonic components and at the same time reduce the power consumption.

[0012]

In order to achieve such an object, the present invention has a channel layer having a high impurity concentration and a thin thickness, and a cap layer laminated on the channel layer. A doping layer is formed that is depleted by the surface depletion layer and has a thickness and a predetermined impurity concentration that prevent the surface depletion layer from reaching the channel layer. Further, an implantation layer is formed at both ends of the cap layer and the channel layer. A pulse-doped gallium arsenide field effect transistor having a source and a drain in each of the injection layers and a gate formed on the cap layer, and between the gate and the source of the pulse-doped gallium arsenide field effect transistor and the drain source. Is connected in between, and is electrically connected to the non-linear strain of the pulse-doped gallium arsenide field effect transistor. Added efficiency is a configuration comprising an impedance matching circuit for matching the output impedance when the maximum.

[0013]

Since the characteristics of the drain current with respect to the gate applied voltage of the pulse-doped gallium arsenide field effect transistor are linear, the generation of nonlinear distortion included in the output of the power amplifier is significantly suppressed. With the suppression of the non-linear distortion, the bias is set to obtain high power added efficiency, the non-linear distortion is small, and the power consumption is significantly reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the power amplifier according to the present invention will be described below with reference to the drawings. This embodiment relates to a high frequency power amplifier applied to the field of wide band communication such as CATV system and wireless communication. Based on FIG. 1, the main configuration (basic circuit) of this power amplifier is shown in FIG. Based on the structure and characteristics of the field effect transistor used in this power amplifier, the effect of the embodiment will be described with reference to FIGS. 3 and 4.

In FIG. 1, the source of the field effect transistor Q is connected to the ground contact, its gate is connected to the input contact via an impedance matching circuit Ain consisting of a coil L1 and a capacitor C1, and its drain is connected to the coil L2 and a capacitor. It is connected to the output contact via an impedance matching circuit Aout composed of C2. And
The DC bias (operating point) is set so that the field effect transistor Q performs amplification operation of class AB, and the input / output impedance of the field effect transistor and the impedance matching circuit Ain, A are set so as to maximize the power added efficiency.
Impedance matching with the respective input / output impedances Z11 and Z22 of out is taken.

Here, the field effect transistor Q is disclosed in Japanese Patent Application Laid-Open No. 4-225533 (Japanese Patent Application No. 2-407762).
The pulse-doped gallium arsenide field effect transistor (hereinafter referred to as GaAsFET) disclosed in Japanese Patent No. 4) is applied. The schematic structure thereof will be described with reference to the vertical sectional view of FIG. 2A.
Type non-doped GaAs buffer layer 2 is laminated to form GaA
A high concentration and thin Si-doped GaA is formed on the s buffer layer 2.
The s channel layer 3 is laminated. Furthermore, the channel layer 3
Above the n-type non-doped GaAs layer 4, a thin Si-doped GaAs doping layer 5, and an n-type non-doped layer 6
Are sequentially laminated, and a gate electrode is formed on the n-type non-doped layer 6. The layers 4 to 6 which are sequentially stacked on the channel layer 3 constitute a so-called cap layer. Then, n ⁺ type ion implantation layers 8 and 9 reaching the GaAs buffer layer 2 are formed on both sides of each of these layers 3 to 6, and the drain electrode 10 is formed on each upper end of these implantation layers 8 and 9.
And the source electrode 11 is formed.

Pulse-doped Ga applied to the present invention
The AsFET Q keeps the transconductance gm (= Id / Vg [m S / mm]) constant with respect to changes in the gate voltage Vg [V], as indicated by the solid line L _NEW in FIG. 2 (b). It has the characteristic of drooping, and the conventional field effect transistor,
For example, an ion-implanted ME having an ion-implanted active layer
This is in contrast to the fact that the transconductance of the SFET or the like (shown by the dotted line L _OLD in FIG. 7B) changes non-linearly according to the change of the gate voltage.

That is, in the pulse-doped type GaAsFET Q applied to the present invention, since the diffusion of the surface depletion layer to the deep portion is blocked by the doping layer 5, the channel layer 3 is affected by this surface depletion layer. Without being affected, only the depletion layer under the gate electrode 7 is affected. Therefore, even if the surface depletion layer is changed by the change of the gate voltage Vg, the carrier mobility is hardly increased, and the drain current is changed only by the increase of carriers, so that the transconductance gm is kept substantially constant. Be done. Moreover, since the doping layer 5 is depleted by the surface depletion layer, the insulation between the gate and the drain is not deteriorated. On the other hand, in the field effect transistor such as the above-mentioned conventional MESFET in which the active layer is formed by ion implantation, the active layer is thick, so that the transconductance gm is increased due to the effect of increasing the carrier mobility and the gate voltage Vg is increased. Has a peak. That is, the transconductance gm of the conventional field effect transistor increases or decreases.

As described above, the pulse-doped GaAsFET Q applied to the present invention exhibits excellent high-frequency characteristics by keeping the transconductance gm substantially constant, and at the same time maintains the above-mentioned insulating property, thereby achieving a high drain breakdown voltage. And has high output and high gain characteristics.

The relationship between the gate voltage Vg and the drain current Id of this GaAsFET Q is expressed by the following equation (9). Id = A. (Vg-Vp) {where A is a constant and Vp is a pinch-off voltage} (9) Therefore, when this GaAsFET Q is applied to a power amplifier, second-order distortion IM2Ga and third-order distortion are included. The strain IM3Ga becomes IM2Gaδ ² Id / δVg ² = 0 (10) IM3Gaδ ³ Id / δVg ³ = 0 (11) by differentiating the above equation (9), which is 2 of the field effect transistor that has been conventionally used.
Second distortion IM2FET and third distortion IM3FET (Equation (5)
(6)) and the second-order strain IM2Ga of this GaAs FET Q
When comparing the third-order distortion IM3Ga (see above equations (10) and (11)), it is clear that IM2Ga <IM2FET (12) IM3Ga <IM3FET (13), and the power of FIG. 1 to which this GaAsFET Q is applied. Non-linear distortion of the amplifier is greatly suppressed.

Next, the principle and effect of the bias setting of the power amplifier shown in FIG. 1 will be described with reference to FIGS. 3 and 4.
3 is related to the power amplifier of FIG. 1 to which this GaAsFET Q is applied, and FIG. 4 is a GaA of the power amplifier of FIG.
The present invention relates to a power amplifier when a conventional general field effect transistor is applied instead of the sFET Q.

In these figures, the horizontal axis represents the input power (unit: dBm) to the high frequency amplifier, the left vertical axis represents the output power (unit: dBm), and the right vertical axis represents the power added efficiency (unit: dBm). %), The fundamental wave output power Pf, the second-order intermodulation distortion output power PIM2, the third-order intermodulation distortion output power PIM3, and the power-added efficiency ηadd with respect to the increase and decrease of the input power Pin of the signal of the frequency f. Shows the change of. The power added efficiency ηadd is the DC power PDC supplied from the power source.
Is an evaluation amount indicating how much is converted to high frequency power (that is, a measure of the quality of the power amplification characteristic of the active element), and ηadd = 100 × (Pf −Pin) / PDC (%) (14) ).

First, the power amplifier of this embodiment will be described with reference to FIG. 3. When the input power Pin gradually increases, the fundamental wave output power Pf linearly increases up to a certain range at a constant rate of increase. When it exceeds, the rate of increase gradually decreases in a non-linear manner and becomes saturated. On the other hand, the second-order intermodulation distortion output power PIM2 and the third-order intermodulation distortion output power PIM3 have similar output power characteristics as the input power Pin increases.

Therefore, the output power P in the linear increasing range
When the increase rate of f is Gf and the increase rate of the third-order intermodulation distortion output power PIM3 is GIM3, there is always a relationship of Gf <GIM3. Therefore, the output power P is based on these increase rates Gf and GIM3.
The upper limit of the operating power range (dynamic range) is determined by the output power PIP3 corresponding to the intersection point (intercept point) IP3 when f and PIM3 are extended.

The power added efficiency ηadd is as shown in the figure.
It becomes the maximum value ηMAX at a certain input power Pin. Therefore, if the input power Pin satisfying the condition that the power added efficiency ηadd becomes ηMAX is supplied, the DC power PDC is most effectively used. However, the basic output power Pf and the third order mutual power when ηadd = ηMAX are used. Modulation distortion output power PIM3 power difference Δ
P does not satisfy the noise resistance characteristic defined by the communication standard or the like. Therefore, the above-mentioned back-off technique is applied, and it is designed mainly for the reduction of the third-order intermodulation distortion output power PIM3 and for the optimization of the power added efficiency ηadd.

That is, the third-order distortion suppression ratio IM3 (= PIM3−P
The input power Pin is limited within the upper limit range that satisfies the standard condition such that f) is, for example, −40 dBc. As a result, the upper limit of the input power becomes Pinm in the figure, which is smaller than the input power PηMAX at the power added efficiency ηMAX. These power differences BO (= PηMAX −Pinm) are called backoff.

As described above, by applying the back-off technique in this embodiment as well, the actual power added efficiency ηIM3 becomes smaller than the maximum power added efficiency ηMAX. This power-added efficiency ηIM3 is obviously improved over the conventional power amplifier described based on. Hereinafter, this will be described.

Since the principle diagram (FIG. 4) of the conventional power amplifier to which the general field effect transistor is applied can be expressed in the same manner as FIG. 3, these will be described in comparison with FIG. 3 and FIG. As described based on the equations (10) to (13), the second-order strain IM2FET and the third-order strain IM3FET of the conventional field effect transistor are the second-order strain IM2Ga and the third-order strain IMGa of the GaAsFET Q of this embodiment. Since it is significantly larger than the fundamental wave output power Pf, as shown in FIG.
The second-order intermodulation distortion output power PIM2 'and the third-order intermodulation output power PIM3' are larger than the second-order intermodulation distortion output power PIM2 and the third-order intermodulation output power PIM3 of this embodiment (see FIG. 3). Then, an intersection point (intercept point) I between the fundamental wave output power Pf and the third-order intermodulation output power PIM3 '
The output power PIP3 'at P3' becomes smaller than the output power PIP3 at the intercept point IP3 of this embodiment. Therefore, the power amplifier of this embodiment exhibits an excellent effect that the dynamic range can be increased as compared with the conventional technique.

Further, according to the regulations, the fundamental wave output power Pf
3rd order intermodulation distortion output power PIM3 'at least-
If the back-off technique is applied so as to reduce it by 40 dBc, the back-off BO 'must be made larger than the back-off BO of this embodiment because the third-order intermodulation distortion output power PIM3' is large. The input power Pinm 'becomes smaller than the input power Pinm of this embodiment, and the power added efficiency ηIM3' corresponding to the input power Pinm 'also becomes smaller than the power added efficiency ηIM3 of this embodiment. That is, in the power amplifier of this embodiment, the above-mentioned GaAs FET
As a result of reducing the non-linear distortion by using Q, it becomes possible to set a higher input power Pinm and a higher power added efficiency ηIM3 than in the prior art, so that the power consumption is substantially reduced. It is possible to do.

As described above, according to the power amplifier of this embodiment, the nonlinear distortion is reduced by applying the pulse-doped GaAsFET Q, the dynamic range is improved, the input power Pin is increased, and the power added efficiency ηadd is obtained. It is possible to improve the power consumption, and it is possible to achieve an excellent effect that a substantial reduction in power consumption can be realized.

In the above description, attention has been paid to the third-order distortion, and the case where the third-order distortion is reduced and the power consumption is reduced has been described. However, the present invention describes the second-order distortion and other higher-order distortion. As for the third-order distortion, these distortions can be reduced and power consumption can be reduced as in the case of the third-order distortion.

A case for reducing the secondary distortion and power consumption will be described with reference to FIGS. 3 and 4. The second-order intermodulation distortion output power PIM2 with respect to the input power Pin of the power amplifier of the present invention to which the pulse-doped GaAsFET Q is applied has the characteristics shown in FIG. 3, and the input power Pin of the power amplifier to which the conventional field effect transistor is applied is Pin. The second-order intermodulation distortion output power PIM2 'has a characteristic as shown in FIG. 4, and the relationship of PIM2 <PIM2' is satisfied. That is, as shown in the equations (10) to (13), the second-order distortion IM2 due to the pulse-doped GaAs FET Q is obtained.
Second-order distortion IM2FE by Ga and conventional field effect transistor
Comparing with T, IM2Ga <IM2FET, so PIM
The relationship of 2 <PIM2 'is satisfied.

Then, based on these second-order intermodulation distortion output powers PIM2 and PIM2 ', the intersection point (intercept point) with the fundamental wave output voltage Pf is determined in the same manner as in the case of the third-order distortion, and the backoff is performed. Is applied to determine the input power (corresponding to Pinm and Pinm ') that satisfies a predetermined second-order distortion suppression ratio IM2 (not shown).

As described above, when the power amplifier is designed with attention to the second-order distortion, IM2Ga <IM2FET and PIM2 <P.
Since the relation of "IM2 'is satisfied, pulse-doped G
The backoff in the power amplifier of the present invention to which aAsFET Q is applied can be made smaller than the backoff in the power amplifier to which the conventional field effect transistor is applied, and as a result, the power amplifier of the present invention is clearer. In addition, the power added efficiency ηIM2 can be improved.

Also, when focusing on other high-order distortions and designing a power amplifier that reduces these distortions and reduces power consumption, as in the case of the above-mentioned second-order distortion and third-order distortion. Since the higher-order distortion due to the pulse-doped GaAsFET Q is smaller than the higher-order distortion due to the conventional field effect transistor, the present invention can provide a power amplifier with less nonlinear distortion and less power consumption. .

In addition, a π / 4 shift QSPK modulation method (qu
In a digital transmission system to which adrature amplitude modification etc. is applied, a digital modulation distortion is generated which is approximated as a collection of many wave components with slightly different frequencies, and higher order such as 3rd order, 5th order, 7th order, etc. It is known that distortion has an adverse effect within the transmission band. That is, the QSPK signal wave can be approximated as a group of majority carriers,
Therefore, a large number of intermodulation distortions with each carrier appear in the band, and suppressing this is extremely important for improving the reliability of the transmission system.

Even in such a case, it is possible to apply the pulse-doped GaAsFET Q and to reduce the above-mentioned second-order distortion, third-order distortion, etc. and power consumption of each of these higher-order distortions. When the power amplifier of the present invention formed by applying the same means is applied to a digital transmission system (for example, a modulation / demodulation circuit), it is significantly nonlinear distortion as compared with the power amplifier using the conventional field effect transistor. In addition, power consumption can be reduced, which can greatly contribute to the realization of a highly reliable transmission system.

As described above, according to the power amplifier of this embodiment, the nonlinear distortion is reduced by applying the pulse-doped GaAsFET Q, the dynamic range is improved, the input power Pin is increased, and the power added efficiency ηadd is obtained. It is possible to improve the power consumption, and it is possible to achieve an excellent effect that a substantial reduction in power consumption can be realized.

If this power amplifier is applied to a mobile phone handset that must be operated with a battery having an extremely limited capacity, it can be operated for a long time with a large reduction in power consumption and the battery itself can be made compact. It is possible to exert excellent effects such as downsizing, and further downsizing of the device itself, and when applied to communication equipment in a communication base station or fixed station, it improves efficiency of the power supply system and heat dissipation. Measures can be simplified.

[0040]

As described above, according to the power amplifier of the present invention, a pulse-doped gallium arsenide field-effect transistor having a linear drain current characteristic with respect to a gate applied voltage is used, and an impedance matching circuit is connected thereto. By setting the bias to obtain high power added efficiency, it is possible to reduce the occurrence of non-linear distortion, increase the input power and improve the power added efficiency. It has an excellent effect that reduction can be realized.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of a power amplifier according to the present invention.

FIG. 2 is an explanatory diagram showing a structure and characteristics of an active element for power amplification used in an example.

FIG. 3 is an explanatory diagram for explaining the principle and effect of the embodiment.

FIG. 4 is an explanatory diagram showing the principle of a conventional technique for further explaining the effect of the embodiment.

FIG. 5 is an explanatory diagram for explaining a problem due to nonlinearity of a power amplifier.

[Explanation of symbols]

L1, L2 ... Coil, C1, C2 ... Capacitance element, Q ... Ga
AsFET, 1 ... Semi-insulating GaAs semiconductor substrate, 2 ... G
aAs buffer layer, 3 ... Channel layer, 4 ... N-type non-doped layer, 5 ... Doping layer, 6 ... N-type non-doped layer, 7 ...
Gate electrode, 8, 9 ... Injection layer, 10 ... Drain electrode, 1
1 ... Source electrode.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kenichiro Matsuzaki 1 Taya-cho, Sakae-ku, Yokohama-shi, Kanagawa Sumitomo Electric Industries, Ltd. Yokohama Works

Claims (1)

[Claims] 1. A channel layer having a high impurity concentration and a thin thickness, and a cap layer laminated on the channel layer, wherein the cap layer is depleted by a surface depletion layer and the surface depletion layer is formed in the channel layer. A doping layer having a thickness and a predetermined impurity concentration for preventing the reaching is formed, and injection layers are formed at both ends of the cap layer and the channel layer. A pulse-doped gallium arsenide field effect transistor having a gate formed therein, and a non-linear strain of the pulse-doped gallium arsenide field effect transistor connected between the gate source and the drain source of the pulse doped gallium arsenide field effect transistor. To the output impedance when the power added efficiency is maximum Power amplifier, characterized by comprising an impedance matching circuit.