JPH0936254A - Mask rom and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the turn around time of a mask ROM while the gate insulating film of the ROM is not deteriorated by a program and the reliability of the ROM is maintained at a high level. SOLUTION: Al films 27 constituting bit lines are connected in advance to the drain diffusion layers 16 of transistors through branch sections 27a, etc., and a program is executed by removing the branch section 27a connected to the drain diffusion layer 16 of a nonselected transistor and an SiN film 31 formed on the section 27a. Therefore, a program process is executed immediately before the final manufacturing process, because an SiO2 film composed of a gate oxide film is not deteriorated by the program and the bit line is formed in the final stage of a wiring forming process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The invention of the present application is NO for programming individual transistors in the middle of a manufacturing process.
The present invention relates to an R-type mask ROM and a manufacturing method thereof.

[0002]

2. Description of the Related Art A NOR type mask ROM program system is roughly classified into an ion implantation program system and a contact program system. Among them, in the ion implantation program method, even the protective film covering the bit lines is formed, and impurities for increasing the threshold voltage of the unselected transistor are doped from above the protective film with high energy and high dose in the channel region of the transistor. Ion implantation.

On the other hand, in the conventional contact programming method, a contact hole is formed in the interlayer insulating film only for the diffusion layer of the selected transistor, and the bit line is connected to the diffusion layer through the contact hole.

[0004]

However, in the ion implantation programming method, since the gate insulating film deteriorates due to the ion implantation with high energy and high dose, the mask R is used.
The reliability of OM was not necessarily high. On the contrary,
In the contact programming method, the insulating film is not deteriorated so that the reliability of the mask ROM is high. However, since the bit line is formed after programming, the turnaround time is long. That is, in the conventional mask ROM, it has been difficult to achieve both improvement in reliability and reduction in turnaround time.

[0005]

A mask ROM according to claim 1
Has a branch portion electrically connected to one diffusion layer of a transistor forming a memory cell, the bit line has a branch portion, and the branch portion is selectively cut off to program It is characterized by what is done.

According to another aspect of the mask ROM of the present invention, the wiring connected to the diffusion layer extends in a direction intersecting with the extending direction of the bit line, and a portion of the wiring other than on the diffusion layer. It is characterized in that the branch portion is connected to.

According to a third aspect of the method of manufacturing a mask ROM, a step of electrically connecting a branch portion of a bit line to one diffusion layer of a transistor forming a memory cell, and a protection film for the bit line. The method is characterized by including a covering step and a step of performing a program by selectively removing the branch portion and the protective film on the branch portion.

According to another aspect of the mask ROM of the present invention, programming is performed by selectively cutting branch portions of bit lines, and impurities for increasing a threshold voltage of a transistor are selectively ion-implanted in a channel region. Since the programming is not performed by the implantation, the gate insulating film of the transistor is not deteriorated by the programming.

Moreover, the program is performed by selectively cutting the branch portions of the bit lines, and the bit line is formed last among the wirings. Therefore, the programming process is a manufacturing process. Just before the end.

According to another aspect of the mask ROM of the present invention, the bit line has a branch portion because the branch portion of the bit line is connected to a portion of the wiring connected to the diffusion layer other than on the diffusion layer. However, this bit line can be extended over the diffusion layer.

According to the method of manufacturing the mask ROM of claim 3,
The programming is performed by selectively removing the protective film on the branch portion together with the branch portion of the bit line, and by selectively implanting impurities for increasing the threshold voltage of the transistor into the channel region. I'm not programming.

Therefore, the gate insulating film of the transistor is not deteriorated by the program, and the bit line is covered with the protective film until the program is performed even though the branch portion of the bit line is selectively removed. It is possible to prevent the bit line from being corroded.

In addition, the program is performed by selectively removing the branch portion of the bit line and the protective film on the branch portion, and the bit line is the last formed wiring. The programming process is just before the end of the manufacturing process.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A specific example of the present invention will be described below.
This will be described with reference to FIGS. In order to manufacture this specific example, the fishbone type SiO ₂ film 12 shown in FIG. 2 is formed on the surface of the P type or N type Si substrate 11 having a P well shown in FIG. 1A by the LOCOS method. Then, the element isolation region is determined.

After that, the SiO ₂ film 1 as a gate oxide film is formed on the surface of the element active region surrounded by the SiO ₂ film 12.
3 is formed and the deposited polycrystalline Si film 14 is patterned to form a word line. Then, the polycrystalline Si film 14
Using the SiO ₂ film 12 as a mask, N-type impurities are ion-implanted into the Si substrate 11 to form the source diffusion layer 15 and the drain diffusion layer 16. Up to this point, memory cell 1
The transistor 18 forming 7 is completed.

After that, an SiO ₂ film 21 is formed as an interlayer insulating film.
Are deposited by the CVD method, and contact holes 22 for the drain diffusion layers 16 of all the transistors 18 are opened in the SiO ₂ films 21 and 13. Then, the Al film 2 is formed by the sputtering method.
3 is deposited, and the Al film 23 is processed into a pattern of the lead wiring extending from the contact hole 22 to the SiO ₂ film 12 in parallel with the polycrystalline Si film 14.

After that, an SOG film 24 is formed as an interlayer insulating film, and the surface of the SOG film 24 is flattened by etching back together with a flatly applied resist (not shown). Then, a contact hole 25 reaching the Al film 23 on the SiO ₂ film 12 is opened in the SOG film 24, and the contact hole 25 is filled with a plug 26.

After that, the Al film 2 deposited by the sputtering method
7 is processed into a bit line pattern. As apparent from FIG. 2, the Al film 27 extends over the contact hole 22 of each memory cell 17 arranged in the direction perpendicular to the extending direction of the polycrystalline Si film 14, and the contact hole 25 is formed. Each memory cell 17 has a branch portion 27a extending upward.

SiN is used as a protective film for corrosion prevention.
The film 31 is deposited on the entire surface by the plasma CVD method to prepare a wafer before programming. Therefore, in this state, the Al film 27 includes the branch portion 27a, the plug 26, and the A
The drain diffusion layers 16 of all the transistors 18 arranged in the extending direction of the Al film 27 are connected via the l film 23.

Next, when the code data is received from the user, as shown in FIG. 2B, a resist 32 is applied on the SiN film 31, and the drain of the transistor 18 which is not selected is formed by lithography using a program mask 33. An opening 32a is formed in the resist 32 on the branch portion 27a connected to the diffusion layer 16.

Next, using the resist 32 as a mask, FIG.
As shown in FIG. 2C, the SiN film 31 is etched, and subsequently, as shown in FIG.
a is etched to form the Al film 27 on the drain diffusion layer 16
Electrically separated from. After that, the resist 32 is removed, and a SiN film (not shown) as a surface protection film is deposited by the plasma CVD method to program the mask RO.
Complete M.

In the above specific example, as is apparent from FIG. 2D, the branch portion 27a connected to the drain diffusion layer 16 of the unselected transistor 18 and the SiN on this branch portion 27a. Since the programming is performed by etching the film 31, the gate oxide film S
The iO ₂ film 13 is not deteriorated by the program.

In the above specific example, the Al film 27 is connected to the drain diffusion layer 16 via the branch portion 27a, the plug 26 and the Al film 23 before programming.
For example, except on the source diffusion layer 15, the Al film 27 is made of SiO 2.
_By patterning so as to extend over the ₂ film 12, the Al film 27 can be connected to the drain diffusion layer 16 only through the branch portion 27a.

[0024]

According to the mask ROM of the first aspect of the present invention, since the gate insulating film of the transistor is not deteriorated by the program and the programming process is just before the final stage of the manufacturing process, the turn-off is achieved despite the high reliability. Around time is short.

In the mask ROM of the second aspect, the bit line can be extended over the diffusion layer even though the bit line has a branch portion. Therefore, the degree of freedom in patterning the bit line is high. There are many.

According to the method of manufacturing the mask ROM of claim 3,
The gate insulating film of the transistor is not deteriorated by programming, and the bit line is covered with a protective film to prevent corrosion of the bit line, etc. Can be prevented, and
Since the programming step is immediately before the final step of the manufacturing process, it is possible to manufacture a mask ROM having a short turnaround time even though the reliability is very high.

[Brief description of drawings]

1 is a side sectional view showing a method of manufacturing a mask ROM according to an embodiment of the present invention in the order of steps, taken along a line I-I in FIG.

FIG. 2 is a plan view of a mask ROM according to a specific example.

[Explanation of symbols]

 16 Drain Diffusion Layer 17 Memory Cell 18 Transistor 23 Al Film 27 Al Film 27a Branch 31 SiN Film

Claims (3)

[Claims] 1. A bit line has a branch portion electrically connected to one diffusion layer of a transistor forming a memory cell, and the branch portion is selectively cut off. A mask ROM characterized by being programmed by. 2. The wiring connected to the diffusion layer extends in a direction intersecting the extending direction of the bit line, and the branch portion is provided in a portion of the wiring other than on the diffusion layer. The mask ROM according to claim 1, wherein the mask ROM is connected. 3. A step of electrically connecting a branch portion of a bit line to one diffusion layer of a transistor forming a memory cell, a step of covering the bit line with a protective film, and the branch portion. A step of performing programming by selectively removing the protective film on the branch portion.