JPH09331329A - Data discrimination device and cell forming device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decide whether or not a data head position of input structural data and a data head interval detected from each of the structural data are normal. SOLUTION: A structural head decision circuit 42 receives structural data in the order of a 1st structural data 21 and the 2nd structural data 22 in this order and finds out the head of the structure of the 1st structural data. A structural data reception display circuit 43 receiving a structural head signal outputs a reception state display signal. A structural position instruction circuit 44 receiving a load instruction signal conducts down-count every time receiving 1 byte of the structural data and outputs of a cell pointer denoting it in how many bytes the head of succeeding structural data comes from the data received at present. A structural error detection circuit 48 receiving the reception state display signal judges that the structure is normal when the cell pointer is zero at notice of a structure head signal, and informs structural error when the cell pointer is not zero at notice of a structure head signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data determining device and a cell forming device, for example, in a process of forming a cell for ATM (asynchronous transfer mode) communication from structured data of an STM (synchronous transfer mode) communication system. It can be applied to the judgment of normality / abnormality of the head position and head interval of structured data.

[0002]

2. Description of the Related Art In recent years, various technical developments have been made to realize ATM communication. For example, in an ATM network, AAL (ATM adaptation layer)
Packet data (structured data: a unit of data having a certain meaning) from the terminal, which is user information, ST
For example, an M (synchronous transfer mode) signal is divided into 48 bytes and passed to the ATM layer, and a header of 5 bytes is added to form a 53-byte cell.

The functions of the AAL type 1 are division and assembly of user information, processing of cell delay variation, processing of delay due to cell payload assembly, processing of loss and erroneous insertion cells, reproduction of source clock frequency at the receiving side, and reception side. Of the transmission data structure in the network, AAL-PCI (protocol control information) monitoring for bit errors, AAL
Handling PCI bit errors, monitoring user information for bit errors and possible corrective actions.

A technique for forming a cell from the structured data is described in, for example, the literature: ITU-T Recommendation I.S. 363
Technical specifications are recommended as a structured data transfer method. FIG. 2 shows an A for forming cells from structured data.
It is a conceptual diagram of processing of AL type 1. In FIG. 2, first, X-byte data 21 having the first meaning
When a block of data is input to the AAL type (1) processing circuit 1 and then the second X-byte data 22 is input, the AAL type (1) processing circuit 1 outputs the first structured data 21. The boundary 23 of the structured data between the second structured data 22 and the second structured data 22 is detected, and this boundary 23 forms the position from the beginning of the first structured data in the pointer field 32 of the ATM cell 31. After setting, the first structured data and the second structured data are set to A
The ATM cell 31 is accommodated in the payload portion 33 of the TM cell 31, and the cell header 34, the SAR header 35, and the like are accommodated to form the ATM cell 31. That is, the pointer of the pointer field 32 is information indicating from which byte position of the payload the head of the second structured data is stored.

[0005]

However, although it is required that the pointer of the pointer field 32 accurately points to the first byte 36 of the second structured data, the reception at the AAL type (1) processing circuit 1 is required. At
It may be difficult to accurately identify the boundary 23 of the structured data due to bit fluctuations or bit errors of the structured data. As a result, an incorrect boundary is detected and the pointer of the pointer field 32 is set to an incorrect value. There is a problem that it will end up.

Further, due to an error in the input structured data,
Although the number of bytes of the input structured data is, for example, 100 bytes, the structure head may be detected, for example, every 110 bytes, or the value of the pointer may always point to a byte position deviated from the structure head. Obtained. When the value of the pointer becomes inaccurate in this way, there is a problem in that the structured data in the cell is decomposed from an incorrect byte position. Further, the number of bytes of the input structured data is set in advance by the AAL type (1) processing circuit 1
It was not possible to detect it even if it was different from the number of bytes set in.

From the above, the data start position of the input structured data (in addition, word data as a significant unit, frame data, etc. are included) and the data start interval detected for each structured data. And a cell forming device that can accurately generate the convergence sublayer display data or pointer of a cell for ATM communication by using the data determination result. Has been requested.

[0008]

Therefore, in the data judging device of the first invention, the first data and the second data have the same data length respectively, and after the first data,
Whether the second data is continuously serially input, and the start position of the second data and the start interval between the start of the first data and the start of the second data are normal. To determine. The first data and the second data are, for example, structured data (for example, voice data, other data) in the STM communication system, word data, channel data as a meaningful unit in itself,
Frame data etc. are applicable.

Specifically, the present invention detects the data at the beginning of the first data and the second data and outputs a data beginning detection signal, and a beginning of the first data. When the data of is detected, the data receiving signal indicating that the data is being received is output until the data of the beginning of the next second data is received, and the data receiving signal is forcibly output when the initialization instruction signal is given. From the data receiving signal output means to be stopped and the data position at the time of current reception after detecting the data at the beginning of the first data,
Counting means for counting and outputting the next data prediction distance value to the data position of the head portion of the next second data, and the detected second
Data of the beginning part of the data of, the data receiving signal,
And a determining unit that determines whether or not the start position and the start interval of the second data are normal based on the next data prediction distance value and, if not, generates and gives an initialization instruction signal.

With such a configuration, the data at the head portion of the first data is detected and a data head detection signal is output, thereby outputting the data receiving signal of the first data,
After the detection of the data of the first part of the first data, in the reception process from the received data to the detection of the data of the first part of the second data, from the data position at the time of the current reception to the next second data. Finally, the next data prediction distance value to the data position of the head portion of the data of A becomes 0 from A when the data length is A. When it becomes 0, when the data is being received and the start position signal of the second data is detected, the start of the second data is normally separated from the start position of the first data by the data length A. It can be judged that the data of the part is detected.

When the next data prediction distance value is 0,
Even during reception, when the head position signal of the second data is not detected, it is determined that the signal is not normal, an initialization instruction signal is generated, and the data reception signal output means is initialized to output the data reception signal. Stop output. As a result, when the data at the beginning of the next data is detected, the data can be immediately received.

Due to the relationship between the first data and the second data, the start position of the second data and the start interval between the start positions of the first data and the second data are normal. However, it is natural that subsequent data such as the third data continues after the second data. In this case, the second data is replaced by the first data. Then, the third data that comes after that is regarded as the above-mentioned second data, and in the same manner, the start position of the third data and the second data
The same can be applied by determining whether or not the leading interval between the leading position of the data of 3 and the leading position of the third data is normal.

Further, the above-mentioned first data and second data can be regarded as frame data, respectively. In this case, the start position of the second frame and the first data
The same can be applied by determining whether the head interval between the head of the frame data and the head of the second frame data is normal. In addition, the first data and the second data may be regarded as multi-frame data, and in this case, the first multi-frame first frame composed of a plurality of frames and the first multi-frame composed of a plurality of frames. It is also possible to determine whether the head frame interval between the head frame of the second multi-frame and the position of the head frame of the second multi-frame is normal.

Further, in the data judging device of the second invention, the second data having the time slot number B (B ≠ A) is continuously serially input after the first data having the time slot number A. , The head position of the second data and the head interval between the head of the first data and the head of the second data are normal.

That is, according to the present invention, the time slot information of the first data and the second data, and the first data and the second data.
Information identification information and the head position information of the first data and the second data are stored and managed in advance, and the number of time slots of the input data is detected. The management means is searched to select the identification information of the first data and the second data and the head position information of the first data and the second data, and the first data and the second data are selected from these information. Of the first part of the first data is detected, and the data of the first part of the first data is detected, and the data of the first part of the second data is received. A data receiving signal indicating that the data is being received, and forcibly stopping the data receiving signal when an initialization instruction signal is given, and a data receiving signal outputting means for outputting a data at the beginning of the first data. After detecting the data, the information management means stores and manages the predicted number of time slots from the time slot position of the data currently being received to the time slot position of the data at the beginning of the next second data. Of the second data from the counting means for counting and outputting based on the present time slot information, the data of the head portion of the detected second data, the data receiving signal, and the predicted number of time slots. And a determination unit that determines whether or not the start position and the start interval are normal and, if not, generates and gives an initialization instruction signal.

With such a configuration, even when the number of time slots of the first data and the number of time slots of the second data are not the same, the start position of the second data and the start position of the first data are It is possible to determine whether or not the leading interval with the leading position of the second data is normal.

Further, a third invention is provided with the above-mentioned data judging device, and when the start position of the second data and the start interval are normal, the next data prediction distance value of the first invention or And generating a convergence sublayer display data or pointer for displaying the boundary or the beginning of the structured data by using any one of the predicted number of time slots of the invention of claim 2; And a cell forming means for accommodating to form a cell.

With such a configuration, it is possible to determine whether or not the first data and the second data are normal, and then generate highly reliable convergence sublayer display data or pointers, and finally a cell of high quality. Can be formed.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a preferred embodiment of the present invention will be described with reference to the drawings. In this embodiment, IT
UT Recommendation I. Structured data shown in 363 is ATM
In a device for making cells, a means for detecting an abnormality at the time of transferring structured data by comparing the start byte position of the structured data with a pointer value generated internally, displaying during reception of structured data, initial reception of structured data And a means for controlling the conversion.

[First Embodiment]: FIG. 1 is a functional block diagram of a structured data transfer apparatus according to the first embodiment.
In FIG. 1, the structured data transfer device 41 includes a structure head determination circuit 42, a structure data reception display circuit 43, and
Structure position indicating circuit 44 and structure byte number table circuit 4
5, a sequence number generation circuit 46, a CSI bit generation circuit 47, a structural abnormality detection circuit 48, a control circuit 49, and an ATM cell conversion circuit 50.

The structured data transfer device 41 fetches the first structured data 21 and the second structured data 22 each having an X-byte length, counts them, and outputs the structured data 21 and 22. The boundary 23 between
Whether or not the detected boundary is normal is determined, and if normal, a pointer is generated based on the detected structure start position, and the structured data 2 is placed at a position corresponding to the value of this pointer.
1 and 22 are accommodated to form an ATM cell. If the detected boundary is abnormal, the structured data reception count is initialized, cell generation is stopped when an abnormality is detected, and the structured data reception count is initialized.
The structured data reception count is restarted again.

The structure head determination circuit 42 receives the first structured data 21 and the second structured data 22 in this order, and receives the structure head of the first structured data (for example, 1
Flag signal included in byte, sync pattern, etc.)
Then, the structure head signal is supplied to the structure data reception display circuit 43 and the structure abnormality detection circuit 48. The structure data reception display circuit 43 is first initialized by the initialization instruction signal from the control circuit 49 to be in a non-reception (off) display state indicating that the structured data is not received, while the structure head is displayed. When the signal is given from the structure head determination circuit 42, a receiving (ON) display signal indicating that the reception of the structured data is started is output, and the CSI bit generation circuit 47, the structure position indication circuit 44, and the structure abnormality detection circuit. 48
When the non-reception (off) display state changes to the reception (on) display state, a load instruction signal is output and given to the structure position instruction circuit 44.

The structured byte number table circuit 45 first receives information on the number of bytes of the structured data from the control circuit 49, and based on this information, gives the structured position indicating circuit 44 the number of structured data bytes. Structure position indicating circuit 44
Is mainly composed of a down counter, and when receiving a load instruction signal from the structure data reception display circuit 43, the structured data byte number is fetched from the structure byte number table circuit 45 and a receiving (ON) display signal is received. When given from the display circuit 43, a down-count operation is performed every time one byte of structured data is received, and a cell pointer value indicating how many bytes ahead of the data the head of the next structured data is currently received. To output CSI bit generation circuit 4
Give to 6.

The sequence number generation circuit 46 creates a sequence number and supplies it to the CSI bit generation circuit 47. This sequence number is used to detect an error by allocating, for example, a modulo 16 serial number on the transmitting side using the sequence number field of the ATM cell, and checking the continuity on the receiving side. In order to perform the convergence sublayer display, the CSI bit generation circuit 47 displays the boundary of the structured data by the 1-byte pointer or the head of the code block in the error correction when the sequence count is an even number, and the sequence count is SRTS if odd
The source clock is reproduced by the method. This SRTS method is based on Synchronous Residual Ti.
Abbreviation for me Stamp (synchronous residual time stamp),
By transferring the difference (residual) from the network clock,
In this method, the information generation clock on the transmitting side is reproduced on the receiving side.

The CSI bit generation circuit 47 receives a receiving (ON) display signal from the structure data reception display circuit 43, a cell pointer value from the structure position designating circuit 44, and a sequence number to the sequence number generation circuit 46. Is given, CSI bits and pointer field data are created and given to the ATM cell assembling circuit 50.
Further, the CSI bit generation circuit 47 stops generation of the CSI bit when the generation stop signal is given from the structural abnormality detection circuit 48, and when the initialization instruction signal is given from the control circuit 49, this circuit 47. After initializing CSI, CSI generation is restarted. The ATM cell conversion circuit 50 is
ATM cells are formed by multiplexing CSI bits, pointer field data, and other header SAR (cell division / assembly) headers and structured data.

The structural abnormality detection circuit 48 is receiving (ON)
When the display signal is given from the structure data reception display circuit 43, the cell pointer value at the time of notification of the structure start signal is 0.
If the cell pointer value at the time of notifying the structure start signal is not 0, the control circuit 49 is notified of the structure abnormality and the CSI bit generation circuit 47 is detected.
To stop the generation. Further, even if the cell pointer value is 0, the structural abnormality detection circuit 48 determines that there is a structural abnormality when the structural head signal has not been notified, notifies the structural abnormality notification to the control circuit 49, and stops generation of the CSI bit generation circuit. Give to 47. The control circuit 49 first
Information on the number of bytes of each structured data to be received is given to the structure byte number table circuit 45, and thereafter, when a structure abnormality notification is received from the structure abnormality detection circuit 48, an initialization instruction signal C
SI bit generation circuit 47 and structure data reception display circuit 4
3 and 3 to be initialized.

(Operation): Next, the operation of the structured data transfer apparatus of FIG. 1 will be described with reference to the timing chart of FIG. In the timing chart of FIG. 3, the byte length (number) of each input structured data is illustrated as 4 bytes. First, prior to receiving structured data from the control circuit 49, information on the number of bytes of each structured data is given to the structure byte number table circuit 45, and an initialization instruction signal is sent to the structure data reception display circuit 43 and the CSI. It is given to the bit generation circuit 47 and is initialized. Accordingly, in the structure byte number table circuit 45,
In the case of FIG. 3, it is set that the number of bytes of each structured data is 4 and is given to the structure position designating circuit 44.

When the first structured data 21 (b) is supplied to the structure head determination circuit 42, the byte position of the structure head is determined according to the internal clock (a), and the structure head signal (c) is the structure data. It is given to the reception display circuit 43 and the structural abnormality detection circuit 48. The structure data reception display circuit 43 supplied with the structure head signal (c) outputs a receiving (ON) display signal and the CSI bit generation circuit 47.
And the structural abnormality detection circuit 48. At the same time, when changing from the non-reception (off) display state to the reception (on) display state, a load instruction signal is output and given to the structure position instruction circuit 44.

The structure position designating circuit 44 supplied with this load designating signal loads the number of bytes (4 bytes in the case of FIG. 3) from the structure byte number table 45, and outputs the cell pointer value as 0 at this point. Then, when the receiving (ON) display state continues, 1 is set according to the cycle of the clock (a).
The countdown operation is performed for each byte received, and in the case of FIG. 3, it is counted down as 3 → 2 → 1, and the value of the boundary with the next second structured data is a number of bytes ahead of the currently received data. Is output as a cell pointer value (d) for notifying whether or not it is present in the CSI bit generation circuit 47 and the structural abnormality detection circuit 48.

The structural abnormality detection circuit 48 is receiving (ON)
Structure head signal (c) when display signal is given
And the cell pointer value (d), 0 match,
Judge that the structure is normal. Then, the CSI bit generation circuit 4
At 7, CSI bits and pointer fields are generated,
It is applied to the ATM cell conversion circuit 50 to form an ATM cell. Further, the second structured data is received following the first structured data.

On the other hand, when the structured data is abnormal when the receiving (ON) display signal is given, for example, as shown in FIG. When it is detected when the pointer value is 1 (f1), or when the structure head (e2) is not detected when the cell pointer value is 0 (f2), it is determined that the structure is abnormal, and the structure abnormality notification is issued to the control circuit. At the same time, the generation stop signal is supplied to the CSI bit generation circuit 47 to stop the generation of the CSI bit.

Further, when the control circuit 49 receives the structural abnormality notification, it gives the initialization instruction signal to the CSI bit generation circuit 47 to initialize the CSI bit generation, and at the same time, sends the initialization instruction signal to the structure data reception display circuit 43. To the non-receiving (off) display state, and then wait until the next structure head signal is given. When the second structured data is received and the structure start signal is given to the structure data reception display circuit 43, the receiving (ON) display signal is output again, and the same operation as described above is performed to detect the structural abnormality. Make a decision. Therefore, immediately after the initialization is instructed, the system can be ready to detect the structure head of the next structured data.

Depending on the cause of the structural abnormality, the control circuit 49 may give new byte number information to the structural byte number table circuit 45 and cause the structural position indicating circuit 44 to output the cell pointer value.

(Effects of the first embodiment of the present invention):
According to the above-described embodiment of the present invention, the head of each input structured data is detected, and whether the length of each structured data is normal or not is determined by comparing the current structured data and the next structured data. It is possible to determine whether or not the boundary with the data is the normal position. If not normal, control circuit 49
However, since the initialization instruction signal is given to the CSI bit generation circuit 47, the CSI bit is not generated in a structurally abnormal state.

Further, by applying the initialization signal to the structure data reception / display circuit 43 for initialization, it is immediately possible to judge whether or not the structure data to be inputted next is being received. The judgment of normality / abnormality of data can be restarted in a short time. Therefore, the amount of structured data to be discarded can be minimized. Further, since the structure head is detected, it is possible to determine the normality in the shortest time.

[Second Embodiment]: In the first embodiment described above, each structured data to be input is set to a predetermined X-byte length, and it is determined whether the input structured data is normal or abnormal. Although the configuration has been described, in the second embodiment, a configuration for determining the presence / absence of normality / abnormality of the input structured data when the lengths of the respective input structured data are different will be described. .

FIG. 4 is a functional block diagram of the structured data transfer device 41A. In FIG. 4, the structured data transfer device 41A includes a structure head determination circuit 42A, a structure data reception display circuit 43A, a structure position designating circuit 44A, a structure byte number table circuit 45A, and a sequence number generation circuit 46A. CSI bit generation circuit 47A, structural abnormality detection circuit 48, control circuit 49, ATM
Cellizing circuit 50, time slot / logical channel conversion table circuit 51, and load memory circuits 43B and 44
B, 45B, 46B, 47B. In this figure, the same reference numerals are given to the components having the same functions as the components in FIG. 1 described above.

FIG. 5 is a diagram for explaining the function of the time slot (TS) / logical channel conversion table circuit 51. In FIG. 5, the first structured data and the second structured data that are input are represented by time slots TS0 to TSn, TS0 to TS2 are the first structured data, and TS3 to TSn. Is the second structured data. These first structured data and second
The received frame is composed of the second structured data.

Further, in FIG. 5, in the structured data transfer device 41A, TS0 to TS2 are assigned to logical channels (identification information) chA1 to chA3 in order to facilitate internal processing of structured data having different byte lengths. Is expressed as
TS3 to TSn are represented by logical channels chB1 to Bm.
Moreover, TS0 and TS3 are set as the structure top (Top) of the structured data. The time slot / logical channel conversion table circuit 51 presets and manages the relationship among such time slots, logical channels, and structural heads. Upon receiving the received frame, the structure head determination circuit 42A supplies the time slot number of the received frame to the time slot / logical channel conversion table circuit 51, and outputs the logical channel ch and the structure head information from the table circuit 51. Is given, the structure head signal is given to the structure data reception display circuit 43A and the structure abnormality detection circuit 48, and the logical channel signal is given to each part. This logical channel (ch) signal is sent to the structural data reception display circuit 43A,
Structure position indication circuit 44A, structure byte number table circuit 45A, sequence number generation circuit 46A, CSI
And bit generation circuit 47A.

Load memory circuits 43B, 44B, 45
B, 46B, and 47B perform the same function. Therefore, the function of the load memory circuit 43B will be described with reference to FIG. The load memory circuit 43B sets the states (for example, the structure head receiving state, non-receiving state, etc.) for the logical channels A1 to A3 and B1 to Bm in advance. When a structure head signal is given to the structure head judgment circuit 42A and a logical channel is designated, the state set for the logical channel is read out and given to the structure head judgment circuit 42A.

The structure head determination circuit 42A outputs a structure head receiving (ON) display signal by using the read state while receiving the structure head signal, and the state after this processing is loaded into the load memory again. It is stored in the circuit 43B. The state of each logical channel is temporarily stored. The other load memory circuits 44B, 45B, 46B, and 47B also temporarily store the state of each logical channel, as in the load memory circuit 43B. Each memory content is different. That is, the load memory circuit 44B stores the cell pointer value for each logical channel. Load memory circuit 4
5B stores the number of structured bytes for each logical channel.
The load memory circuit 46B stores information on generation of a sequence number for each logical channel. The load memory circuit 47B stores information for generating a CSI bit for each logical channel.

(Operation): Next, the operation of FIG. 4 will be described. First, the control circuit 49 initializes the logical channel of each load memory circuit, initializes the structure data reception display circuit 43A, and puts it in the non-receiving state.
The generation of the CSI bit generation circuit 47A is initialized. Next, when the received frame is given to the structure head determination circuit 42A, the time slot number is detected and given to the time slot / logical channel conversion table circuit 51.

As a result, the time slot / logical channel conversion table circuit 51 outputs the corresponding logical channel number and the structure head presence / absence information, and supplies it to the structure head determination circuit 42A. The structure head determination circuit 42A gives a logical channel to each section, outputs a structure head signal when the structure head is recognized from the structure head presence / absence information, and outputs the structure data reception display circuit 43A and the structure abnormality detection circuit 48. Give to. In the case of FIG. 5, this structure head signal is
It is output to the logical channel A1 and the logical channel B1.

The structure start signal is the structure data reception display circuit 4
3A, first the load channel circuit 43B is loaded by the logical channel A1 to read the state, a load instruction signal is given to the structural position instruction circuit 44A, and a receiving (ON) display signal is given to the CSI bit generating circuit 4A.
7A, the structure position indicating circuit 44A, and the structure abnormality detecting circuit 48. The structure position designating circuit 44A, to which the load designating signal is applied, fetches the structure byte count for the logical channel A1 from the structure byte count table 45A and receives the receiving (ON) display signal using the load memory circuit 44B. In the meantime, a countdown is performed every 1 byte received, and the load information is reduced by -1 byte and stored in the load memory circuit 44B. Logical channels A1 to A3
Is received while receiving the next structured data (logical channels B1 to B) from the current received data.
The number of bytes ahead up to the boundary of m) is output as a cell pointer value and given to the CSI bit generation circuit 47A and the structural abnormality detection circuit 48.

In the CSI bit generation circuit 47A, while the receiving (ON) display signal is given, the CSI bit and the pointer field are generated from the cell pointer value and the sequence number from the sequence number generation circuit 47A, and the ATM is generated. It is applied to the cell assembling circuit 50 to form an ATM cell.

The structural abnormality detection circuit 48 is receiving (ON)
When the structure start signal and the cell pointer value match when the display signal is given, it is determined that the structure is normal. Then, the CSI bit generation circuit 47A generates the CSI bit and the pointer field and supplies them to the ATM cell conversion circuit 50 to form an ATM cell. Furthermore, following the first structured data (logical channels A1 to A3), the second structured data (logical channels B1 to B3) is continued.
m) is received.

On the other hand, when the structured data is abnormal when the receiving (ON) display signal is given, or when the timing of the structure start signal for each logical channel and the cell pointer value (0) do not match. Judges that it is a structural abnormality and gives a structural abnormality notification (including an abnormal logical channel number) to the control circuit 49, and at the same time sends a generation stop signal to CS.
It is given to the I bit generation circuit 47A to stop the generation of the CSI bit.

Further, when the control circuit 49 receives the structural abnormality notification, it gives the initialization instruction signal to the CSI bit generation circuit 47A to initialize the CSI bit generation, and at the same time, sends the initialization instruction signal to the structure data reception display circuit 43A. To the non-reception (off) display state, and then waits until the structure head signal of the next logical channel B1 is given. Second structured data (logical channels B1 to B
m) is received and the structure head signal is given to the structure data reception display circuit 43A, the load memory circuit 43 is again supplied.
A receiving (ON) display signal is output using B, and the same operation as described above is performed to determine the structural abnormality. Therefore, immediately after the initialization is instructed, the system can be ready to detect the structural head of the next structured data (logical channels B1 to Bm). (Effects of the Second Embodiment of the Present Invention): According to the above-described embodiments of the present invention, even if the byte length of each structured data is not the same, time slot (TS) / logical channel conversion is performed in advance. By creating the table circuit 51 and performing structural abnormality determination for each logical channel in the same manner as in the above-described first embodiment, the abnormality determination can be accurately performed. Further, it is possible to determine whether or not the length of each structured data is normal, whether the boundary between the current structured data and the next structured data is a normal position, and the like. If it is not normal, the control circuit 49 gives the initialization instruction signal to the CSI bit generation circuit 47A for each logical channel, so that the CSI bit is not generated in a structurally abnormal state.

Further, by applying the initialization instruction signal to the structure data reception / display circuit 43A for initialization, it is immediately possible to judge whether or not the structure data (logical channel) to be inputted next is being received. It is possible to restart the judgment of normality / abnormality of the input structured data in a short time only by initializing the abnormal logical channel. Therefore, the amount of structured data to be discarded can be minimized. Further, since the structure head is detected, it is possible to determine the normality in the shortest time.

(Other Embodiments) (1) In the above second embodiment, a structure abnormality judgment configuration is adopted in the case where received frames in which the byte lengths of structured data are not the same are input. As shown above, as other input signal forms,
ITU-T Recommendation G. 709 (JT-G709) can also be applied to the case of receiving a TU (tribitary unit) -11/2 multiframe signal, and specifically, the leading frame of the multiframe signal is determined. By adding the condition (configuration), it is possible to determine whether the byte length or the structural head of each structured data is normal even if the number of structured bytes of the multi-frame exceeds the number of bytes that configure one frame. .

(2) In the first embodiment, the input structured data is ITU-T Recommendation I.S. 363
The input data used in, in a simple example, 1
It can be applied as audio data or image data for each sample without any problem. Further, the circuit configuration for determining the presence / absence of a structural abnormality in the input data in the above-described embodiment needs to determine whether the start position and the start interval of the input data are normal, in addition to the above-described ATM cell formation. Can be widely applied to any device that has.

(3) Further, the load memory circuit of the second embodiment described above can be configured by a plurality of registers and can be realized by a simple circuit. Further, the logical channel used in the second embodiment can be broadly regarded as the identification information of each structured data.

[0053]

As described above, according to the data determining apparatus of the present invention, when the second data is continuously serially input after the first data, the start position of the second data and It is possible to quickly determine with a simple configuration whether or not the head interval between the head of the first data and the head of the second data is normal. Further, it is possible to realize a highly reliable cell forming device by using this data determination device.

[Brief description of drawings]

FIG. 1 is a functional configuration diagram of a structured data transfer device according to a first embodiment of this invention.

FIG. 2 is an explanatory diagram of cellization of structured data in AAL type 1 of a conventional example.

FIG. 3 is an operation timing chart of the structured data transfer device according to the first embodiment.

FIG. 4 is a functional configuration diagram of a structured data transfer device according to a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a time slot / logical channel conversion table circuit of the structured data transfer device according to the second embodiment.

FIG. 6 is a functional explanatory diagram of a load memory circuit of the structured data transfer device according to the second embodiment.

[Explanation of symbols]

21 ... First structured data, 22 ... Second structured data, 31 ... ATM cell, 41 ... Structured data transfer device, 42 ... Structure head determination circuit, 43 ... Structure data reception display circuit, 44 ... Structure position designating circuit, 45 ... Structure byte number table circuit, 46 ... Sequence number generating circuit, 4
7 ... CSI bit generation circuit, 48 ... Structural abnormality detection circuit,
49 ... Control circuit, 50 ... ATM cell circuit.

Claims (3)

[Claims] 1. The first data and the second data each have the same data length, and the second data is continuously serially input after the first data, and the second data
A data determination device for determining whether or not the start position of the first data and the start interval between the first data and the second data are normal. And a data head detecting means for detecting the data of the head portion of the second data and outputting a data head detection signal; and detecting the data of the head portion of the first data, the head portion of the next second data is detected. A data receiving signal outputting means for outputting a data receiving signal indicating that data is being received until data is received, and forcibly stopping the output of the data receiving signal when an initialization instruction signal is given; Counting means for counting and outputting the next data prediction distance value from the data position at the time of the current reception to the data position of the leading part of the next second data after detecting the data of the leading part of the data; Shi Further, it is determined whether the start position and the start interval of the second data are normal from the data of the start portion of the second data, the data receiving signal, and the next data prediction distance value. A data determination device comprising: a determination unit that generates and gives the initialization instruction signal when the data is not normal. 2. A second data consisting of a time slot number B (B ≠ A) after a first data consisting of a time slot number A.
Data is continuously serially input, and the start position of the second data, the start position of the first data and the second position
Of the first data and the second data, the first data and the second data, and a data determination device that determines whether or not a leading interval between the first data and the first data is normal. Data identification information, and information management means for storing and managing in advance the head position information of the first data and the second data, and the number of time slots of the input data is detected, and the above information is calculated from this number of time slots. The management means is searched to select the identification information of the first data and the second data and the head position information of the first data and the second data, and the first data and the second data are selected from these information. Data head detecting means for detecting the data of the head portion of the first data and outputting a data head detecting signal, and when the data of the head portion of the first data is detected, the data of the head portion of the next second data is received. Until A data receiving signal indicating that the data is being received, and forcibly stopping the output of the data receiving signal when an initialization instruction signal is given, and a head portion of the first data. After detecting the data of No. 2, the predicted number of time slots from the time slot position of the data at the time of the current reception to the time slot position of the data of the head portion of the next second data is stored by the information management means. The counting means for counting and outputting based on the managed time slot information, the data of the leading portion of the detected second data, the data receiving signal, and the predicted time slot number And a determination unit that determines whether or not the head position of the data and the head interval are normal and, if not, generates and gives the initialization instruction signal. Data determination device. 3. The next data prediction distance value according to claim 1, or the data determination device according to claim 1, further comprising: when the start position and the start interval of the second data are normal. Using any of the predicted number of time slots described in Item 2, generating means for generating convergence sub-layer display data or pointer for performing boundary display or head display of structured data, and the convergence sub-layer display data or pointer. A cell forming device, comprising: a cell forming means for accommodating and forming a cell.