JP2985844B2 - ATM receiver - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM receiving apparatus having a packet timeout detecting function.

[0002]

2. Description of the Related Art ATM (Asynchronous Transfer Mode), which is a multiplex transfer system for digital information in B-ISDN (Broadband ISDN), does not need to synchronize the transfer with the bit rate of the network, so that the amount of information to be transferred is adjusted. It is widely used for high-speed and broadband communication services because it can perform efficient processing. FIG. 4 shows the configuration of an ATM network in which a plurality of ATM terminals 21a to 21c are connected to a plurality of AT terminals.
It is composed of an ATM communication controller connected to a plurality of ATM servers 22a and 22b via M switches 22a to 22c. On the transmitting side of each ATM communication apparatus, as shown in FIG. 5, a packet is decomposed into ATM cells each having a 5-byte header and a 48-byte payload, and transmitted over a line. In the header of the ATM cell, VPI /
A number for identifying a virtual connection called VCI is embedded, thereby realizing communication between transmitting and receiving terminals of the cell.

In such an ATM network,
Due to some abnormality of the line or the device, the cell of this packet of a certain connection may be delayed or discarded, and may not reach the receiving end until the end. Therefore, in order to end the processing of this connection, A
It is necessary to detect the timeout of the TM packet.

Conventionally, this type of ATM reception packet time-out detection unit has been disclosed in, for example, "User's Manual μ".
PD98401 Local ATM SAR chip (NE
As shown in "ASCOT-S10)", the receiving side of the ATM communication control device defines the time required for assembling the packetized ATM cell, and monitors whether the time exceeds the allowable time by hardware. When a timeout is detected, it is used to notify the upper layer of the timeout.

FIG. 6 is a block diagram showing an example of an ATM communication control device.

[0006] The ATM communication control device includes a device PHY 28 having an ATM physical layer function and a received ATM.
Judgment of reception based on the value of VPI / VCI in the header of the cell, identification number of VPI / VCI (hereinafter referred to as VC)
SAR (Segmentation AndR) that performs conversion to ISA, various types of error verification, and packet assembly
(Eassembly) receiving unit 24, SAR transmitting unit 25 that performs ATM cell disassembly of a packet to be transmitted and control of the transmission cell rate, and SAR receiving unit 24 and SA
A control memory 27 for storing various types of information (such as an address in a DMA and a flag of a first cell) used by the R transmitting unit 25; a SAR receiving unit 24 and an SAR transmitting unit 25;
For controlling the interface between the CPU and the system bus 31 to which the CPU 29 and the system memory 30 are connected.
And a controller 26.

When a cell is received, the SAR receiver 24 determines the value of VPI / VCI in the header. The payload of the reception cell for which reception is permitted is read out by the DMA controller 26 and DMA-transferred to the system memory 30 via the system bus 31.

FIG. 7 is a block diagram of a conventional device for detecting a timeout of an ATM reception packet.

The time-out detecting device for the ATM received packet is provided in the SAR receiving section 24 and includes a T1 register 16 for setting an allowable time-out time for a time-out and a TS register for storing the start time of "the VC which has started receiving most recently". 17
A timer unit 6 comprising an adder 10 for adding the value of the T1 register 16 and the value of the TS register 17 and a counter 7 incremented in synchronization with a system clock 19 supplied from the system bus 31 side. And a comparator 18 for comparing the output value of the adder 10 with the counter value of the timer unit 6.

The control memory 27 has a configuration (hereinafter referred to as a VC table) for storing information of each VC by dividing the area in units of VCs. As parameters related to timeout detection in the VC tables 15a to 15c, timeout detection is enabled,
The E bit for linking to the link list, the reception start time of the packet, that is, the arrival time (TS) of the head cell of the packet, and the forward / backward for forming the link list.
There is a backward pointer (EP / BP).

The SAR receiving unit 24 further includes a header / payload for separating the header of the received cell from the payload.
And a VPI extracted from the header of the received cell.
/ VCI that converts / VCI to the corresponding VC
It has an I-VC converter 12 and a reception data FIFO 13 for storing the payload of a reception cell until the time of DMA.

Next, the operation will be described.

The detection of a timeout of a received packet is performed by V
This is performed by a linked list system formed using forward / backward pointers (FP / BP) in the C table. These pointers store the VC number for which reception was started earlier and the VC number for which reception was started later.

When a cell is received, the V corresponding to the received VC
Read the E bit from the C table. When the E bit is set and the cell is the head of a new packet, the counter value of the timer section 6 at that time is written to the TS area of the VC table corresponding to this VC as the current time. If there is no VC in the link list, the data is similarly written to the TS register 17 at this time. After updating the pointer of the VC table,
Is added to the end of the link list. In other words, the link list is always linked such that "the VC which has started receiving the earliest" is linked to the head and "the VC which has started receiving the link most recently" is linked to the end.

When the last cell of the packet arrives within the allowable time-out period set in the T1 register 16, the VC and the pointers of the preceding and following VCs are updated, and this VC is removed from the link list. If “the VC that has started receiving the earliest” is deleted from the link list, the VC register that links the TS register 17 to the next VC is deleted.
Is rewritten with the reception start time.

Therefore, the first time-out is detected in the VC at the head of the link list, that is, the “VC that has started receiving the earliest”, and the reception of this VC written in the TS register 17 is performed. A value obtained by adding the start time and the allowable time for timeout set in the T1 register 16 by the adder 10 is input to the input terminal A of the comparator 18, and the counter value of the timer unit 6 indicating the current time is input to the comparator 18. Timeout can be detected by inputting to the input terminal B and comparing. When the inputs to the input terminals A and B of the comparator 18 are equal to each other, it means that the timeout has been detected in the “VC that has started receiving the earliest”.

[0017]

However, the above-described conventional detection apparatus has a problem that timeout detection cannot be performed in accordance with the cell rate and packet length of each VC. That is, in FIG. 7, for example, the time required for each VC packet to be normally received and assembled is represented by VCi:
2 msec, VCj: 4 msec, VCk: 8 msec
Is set to 8 ms.
ec. In this case, even if the VCi packet is received in 5 msec, the timeout is not detected. Also, VCi is actually
8 mse even if the cell is discarded and reception is not completed
Until c has elapsed, timeout detection cannot be performed. Therefore, accurate timeout detection cannot be performed for each VC.

The reason is that the timeout allowable time of a received packet can be set to only one value for a plurality of VCs.

An object of the present invention has been made in view of the above-described points, and an ATM communication control apparatus has a structure in which each reception V
A method and apparatus for detecting a timeout which can accurately detect a packet assembling time for each received VC in accordance with the C cell rate and packet length, that is, the time from the reception of the first cell to the last cell. Is to provide.

[0020]

In order to achieve the above-mentioned object, according to the present invention, an ATM receiver is constituted as follows. That is, a header / payload separation unit that separates a header and a payload of each ATM cell of a received packet, a reception data storage unit that stores the payload, and reads the payload from the reception data storage unit.
DM to the system bus to which U and system memory are connected
A DMA controller for A transfer, and a VPI / VCI-converting VPI / VCI extracted from the header to VC.
A plurality of VC tables which are connected to the VC conversion section and which are connected to the VPI / VCI-VC conversion section and which store a timeout allowable time corresponding to the VC and a first E bit for setting whether or not to perform timeout detection; A timer unit for outputting a reception time of each of the ATM cells; and an adder for adding the time output from the timer unit and the timeout allowable time read from a VC table corresponding to the VC of each of the ATM cells. A selector for selecting and outputting one of the output value of the adder and the time output from the timer, and decoding the VC by a decoder;
The output value of the adder corresponding to the VC is written via the selector, and when the written output value matches the time output from the timer unit, the output value matches with the match signal via the encoder. A plurality of CAM cells that output a match address indicating whether the
A second state is provided for each of the plurality of CAM cells, and is set to a first state when a first cell is received, and to a second state when a last cell is received or when the coincidence signal is detected. And the E bit of the above.

The system further comprises means for dividing a system clock, and a selector for selecting a signal for incrementing a counter value in the timer unit by a time resolution selection code supplied from the outside, and controlling one unit time of the timer unit. The above-described ATM receiving apparatus has a frequency dividing means.

The timeout period of the ATM reception packet can be set for each reception VC, so that the timeout detection is performed according to the cell rate and packet length of each VC.
It can be performed accurately in C units. Further, since the CAM is used for detecting the timeout, the circuit scale can be reduced.

Further, since the frequency dividing circuit is provided, the unit time of the timer unit can be changed, and it is possible to cope with a packet received at a low rate or a packet having a long packet length.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of a timeout detecting device according to the present invention.

The time-out detecting device for the ATM received packet shown in FIG. 1 is the same as the ATM communication control device shown in FIG.
The AR receiver 24 has a selector 2 for switching input data according to a write / search mode, a cell array 3 for registering a timeout detection time, and an address for writing / reading the contents of the cell array 3 from the received VC. CAM 1 comprising an address decoder 4 for reading, a priority encoder 5 for outputting a match signal and a match address from the output of the cell array, a write / search mode switching unit 9, and a system bus 31. The timer unit 6 includes a counter 7 that is incremented in synchronization with the supplied system clock 19, and an adder 10 that adds the timeout allowed time of each VC and the counter value of the timer unit 6. You.

The control memory 27 divides the area in units of VC and stores information on each VC. VC te
The parameters related to timeout detection in the cables 14a to 14c include an E bit for enabling timeout detection and a timeout period (T1) for a received packet.

The SAR receiver 24 further includes a header / payload for separating the header of the received cell from the payload.
And a VPI extracted from the header of the received cell.
/ VCI that converts / VCI to the corresponding VC
It has an I-VC converter 12 and a reception data FIFO 13 for storing the payload of a reception cell until the time of DMA.

Next, the operation will be described.

In the present invention, the detection of the timeout of the received packet is performed by using the CAM. CA
M is an associative memory. When the data stored in the cell array matches the data input as the search pattern, the stored address of the data together with the match signal is output. It is a memory to output.

FIG. 2 is a flowchart for explaining the operation of the first embodiment. When the SAR receiving section 24 receives the cell, it reads out the E bit and the allowable time-out period from the VC table corresponding to the received VC stored in the control memory 27 (S2, S3). E
The bit is examined (S4), and if the E bit is not set, it waits for cell reception again. If the E bit is set, it is checked whether the received cell is the last cell of the packet (S5). In the case of the last cell, that is, when the last cell of the packet arrives within the time-out allowable time, CAM1 is switched to the write mode (S
11), the E bit in the cell array 3 is cleared, and
The timeout detection of C is terminated (S12). If it is not the last cell, it is checked next whether it is the first cell (S
6). If it is not the first cell, it waits for cell reception again. If the received cell is the head cell, CAM1 is switched to the write mode (S7), and the timeout detection time, that is, the sum of the reception time (TS) of the head cell and the allowable time for timeout (T1), and the E bit CAM
1 is registered in the cell array 3 (S8), and CAM1 is switched to the search mode (S1).

In the search mode of CAM1, "1" is set to the most significant bit of the counter value of the timer section 6 indicating the current time.
Is input as a search pattern. This is to prevent the coincidence detected in the cell array 3 with the E bit cleared. The input search pattern is
When the timeout matches the timeout time registered in the cell array 3 of the CAM 1, a timeout is detected in the VC of the matching address (S9, S10). When the timeout is detected, CAM1 is rewritten to the write mode (S11), the E bit in the cell array 3 is cleared, and the timeout detection of this VC is terminated (S1).
2).

In the first embodiment of the present invention, the VC tables 14a, 14b, 14 in the control memory 27 are used.
c indicates the allowable time-out period (T
Since 1) can be set, timeout detection can be accurately performed for each VC in accordance with the cell rate and packet length of each VC. Further, since the CAM is used, integration is easy, and the circuit size of the timeout detection circuit can be reduced.

FIG. 3 is a block diagram of a second embodiment of the timeout detecting device according to the present invention.

In FIG. 3, a system clock 19 supplied from the system bus 31 side, a k frequency dividing circuit for dividing the system clock 19, an m frequency dividing circuit 34, and an n frequency dividing circuit 35 (where k, m , N is a positive integer) provided by a timer resolution selection code supplied from the outside, a selector 32 is provided, and the counter value in the timer section 6 is incremented in synchronization with the output signal of the selector 32. Configuration. Other configurations are the same as those of the first embodiment shown in FIG.

A packet received at a low rate or a packet having a long packet length takes a long time to complete reception. Therefore, it is necessary to increase each bit width of each area such as the counter 7 in the timer section 6, the cell array 3 of the CAM 1, and the time-out allowable time in each VC table.
For example, when the bit width of these areas is 16 bits and the system clock 19 is 33 MHz, one unit time is 30 nesc, and the time in which timeout can be detected is about 2 msec at the maximum. For this reason, timeout detection of a packet that takes 10 msec to complete reception cannot be performed. Therefore, in order to detect timeout, the bit width of each area must be increased by 3 bits.

In this embodiment, the counter value in the timer section 6 can be incremented by a signal obtained by dividing the system clock 19 by each frequency dividing circuit and the timer resolution selection code, so that one unit time can be lengthened. Thus, it is not necessary to increase the bit width of each area even for a packet received at a low rate or a packet having a long packet length. When receiving a packet that takes 10 msec to complete the reception, timeout can be detected by selecting a signal obtained by dividing the system clock 19 by six.

In the second embodiment, in addition to the effects of the first embodiment, the system clock can be divided and the unit time for incrementing the timer section can be set long, so that the low rate can be achieved. Can correspond to a packet received with a packet length or a packet having a long packet length. In addition, there is an effect that the bit width of a region such as a counter in the timer unit, a cell array of the CAM, and a time-out allowable time in each VC table can be reduced.

[0039]

The first effect is that the detection of the timeout of the ATM packet can be accurately performed for each VC in accordance with the cell rate and the packet length of each received VC. The reason is that the permissible time of the timeout of the ATM reception packet can be set for each reception VC. Referring to FIG. 1, for example, the time required for a packet of each VC to be normally received and assembled is represented by VC
i: 2 msec, VCj: 4 msec, VCk: 8 ms
ec, the allowable time for timeout is set to 2 msec, 4 msec, 8 msec for each VC.
Can be set.

The second effect is that CA
The use of M means that the circuit size of the timeout detection unit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of a timeout detecting device of an ATM receiving device according to the present invention.

FIG. 2 is a flowchart for explaining the operation of the first embodiment of the present invention shown in FIG.

FIG. 3 is a block diagram of a second embodiment of the timeout detecting device of the ATM receiving device according to the present invention.

FIG. 4 is a diagram for explaining an example of an ATM network system including an ATM communication device to which the present invention and the prior art are applied.

FIG. 5 is a block diagram for explaining conversion of a packet to an ATM cell.

FIG. 6 is a block diagram showing an example of an ATM communication device to which the present invention and the prior art are applied.

FIG. 7 is a block diagram of an example of a conventional timeout detection device.

[Explanation of symbols]

 1 CAM 2 Selector 3 CAM Cell Array 4 Address Decoder 5 Priority Encoder 6 Timer 7 Counter 8 Incrementer 9 Write / Search Mode Switching Unit 10 Adder 11 Header / Payload Separation Unit 12 VPI / VCI- VC converter 13 Received data FIFO 14a-14c Received VC table 15a-15c Received VC table 16 T1 register 17 TS register 18 Comparator 19 System clock 20a, 20b ATM server 21a-21c ATM terminal 22a ATM switch 23a to 23f ATM cell 24 SAR receiver 25 SAR transmitter 26 DMA controller 27 Control memory (VC table) 28 PHY 29 CPU 30 System memory 31 System bus 32 Selector 33 k frequency divider 34 m frequency divider 35 n frequency divider

Claims (2)

(57) [Claims] 1. The header of each ATM cell of a received packet.
Header / payload separation unit that separates data from payload
And a reception data storage unit for storing the payload, and reading the payload from the reception data storage unit.
D to system bus to which PU and system memory are connected
DMA controller for MA transfer, and conversion of VPI / VCI extracted from the header to VC
And a VPI / VCI-VC conversion unit connected to the VPI / VCI-VC conversion unit.
Executes the corresponding timeout allowable time and timeout detection.
And a first E bit for setting whether or not
VC table, a timer section for outputting the reception time of each of the ATM cells, a time outputted from the timer section, and each of the ATM cells.
The tie read from the VC table corresponding to the VC of
An adder for adding the time-out allowable time, an output value of the adder , and a time output from the timer unit.
And a selector for selecting and outputting any one of the following: and a decoder for decoding the VC by a decoder.
Write the output value of the adder corresponding to the VC via
Output from the timer unit
If the time matches the
A match signal indicating which VC matched with the match signal.
A plurality of CAM cells for outputting the address, and a first cell provided in each of the plurality of CAM cells.
When receiving, set to the first state and receive the last cell
Or the second state when the coincidence signal is detected.
And a second E bit that is
TM receiver. And means for dividing the system clock.
The time resolution selection code supplied from the
Select the signal to increment the counter value in the timer section
To control one unit time of the timer section
2. The frequency dividing means according to claim 1, further comprising:
ATM receiver.