JPH09331253A - Phase-locked loop for improving phase-synchronizing time - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain synchronization in an early stage by reducing the deviation of a voltage-controlled oscillator due to the variation of the surrounding environment. SOLUTION: A switch (SW) 108 is turned off before starting communication. The data read out from the memory of a second buffer 110 are inputted to a VCO 104 through a D/A converter 111 and an adder 112 and a specific frequency fVCO is outputted from the VCO 104. The frequency fVCO is also supplied to a variable frequency divider 105 which divides the frequency fVCO under the control of a second controller 106 and a phase comparator 102 compares the divided frequency with an input from a reference signal generator 101. The result of the comparison is supplied to the SW 108 and a level detector 113 which compares the result with a reference level through a LPF 103 and inputted to a control section 107. The section 107 discriminates the phase advancing or delaying state of a reference signal and controls the phase of the VCO 104 by increasing or decreasing the data in the buffer 110 in accordance with the discriminated result. When the phase of the VCO 104 is controlled, the section 107 stores the data in the buffer 110 in a first buffer 109. When communication is started, the data are read out from the buffer 109 and the SW 108 is turned on, resulting in a steady state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop of a wireless communication system, and more particularly to a phase locked loop of a wireless communication system capable of improving a long sync time due to a deviation of components of a voltage controlled oscillator and a deviation due to a change of surrounding environment. Regarding the loop.

[0002]

2. Description of the Related Art In a phase locked loop (hereinafter referred to as "PLL"), an oscillation frequency to be output is perfectly tuned or matched with a frequency of an input signal or a frequency of a reference oscillator. It is a kind of automatic control circuit that processes like a normal phase comparator (Phase Compara
tor or Phase Detector) and low pass filter (Low
pass Filter) and voltage controlled oscillator (Voltage Controlled)
Oscillator) to form a feedback loop.

FIG. 1 is a diagram showing a general configuration of a PLL. The oscillation frequency of a voltage controlled oscillator 104 is applied to a phase comparator 102 after being frequency-divided by a variable frequency divider 105. The phase comparator 102 compares the oscillation frequency obtained by the specific frequency division with the reference signal generated by the reference signal generator 101, and outputs a signal indicating a phase difference resulting from the comparison to the low pass filter 103. Phase comparator 10
When the signal output from 2 is supplied to the voltage controlled oscillator 104 through the low pass filter 103, the phase of the voltage controlled oscillator 104 changes, and as a result, the voltage controlled oscillator 1
Reference numeral 04 outputs a signal whose phase is synchronized with the reference signal generated by the reference signal generator 101, as an output frequency fvco.

The phase noise characteristic of the voltage control oscillator 104 of the PLL and the locking time characteristic of the PLL synchronized with the reference signal are mainly determined by the low-pass filter 103. To be done. In other words, if the bandwidth of the low pass filter 103 is widened, the synchronization time of the PLL is improved, but the noise applied to the voltage controlled oscillator 104 increases and the voltage controlled oscillator 1
The phase noise characteristic of No. 04 deteriorates, and the low-pass filter 103
When the band width of the signal is narrowed, the phase noise characteristic of the voltage controlled oscillator 104 is improved but the PLL synchronization time is reduced.

On the other hand, since the frequency division value of the variable division period 105 is fixed to one, in the system in which the voltage controlled oscillator 104 outputs only one oscillation frequency, the PLL synchronization time does not matter much, but it is variable. In a system in which the oscillation period of the voltage control oscillator 104 is alternately output by changing the minute period 105, a fast PLL synchronization time is required. For example, wireless phones, mobile phones or frequency hops using multichannel.
In the ping system, the phase noise characteristics of the voltage controlled oscillator are excellent and fast synchronization time is required.

A method proposed in response to such a demand is disclosed in US Pat. No. 4,980,652, "Frequency Synthesizer," which was registered on December 25, 1990.
It is disclosed under the title "Compensation For Nonlinearities". According to No. 4,980,652, the control voltage value corresponding to the output frequency to be obtained from the voltage control oscillator is stored in advance in the ROM (Read Only Memory). Hereinafter, this voltage value is used as the control voltage of the voltage controlled oscillator. After calculating using a drift compensation block what the error value due to environmental changes such as time changes and temperature changes extracted from the low-pass filter is, it is compensated with a subtractor block and Used as control voltage. Thus, the fourth, 980, 652
No. 1 applies an indirect compensation method such as applying a voltage value stored in ROM in advance as a control voltage of the voltage controlled oscillator and applying a voltage value compensated by the subtractor block as a control voltage of the voltage controlled oscillator. It is used to improve the synchronization time characteristic and the phase noise characteristic.

[0007] On the other hand, 900 of the mobile phones that have been commercialized
In the voltage controlled oscillator of the MHz band, the output frequency deviation due to the ambient temperature change is usually ± 2 MHz, and the output frequency deviation due to the component deviation of the voltage controlled oscillator is about ± 5 MHz under a constant control voltage at room temperature. In other words, the component deviation of the voltage controlled oscillator and the deviation of the output frequency due to the time change and the environmental change such as the ambient temperature are usually several thousand PPM (Par
ts Per Million) or more. The 4,980,65
Thousands of such PPMs, as disclosed in No. 2
When the above output frequency deviation is reduced by using the PLL of the indirect compensation method, the system configuration and calculation are complicated, and the compensation error becomes large.

Another method proposed to improve the phase noise characteristic of the voltage controlled oscillator and the synchronization time characteristic of the PLL is 1.
U.S. Pat. No. 5,355,098, "Phase-Locked Loop with Memor," issued October 11, 994.
y Storing Control Data Controlling the Oscillation
It is disclosed under the title "Frequency". According to this No. 5,355,098, the control voltage applied to the voltage controlled oscillator immediately before the PLL is powered off is stored in the memory, and the stored control voltage immediately before the power is turned off when the PLL further powers up. When it is turned on, it is used as the control voltage of the voltage controlled oscillator to improve the phase noise characteristic of the voltage controlled oscillator and the synchronization time characteristic of the PLL.

However, even if this method is used, if a long time elapses or the ambient temperature changes abruptly, the output frequency deviation due to the change in the ambient environment of the voltage controlled oscillator becomes several thousand PPM or more. That is, since the PLL synchronizes the phase with an error range due to a large frequency deviation at the initial phase synchronization, P
There is a problem that the synchronization time characteristic of LL deteriorates. For example, after a long time (a long time in which the component deviation of the voltage controlled oscillator is considerably large) has passed since the PLL was powered off,
Alternatively, when the ambient temperature suddenly moves to another place and the PLL is further powered on, the deviation of the output frequency due to the change of the ambient environment at this time becomes large, so that the time required for the initial phase synchronization will be considerably long.

[0010]

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a phase locked loop capable of improving a PLL synchronization time which is lengthened by a deviation of a voltage controlled oscillator in a wireless communication system and a deviation caused by a change in an ambient environment. Especially.

Another object of the present invention is to provide a PLL capable of minimizing the error due to the component deviation of the voltage controlled oscillator and the change of the surrounding environment immediately before the transmission mode or the reception mode of the wireless communication system is operated. is there.

[0012]

In order to achieve such an object, the present invention provides a control for a frequency required in each operation mode immediately before an operation in a transmission mode or a reception mode of a wireless communication system is performed. The purpose of the present invention is to provide a PLL capable of improving the synchronization time lengthened by the component deviation of the voltage controlled oscillator and the deviation due to the change of the surrounding environment by using the evaluated control voltage in the actual operation mode after evaluating the voltage.

A PLL of a wireless communication system according to the first aspect of the present invention is a storage means for digitally storing a series of control voltages having mutually different values, and a series of storage means stored in the storage means. A digital / analog converter for converting the read control voltage into an analog control voltage when any one of the control voltages is read, and a frequency depending on the level of the applied analog control voltage or analog signal. , A variable frequency divider that divides the output of the voltage controlled oscillator according to a variable frequency division ratio determined by the operation mode of the wireless communication system, and an output from the variable frequency divider. A phase comparator that compares the phase of a signal that is applied with the phase of a reference signal applied from the outside and outputs a phase difference signal that indicates the comparison result; A low-pass filter for low-pass filtering a signal, a level detector for comparing the level of an analog signal output from the low-pass filter with a reference level, and outputting the comparison result as a digital signal, and the level detection Using the digital signal output from the storage unit, one of the series of control voltages stored in the storage unit is read out and provided to the digital / analog conversion unit, and the read operation is performed by the level detection unit. The digital signal output from the controller is controlled until it reaches a value within a preset range, and immediately before the operation mode of the wireless communication system is performed, it is electrically turned off by the control of the controller. So that the analog control voltage output from the digital / analog converter is provided to the voltage controlled oscillator. And a switch that electrically supplies the analog signal output from the low pass filter to the voltage controlled oscillator under the control of the control unit during operation of the wireless communication system. To be done.

The controller may detect a key input generated by powering on the PLL or by inputting a key for sensing a received signal or transmitting a signal.
The switch is electrically turned off to perform a read operation for a series of control voltages stored in the storage means. In this read operation, the level value of the digital signal output from the level detector is within the set range. If it is smaller, the control voltage stored in the storage means is increased, and if it is larger than the preset range value, the control voltage stored in the storage means is reduced. . Note that the control unit uses the level value of the digital signal output from the level detector as the storage means even when no operation is performed for a preset time during the operation mode of the wireless communication system. One of the stored series of control voltages is read and provided to the digital / analog converter, and the read operation is performed within the range in which the level value of the digital signal output from the level detector is preset. Perform until the value becomes within.

A PLL of a wireless communication system according to a second aspect of the present invention is a storage means for digitally storing a series of control voltages having different values, and a series of control voltages stored in the storage means. When any one of the above is read, a digital / analog converter for converting the read control voltage into an analog control voltage and a frequency dependent on the level of the applied analog control voltage or analog signal are oscillated. A voltage-controlled oscillator, a variable frequency divider that divides the output of the voltage-controlled oscillator according to a variable frequency division ratio determined by an operation mode of the wireless communication system, and a signal output from the variable frequency divider. A phase comparator that compares the phase with the phase of a reference signal applied from the outside, and outputs a phase difference signal indicating the comparison result; Analog converting and low-pass filter for low-pass filtering, the analog signal output from the low-pass filter into a digital signal /
A digital converter and a digital signal output from the analog / digital converter are used to read any one of a series of control voltages stored in the storage means and provide the digital / analog converter with the control voltage. Then
The read operation is performed until the digital signal output from the analog / digital converting means reaches a value within a preset range, and the read operation is performed immediately before the operation mode of the wireless communication system is performed. An analog control voltage that is electrically turned off by the control of the control means and output from the digital / analog converter is provided to the voltage controlled oscillator, and the control means of the control means is operated during the operation of the wireless communication system. And a switch that electrically turns on under control so that the unlogged signal output from the low pass filter is provided to the voltage controlled oscillator.

The control unit electrically turns off the switch when the PLL is powered on or when a key input for sensing a received signal or a key for signal transmission is sensed, and the controller stores the data in the storage unit. The read operation for the control voltage is carried out, and the read operation at this time is stored in the storage means when the level value of the digital signal output from the analog / digital converter is smaller than the value within the set range. The process is performed while increasing the value of the control voltage, and when the value is larger than the value of the set range, the process is performed while decreasing the value of the control voltage stored in the storage unit. The control unit uses the level value of the digital signal output from the analog / digital converter even when no operation is performed during a preset time during the operation mode of the wireless communication system. One of a series of control voltages stored in the analog / digital converter is read out and provided to the digital / analog converter, and the read operation is preset with the level value of the digital signal output from the analog / digital converter. Perform until a value within the specified range is reached.

A PLL of a wireless communication system according to a third aspect of the present invention comprises a storage means for digitally storing a series of control voltages having different values, and a series of control voltages stored in the storage means. When any one of the above is read, a digital / analog converter for converting the read control voltage into an analog control voltage and a frequency dependent on the level of the applied analog control voltage or analog signal are oscillated. A voltage-controlled oscillator, a variable frequency divider that divides the output of the voltage-controlled oscillator according to a variable frequency division ratio determined by an operation mode of the wireless communication system, and a signal output from the variable frequency divider. A phase comparator that compares the phase with the phase of a reference signal applied from the outside, and outputs a phase difference signal indicating the comparison result; A low-pass filter for low-pass filtering, a phase error comparator for detecting and outputting a phase error value between the signal output from the variable frequency dividing means and the reference signal using the phase difference signal, Using the phase error value output from the phase error comparator, one of the series of control voltages stored in the storage means is read and provided to the digital / analog converter, and the read operation is performed. A control unit that performs until the phase error value output from the phase error comparator reaches a value within a preset range, and immediately before the operation mode of the wireless communication system is performed, by the control of the control unit. An analog control voltage that is electrically turned off and output from the digital / analog converter is provided to the voltage controlled oscillator, and the wireless communication is performed. During stem of operation, composed of a switch to turn an analog signal the output from the low pass filter is electrically turned on by the control of the control unit is provided to the voltage controlled oscillator.

The control unit electrically turns off the switch when the PLL is powered on or when a key input for sensing a reception signal or a signal transmission is sensed and stored in the storage means. The read operation for the series of control voltages is performed, and the read operation at this time is stored in the storage means when the phase error value output from the phase error comparator is smaller than the value in the set range. The process is performed while increasing the value of the control voltage, and when the value is larger than the value of the set range, the process is performed while decreasing the value of the control voltage stored in the storage unit. The control unit stores in the storage means using the phase error value output from the phase error comparator even when no operation is performed for a preset time during the operation mode of the wireless communication system. One of the set control voltages is read and provided to the digital / analog converter, and the read operation is a value within the preset range of the phase error value output from the phase error comparator. Until the time.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. In addition, in the drawings, the same reference numerals and numbers are commonly used for the same components and parts as much as possible.

When it is determined that a detailed description of related known functions or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
Since the terms defined in consideration of the functions of the present invention may differ depending on the intention or custom of the user or chip designer, the definition is based on the contents throughout the specification. It should be.

FIG. 2 shows a PLL according to the first embodiment of the present invention.
It is a figure which shows the structure of. In the figure, the switch SW108 is turned off immediately before communication is performed, the digital data stored in the buffer 2 (110) of the auxiliary storage device is converted into analog data by the D / A converter 111, and then the adder is added. Voltage controlled oscillator 104 through 112
Voltage controlled oscillator 104 continuously oscillates and outputs a specific frequency. At this time, the voltage controlled oscillator 1
The output frequency stability of No. 04 depends on the short-term stability characteristic of the voltage-controlled oscillator, but the short-term stability characteristic of the commonly used voltage-controlled oscillator in the 900 MHz band is tens of PPM.
To hundreds of PPM. The phase comparator 102 generates the output of the variable frequency divider 105 that divides the oscillation frequency of the voltage controlled oscillator 104 according to the variable frequency division ratio determined by the control unit 2 (106) and the reference signal generator 101. The phase of the reference signal is compared, and a phase difference signal indicating the comparison result is output. Since the low-pass filter 103 contains a large amount of high frequency and noise components in the phase difference signal,
This is converted into a pure DC component and then provided to the switch 108 and the level detector 113. At this time, the signal output from the low pass filter 103 is an analog signal. The level detector 113 compares the analog signal output from the low-pass filter 103 with a preset reference level value to detect whether the phase difference signal is within a specific range or outside the range. After that, the detection result is provided to the control unit 1 (107) as a digital signal. The controller 1 (107) uses the digital signal provided from the level detector 113 to determine whether the phase difference signal is within a specific range, the phase of the reference signal is fast, or the frequency-controlled oscillator 104 whose frequency is divided. Determine if the phase of the oscillating signal is fast. The control unit 1 (107) increases or decreases the data stored in the buffer 2 (110) according to the determination result, and the phase difference between the reference signal and the divided oscillation signal of the voltage controlled oscillator 104. Within the specified error range. Voltage controlled oscillator 10 divided by reference signal
When the phase difference between the four oscillating signals falls within the specific error range, the control unit 1 (107) stores the corresponding data in the buffer 2 (110) in the buffer 1 (109). Buffer 1
Since (109) is composed of a large number of addresses set corresponding to respective frequencies used in the system,
Of the data in the buffer 2 (110), the control unit 1 (10
The data selected by 7) is the buffer 1 (10
It can be stored at the corresponding address in 9).

By such an operation, the buffer 1 (10
The data stored in 9) is D /
Voltage-controlled oscillator 1 after being converted by the A converter 111
04 as a control voltage. D / A converter 111
When the signal converted by is applied to the voltage controlled oscillator 104 through the adder 112, the control unit 1 (107)
Turns on the switch 108 to turn on the voltage-controlled oscillator 104.
The deviation caused by the short-term stability characteristic of C and the deviation caused by the change of the surrounding environment such as time space are continuously compensated.

FIG. 3 is a diagram showing a processing flow for a write operation performed in the reception mode of the PLL according to the present invention. In this write operation, whether the PLL is powered on,
Alternatively, it begins when the received signal is sensed.

When the PLL is powered on or a received signal is sensed (step 301), the controller 1
(107) turns off the switch 108 (step 302). Next, the frequency division data corresponding to the frequency selected by the control unit 2 (106) is sent to the variable frequency divider (105), and the control unit 1 (107) causes the buffer 1 of the main storage device to be stored.
A frequency selection process of writing data from (109) to the buffer 2 (110) or writing arbitrary data to the buffer 2 (110) is performed (step 303). next,
After the phase difference between the reference signal and the oscillation signal of the voltage controlled oscillator 104 is detected (step 304), it is compared whether the phase difference is within the allowable error range ± R, or is larger or smaller than the allowable error range (305). Step). If the phase difference is larger than the allowable error range + R, the controller 1 (107) decreases the data value of the buffer 2 (110) (step 308).
After that, the phase difference is detected again (step 304), and when it is smaller than the allowable error range −R, the control unit 1 (107) increases the data value of the buffer 2 (110) (step 307).
After that, the phase difference is detected again (step 304). In this way, when the phase difference is within the allowable error range ± R, the control unit 1 (107) transfers the data of the buffer 2 (110) as the auxiliary storage device to the buffer 1 (1 of the main storage device.
09) is written (step 309). Then, it is compared whether the above process has been performed for the frequency used (step 310). If all the steps are not performed, the control unit 1 (109) again performs the frequency selection step (30
The operation of writing the data of the buffer 2 (110) back to the buffer 1 (109) is performed after returning to the three stages, and if all the steps are performed, the data of the buffer 2 (110) is written to the buffer 1 (109). Carry out an action. This completes the reception mode operation. FIG. 4 is a diagram showing a processing flow for a write operation performed in the transmission mode of the PLL according to the present invention.

The write operation in the transmission mode as shown in the figure is performed almost the same as the write operation in the reception mode as shown in FIG. However, if there is a difference, since the operation is in the transmission mode, unlike the operation in the reception mode, when the PLL is powered on or when the user wants to transmit data, for example, the user touches the keypad. When pressed, the operation starts (step 401). Usually, whether or not data is input from a keypad in a telephone is confirmed in a cycle of about 50 ms. Other systems, other than telephones, likewise operate by sensing a user inputting data for transmission.

As shown in FIGS. 3 and 4, the control of the voltage controlled oscillator corresponding to the frequency required in each mode immediately before the actual transmission / reception operation is performed in the communication mode (transmission mode and reception mode) of the system. The PLL can be synchronized in a short time to evaluate and use the voltage. In other words, the PLL synchronization time can be shortened by using a value that matches the situation at that time, without considering the data difference caused by the deviation of the voltage controlled oscillator and other parts and the deviation due to the change of the surrounding environment. obtain.

The function of compensating for the PLL synchronization time, which becomes longer as the error in the data value stored in the buffer 1 (109) increases due to changes in the surrounding environment such as abrupt changes in space during operation in the communication mode. I do. FIG. 5 shows a processing flow for the write operation performed in the communication mode of the PLL according to the present invention for such a function.

Generally, in the operation of each transmission / reception mode of the wireless communication system, the transmission / reception of data is not continuously performed at a high speed but may be in a slow state at a certain moment. The control unit 1 (107) continuously senses a slow transmission / reception operation state (a state in which transmission / reception is not busy) (step 501).
However, when the busy state of transmission and reception is detected, the switch (108) is held in the ON state (step 502) and the phase difference between the reference signal and the oscillation signal of the voltage controlled oscillator 104 is detected (step 503). . Next, the control unit 1 (107) compares the phase difference (step 504), and then decreases (in step 506) or increases (in step 505) the data in the buffer 2 (110) according to the comparison result. , Make the phase difference within the allowable error range. When the phase difference falls within the allowable error range, the control unit 1 (107) causes the buffer 1 (109) to update the data (step 507). After that, the control unit 1 (107) compares the updated data with the existing data, calibrates the data stored in the buffer 1 (109) for other frequencies used, and then calibrates the data. The data is updated (step 508). Buffer 1 like this
After updating the data stored in (109), it is periodically determined whether transmission and reception are not busy (50
The data stored in the buffer 1 (109) is continuously updated in 9 steps. On the other hand, among the initially stored values, the value updated due to changes in the surrounding environment is the same as the error value generated at one frequency and can be applied to other frequencies. Applying the error correction value for one frequency to the other used frequencies does not pose a problem.

FIG. 6 is a diagram showing a processing flow for a read operation performed in the PLL according to the present invention, which is a process of reading data stored or updated through the processes shown in FIGS. 3 to 5.

The control unit 1 (107) uses the buffer 1 (10
After the data stored in 9) is transferred to the buffer 2 (110) (step 601), this value is output to the D / A converter 111 for D / A conversion (step 602). The converted data passes through the adder 112 and the voltage control oscillator 104.
When the switch 108 is turned on after being applied to (60
(3 steps), the switch 108 is turned on in a state where the frequency of the voltage controlled oscillator 104 is within the range of the allowable error due to the signal converted by the D / A converter 111, so that the PLL becomes faster. Phase-lock to

The PLL according to the present invention is stored in the buffer 1 (109) at the data value within the allowable error range that matches the situation through the processes shown in FIGS. You can sync quickly in any situation. FIG. 7A is a diagram showing a synchronization time characteristic of a PLL according to the related art, and FIG. 7B is a diagram showing a synchronization time characteristic of a PLL according to the present invention. As shown in FIG. 7A, in the method according to the related art, when the power is turned off and then turned on again, the PLL synchronization time is long due to the characteristics of the PLL loop including the low-pass filter 103, and the frequency is changed during use. Similarly, the synchronization time becomes considerably long. On the other hand, as can be seen from FIG. 7B, in the method according to the present invention, the synchronization time becomes very fast even when the power is turned on or the frequency changes during use.

8 and 9 are diagrams showing the configuration of the PLL according to the second and third embodiments of the present invention. The PLL according to the second embodiment of the present invention has substantially the same configuration as the PLL according to the first embodiment of the present invention shown in FIG. 2, but the reference signal generator 10 output from the low pass filter 103 is used.
The signal corresponding to the phase difference between the reference signal generated by 1 and the divided oscillation signal of the voltage controlled oscillator 104 is
It is applied to the control unit 1 (107) via the A / D converter 114. Then, the control unit 1 (107) analyzes whether or not the phase difference signal is within the range of the specific error using the output signal from the A / D converter 114, and according to the first embodiment of the present invention. The buffer 1 (109) and the buffer 2 (110) are controlled by the same method.

The PLL according to the third embodiment of the present invention is shown in FIG.
Although the configuration of the PLL according to the first embodiment of the present invention shown in FIG. 1 is almost the same, the phase difference signal output from the phase comparator 102 passes through the low pass filter 103 and the control unit 1 (10
7), rather than being applied to the phase error comparator 11
It is applied to the control unit 1 (107) through the line 5. Then, the control unit 1 (107) causes the phase error comparator (11
The output signal from 5) is used to analyze whether the phase difference signal is within a specific error range, and the buffer 1 (109) and the buffer 2 are analyzed by the same method according to the first embodiment of the present invention.
Control (110).

[0034]

As described above, the present invention provides:
You can synchronize the PLL in a short time no matter what the situation,
It should be noted that such a PLL can be very advantageously used in a communication system that requires a fast frequency change, for example, a frequency jump communication system.

On the other hand, although specific examples have been described in the present invention as described above, it is a normal knowledge that various modifications and changes can be made without departing from the technical idea of the present invention. It will be obvious to anyone with. For example, although the PLL is realized by using two buffers in the embodiment of the present invention, it can be realized by using one storage means. Therefore, the present invention should not be limited to the described embodiments, but rather should be determined not only by the scope of the claims, but also by the equivalents of the claims.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a phase locked loop according to a conventional technique.

FIG. 2 is a configuration diagram of a phase locked loop according to the first embodiment of the present invention.

FIG. 3 is a diagram showing a processing flow for a write operation performed in a reception mode of a phase locked loop according to the present invention.

FIG. 4 is a diagram showing a processing flow for a write operation performed in a transmission mode of a phase locked loop according to the present invention.

FIG. 5 is a diagram showing a processing flow for a write operation performed in a transmission mode or a reception mode of the phase locked loop according to the present invention.

FIG. 6 is a diagram showing a processing flow for a read operation performed in a phase locked loop according to the present invention.

FIG. 7 is a diagram showing a comparison between the synchronization time characteristic of the phase locked loop according to the related art and the synchronization time characteristic of the phase locked loop according to the present invention.

FIG. 8 is a configuration diagram of a phase locked loop according to a second embodiment of the present invention.

FIG. 9 is a configuration diagram of a phase locked loop according to a third embodiment of the present invention.

[Explanation of symbols]

 101 Reference Signal Generator 102 Phase Comparator 103 Low Pass Filter 104 Voltage Control Oscillator 105 Variable Frequency Divider 106, 107 Control Unit

Claims (12)

[Claims] 1. In a phase locked loop of a wireless communication system, any one of a storage means for digitally storing a series of control voltages having different values, and a series of control voltages stored in the storage means. Digital / analog conversion means for converting the read control voltage into an analog control voltage when one of them is read, and voltage controlled oscillating means for oscillating a frequency depending on the level of the analog control voltage or analog signal applied. A variable frequency divider that divides the output of the voltage controlled oscillator according to a variable frequency division ratio determined by the operation mode of the wireless communication system; and a phase of a signal output from the variable frequency divider. Phase comparison means for comparing the phase of a reference signal applied from the outside and outputting a phase difference signal indicating the comparison result; Low-pass filtering means for low-pass filtering the signal; level detection means for comparing the level of the analog signal output from the low-pass filtering means with a reference level and outputting the comparison result as a digital signal; Using the digital signal output from the level detecting means, any one of a series of control voltages stored in the storing means is read out and provided to the digital / analog converting means, and the read operation is performed by the level detecting operation. Control means for performing until the digital signal output from the means has a value within a preset range; and immediately before the operation mode of the wireless communication system is performed, it is electrically turned off by the control of the control means. The analog control voltage output from the digital / analog conversion means is the voltage control An analog signal which is electrically turned on by the control of the control means and is output from the low pass filtering means during the operation of the wireless communication system to the voltage controlled oscillation means. Switching means to be
A phase-locked loop comprising: 2. The control means electrically turns off the switching means when the phase-locked loop is powered on or when a key input for sensing a reception signal or transmitting a signal is sensed. 2. The phase-locked loop according to claim 1, wherein a read operation is performed on a series of control voltages stored in the storage means. 3. The control means reads while increasing the value of the control voltage stored in the storage means when the level of the digital signal output from the level detection means is smaller than the value of the set range. The operation is performed, and when the level of the digital signal output from the level detecting means is larger than the value in the set range, the reading operation is performed while reducing the value of the control voltage stored in the storing means. The phase-locked loop according to claim 1. 4. The control means uses the digital signal output from the level detection means even when no operation is performed during a preset time during the operation mode of the wireless communication system. One of a series of control voltages stored in the storage means is read out and provided to the digital / analog conversion means, and the read operation is preset by the digital signal output from the level detection means. The phase-locked loop according to any one of claims 1 to 3, wherein the phase-locked loop is performed until a value within a range. 5. In a phase locked loop of a wireless communication system, a storage means for digitally storing a series of control voltages having different values, and a series of control voltages stored in the storage means. Digital / analog conversion means for converting the read control voltage into an analog control voltage when any one of them is read, and voltage controlled oscillation for oscillating a frequency depending on the level of the analog control voltage or analog signal applied. Means, a variable frequency dividing means for dividing the output of the voltage controlled oscillator according to a variable frequency dividing ratio determined by an operation mode of the wireless communication system, and a phase of a signal output from the variable frequency dividing means. And a phase comparison means for comparing the phase of a reference signal applied from the outside and outputting a phase difference signal indicating the comparison result, Low-pass filtering means for low-pass filtering the phase difference signal, analog / digital converting means for converting an analog signal passed from the low-pass filtering means into a digital signal, and output from the analog / digital converting means. A digital signal is used to read out one of a series of control voltages stored in the storage means and provide it to the digital / analog conversion means, and the read operation is output from the analog / digital conversion means. Control means for performing a digital signal until the digital signal has a value within a preset range, and immediately before the operation mode of the wireless communication system is performed, the digital / analog is turned off by the control of the control means. The analog control voltage output from the conversion means is the voltage control An unlog signal output from the low-pass filtering means is provided to the voltage control oscillating means while being turned on by the control of the control means during operation of the wireless communication system. A phase-locked loop comprising: 6. The control means electrically turns off the switching means when the phase locked loop is powered on or when a key input for sensing a received signal or transmitting a signal is sensed. The phase-locked loop according to claim 5, wherein a read operation is performed on a series of control voltages stored in the storage means. 7. The control means increases the value of the control voltage stored in the storage means when the level of the digital signal output from the analog / digital conversion means is smaller than the value in the set range. While performing the reading operation, when the level of the digital signal output from the analog / digital converting means is larger than the value within the set range, the reading operation is performed while reducing the value of the control voltage stored in the storing means. The phase-locked loop according to claim 5, which is performed. 8. The control means uses the digital signal output from the analog / digital conversion means even when no operation is performed during a preset time during the operation mode of the wireless communication system. Read out one of a series of control voltages stored in the storage means and provide it to the digital / analog conversion means, and the read operation is performed by a digital signal output from the analog / digital conversion means. The process is performed until a value within a preset range is reached.
~ The phase locked loop according to claim 7. 9. In a phase locked loop of a wireless communication system, a storage means digitally storing a series of control voltages having different values, and a series of control voltages stored in the storage means. Digital / analog conversion means for converting the read control voltage into an analog control voltage when any one of them is read, and voltage controlled oscillation for oscillating a frequency depending on the level of the analog control voltage or analog signal applied. Means, a variable frequency dividing means for dividing the output of the voltage controlled oscillator according to a variable frequency dividing ratio determined by an operation mode of the wireless communication system, and a phase of a signal output from the variable frequency dividing means. And a phase comparison means for comparing the phase of a reference signal applied from the outside and outputting a phase difference signal indicating the comparison result, Low-pass filtering means for low-pass filtering a phase difference signal, and phase error comparison for detecting and outputting a phase error value between the signal output from the variable frequency dividing means and the reference signal using the phase difference signal Means for reading out one of a series of control voltages stored in the storage means using the phase error value output from the phase error comparison means and providing the read control voltage to the digital / analog conversion means, Control means for performing the reading operation until the phase error value output from the phase error comparison means reaches a value within a preset range; and the control means immediately before the operation mode of the wireless communication system is performed. The analog control voltage which is electrically turned off by the control of the means and output from the digital / analog conversion means is the voltage controlled oscillator. An analog signal that is electrically turned on by the control of the control means and output from the low-pass filtering means is provided to the voltage controlled oscillation means during operation of the wireless communication system. A phase-locked loop comprising: 10. The control means electrically turns off the switching means when the phase-locked loop is powered on or when a key input for sensing a received signal or transmitting a signal is sensed. 10. The phase locked loop according to claim 9, wherein a read operation is performed on a series of control voltages stored in the storage means. 11. The control means reads out while increasing the value of the control voltage stored in the storage means when the phase error value output from the phase error comparison means is smaller than the value in the set range. When the level of the digital signal output from the phase error comparison means is higher than the value within the set range, the read operation is performed while decreasing the value of the control voltage stored in the storage means. The phase locked loop according to claim 9, wherein 12. The control unit controls the phase error value output from the phase error comparison unit even when no operation is performed during a preset time during the operation mode of the wireless communication system. A phase error value output from the phase error comparing means by reading out one of a series of control voltages stored in the storage means and providing the digital / analog converting means with the read operation. The phase-locked loop according to any one of claims 9 to 11, characterized in that the phase-locked loop is executed until a time becomes a value within a preset range.