JPH09330291A - Bus use arbitration circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize priority corresponding to system structure by selecting whether or not the preceding priority is to be succeeded. SOLUTION: When the priority of respective bus masters 2, 3 and 4 is set by a round robbin type arbitration method, a power saving mode (PSM) (operating clock stop mode) is started. Afterwards, when operation is started again, usually, an initial state is recovered and the preferential use is set in any specified bus master. When a preferential PSM select signal is outputted, however, the preceding state is held and the preferential use is applied to the bus master, which is made most preferential just before, as it is.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention comprises a plurality of bus masters connected via a processor bus and an arbitration module for arbitrating the processor bus usage right of these bus masters, and particularly adopts a round robin type arbitration method. The present invention relates to a bus right-of-use arbitration circuit that optimizes priority determination in the case of performing

[0002]

2. Description of the Related Art When a plurality of bus masters are connected to a processor bus and used, the arbitration module arbitrates the bus use right. When a plurality of bus masters simultaneously output processor bus usage requests and they conflict with each other, usage permission is granted in a preset priority order. This priority can be fixed or floating. The round-robin arbitration method is known as the latter arbitration method. In this method, the priority order is periodically changed so that the arbitration is fair to a plurality of bus masters.
Therefore, the bus master, which has become the first priority at a certain time, becomes the lowest priority at the next time, the priority is raised in order, and then the priority returns to the first again.

On the other hand, in a system using a microcomputer, when the processor is not used even when the power is on, the operation clock is stopped to reduce the power consumption of the system. At the start of the low power consumption mode, a low power consumption mode signal is output to each part of the system in advance, and each part performs a corresponding process. Also in the bus right arbitration circuit, when the mode shifts to such a mode, the circuit is initialized in advance. Therefore, when the output of the operation clock is started again to shift to the normal mode, the arbitration of the bus use right is started again from the initial state. That is, in the initial state, a certain bus master is always given the highest priority, and the process proceeds to the process of changing the priority order from that state.

[0004]

The conventional bus use right arbitration circuit as described above has the following problems to be solved. As described above, in the conventional round robin arbitration method, when the system shifts to the low power consumption mode, exits the low power consumption mode, and restarts operation, it always becomes the initial state and becomes a constant bus master. First, priority is given. However, for example, there are cases where it is desired to start the processing that was being executed immediately before shifting to the low power consumption mode with the highest priority. There is then no guarantee that the bus master will be given priority first.

Further, in the round robin type arbitration method, the priority order is periodically changed in a predetermined order. The order of change and the cycle of change are also fixed in advance. For example, when an urgent process is to be executed by a specific bus master, that bus master does not necessarily set the priority at that time. It is not always set as the highest priority. In such a land-robin arbitration method, there is a demand for a degree of freedom that enables flexible setting of priority settings.

[0006]

The present invention employs the following structure to solve the above problems. <Configuration 1> A plurality of bus masters connected via a processor bus and an arbitration module that arbitrates the processor bus use right of these bus masters are provided.
This arbitration module prioritizes bus masters in a round-robin fashion, and prioritizes the transition to the low power consumption mode when the system enters and exits the low power consumption mode. A bus right-of-use arbitration circuit provided with a determination circuit for determining whether to inherit the ranking or to always give priority to a certain bus master first.

<Explanation> When accessing data and the like using the processor bus, each bus master makes a bus use request in advance to the arbitration module. When the bus use requests conflict with each other, the arbitration module gives the use permission of the processor bus to the corresponding bus master according to the preset priority order.
In the round-robin arbitration method, the priority is changed periodically. The low power consumption mode is a mode that is selected to enter the low power consumption state when the processor is not used. When shifting to the low power consumption mode, the arbitration module is reset to the initial state. Therefore, when the low power consumption mode ends, the arbitration module always operates to give priority to a certain bus master first.

The decision circuit, for example, prevents the reset so as to inherit the prioritization just before the transition to the low power consumption mode according to the designation. As a result, it is possible to support both the system that wants to continue the immediately preceding process after the transition to the low power consumption mode and the system that always wants to perform the process again from the beginning, and optimize the prioritization.

<Structure 2> A plurality of bus masters connected via a processor bus and an arbitration module for arbitrating the processor bus use right of these bus masters are provided, and this arbitration module gives priority to each bus master in a round robin manner. In addition to performing ranking, when the system shifts to the low power consumption mode and ends the low power consumption mode, a determination circuit for determining the bus master designated to give priority first is provided. And a bus right arbitration circuit.

<Explanation> The arbitration module ends the low power consumption mode, and when an arbitrary bus master is designated, the bus master is first given priority. If such free designation is possible, further optimization of the prioritization can be achieved.

<Structure 3> A plurality of bus masters connected via a processor bus and an arbitration module for arbitrating the processor bus use right of these bus masters are provided, and this arbitration module gives priority to each bus master in a round robin manner. A bus use right arbitration circuit, which prioritizes a bus master designated in advance when a predetermined interrupt signal is input, while performing ranking.

<Explanation> When priority is given to each bus master in order in a round-robin manner and processing is performed, if there is an interrupt for notifying a situation that seriously affects the system, the previous order will be applied. I want to give priority to a specific bus master even if I ignore. Therefore, the arbitration module accepts the interrupt signal and forcibly switches the priority order. The cause of the predetermined interrupt signal may be arbitrary. Also, when an interrupt signal is input, which bus master is given priority is
Decide in advance. When there are a plurality of interrupt signal lines, it is sufficient to designate a bus master which gives priority to each interrupt signal. As a result, the priority of the round robin method can be arbitrarily changed by the external interrupt, and the degree of freedom of control is increased.

<Structure 4> A bus right arbitration circuit according to Structure 3, further comprising a mask circuit for masking an interrupt signal at an arbitrary timing.

<Explanation> In some cases, priority order change control by an interrupt signal should be performed, and in other cases, it may not be necessary. Therefore, a mask circuit is provided in the line for inputting the interrupt signal to the arbitration module circuit so that the interrupt signal can be invalidated freely. In this way, various systems can be flexibly dealt with.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to specific examples. <First Specific Example> FIG. 1 is a block diagram showing a bus right-of-use arbitration circuit of a first specific example. This circuit is configured such that the arbitration module 1 arbitrates the bus use right of a plurality of bus masters 2, 3, 4 connected to the processor bus 11. From each bus master 2, 3, 4
Processor bus request signals (NAREQ) 5, 7, 9 are output to the arbitration module 1, and the arbitration module 1 outputs a processor bus use permission signal (NAACK) 6 or 8 or 10 to any bus master.

The operation clock (CLK) 12 is supplied to all of these modules. In addition, the arbitration module 1 has a low power consumption mode signal (PS
M) 13 and PSM priority select signal (PSMSET)
15 and 15 are configured to be input. The arbitration module 1 is a processor bus 1 for bus masters 2, 3 and 4 by a round robin type arbitration method.
1 is arbitrating the right of use. Also, the operation clock 12
It is assumed that the low power consumption mode signal 13 and the PSM priority select signal 15 are sent from a higher-order microcontroller (not shown).

FIG. 2 shows the internal circuit of the arbitration module of the first embodiment. The arbitration module 1 shown in FIG. 1 is composed of a determination circuit 17 and a control circuit 14 as shown in this figure. Judgment circuit 1
7 has two flip-flops (F / F) 31, 32
And an OR circuit 33 are provided. Each of the flip-flops 31 and 32 outputs the signal input to the D terminal to 1
Only the clock is held and output to the Q terminal. This control is performed by the operation clock (CLK) 12. The output of the flip-flop 32 is controlled by the low power consumption mode signal 13. For this reason, this signal is received at the enable terminal EN.
The OR circuit 33 is configured to receive the output of the flip-flop 31 and the output of the flip-flop 32 and output them as the mode determination signal (PSMOUT) 16 to the control circuit 14.

The structure of the control circuit 14 is not different from that of the conventional one, that is, the operation clock 12 is received, and the use permission signals 6, 8, and 10 for the processor bus request signals 5, 7, and 9 are received at that timing. It is configured to output. The control circuit 14 controls the mode decision signal 16
When is input, the arbitration operation is temporarily stopped, initialization is performed,
When the operation clock 12 is input again, arbitration is started again from its initial state.

FIG. 3 shows a specific internal circuit of the control circuit 14. If this circuit is represented by a simple functional block, for example, a priority setting counter 35 and gates 36, 37, 3
8 and. As shown, processor bus request signals 5, 7, 9 are input to gates 36, 37, 38, respectively. The priority setting counter 35 determines a count value so as to give priority to one of the bus masters, and outputs it to the gates 36, 37 and 38. For example, when priority is given to the bus master 2, only the gate 36 is opened and the gates 37 and 38 remain closed. As a result, only the processor bus signal enable signal 6 is asserted in response to the processor bus request signal 5. The priority setting counter 35 counts up at a predetermined timing to switch the priority. In the low power consumption mode, the mode determination signal 16 resets and initializes the priority determination counter.

FIG. 4 shows an explanatory diagram of such a basic round robin arbitration method. In this example, it is assumed that the bus masters (BMs) 2, 3, and 4 are given alternate priorities in the order of thick solid arrows. That is, during the normal operation, the bus master 2 is first given the priority, and then the bus master 3 and the bus master 4 are given the priority at a predetermined timing, and the priority is switched periodically. Here, for example, it is assumed that the bus master 2 has the right to use the processor bus and once enters the low power consumption mode. In this case, if the initialization is performed as described above, the bus master 2 is given the priority right in the initial state set in advance, so that the bus master 2 has the priority right after the operation is restarted. On the other hand, bus master 3
Has the right to use the processor bus and shifts to the low power consumption mode, the priority shifts to the bus master 2 in the initial state when the operation is restarted. Even when the bus master 4 has the processor bus use right and shifts to the low power consumption mode, the priority is returned to the bus master 2 and the operation is restarted.

On the other hand, according to the configuration of the specific example 1, the state where the priority is always returned to the bus master 2 and the bus master which has the priority immediately before the transition to the immediately previous state, that is, the low power consumption mode, is performed. It is possible to select the status such that the priority is succeeded after the operation is restarted.

FIG. 5 is an explanatory diagram of the priority order change of the first specific example. As shown in (a) of the figure, during normal operation, the priority order is BM2, BM3, BM4, BM2, BM3, BM.
4 and so on. Here, in the present invention, for example, as shown in (b), when the BM 4 has the processor bus use right and shifts to the low power consumption mode, when the priority order is not inherited, the low power consumption mode is set. When the operation is restarted at the time of the transition, BM2 and BM are restarted.
The priority order of 3, BM4 is set. On the other hand, when the immediately preceding operation is succeeded, the usage right is transferred to BM4, BM2, and BM3, and when the operation is restarted by shifting to the low power consumption mode, BM4 is first given the priority.

(C) shows the order change when the BM2 has the processor bus usage right and shifts to the low power consumption mode, and (d) shows the BM3 has the processor bus usage right and shifts to the low power consumption mode. Shows the ranking changes when transitioning. In either case, when the operation is resumed when the mode is changed to the low power consumption mode and the operation is succeeded, the BM2 and BM3 which have the right to use the processor bus immediately before have the priority. The operation of succession and non-succession as described above is
It is selected by the SM priority select signal 15 (FIG. 1). A specific operation of the determination circuit 17 shown in FIG. 2 will be described with reference to FIGS. 6 and 7.

FIG. 6 is an operation mode time chart when priority is not inherited. First, it is assumed that the operation clock 12 is supplied to each module as shown in FIG. Here, it is assumed that the low power consumption mode signal 13 is asserted at time t1. The low power consumption mode signal 13 indicates a normal state when "1" and a low power consumption mode state when "0".

Here, in the state shown in FIG. 6, the PSM priority select signal 15 remains at the low level "0" as shown in (c). When this signal is "0", it indicates that the priority order is not inherited, and when it is "1", it indicates that the priority order is to be inherited from the previous state. When the low power consumption mode signal 13 is asserted at time t1 and the flip-flop 31 shown in FIG. 2 is set to zero, the flip-flop 31 outputs “0” at the next clock rise.
Is output to the OR circuit 33. On the other hand, since the low power consumption mode signal 13 is input to the enable terminal EN of the flip-flop 32, the output of the flip-flop 32 in which "0" is already set is output to the OR circuit 33 at the timing of time t2. This content is "0"
It is. As a result, the content of the mode decision signal 16 is "0".
Is sent to the control circuit 14. This is the same state as when the low power consumption mode signal 13 was directly input to the control circuit 14 from the beginning. That is, thereby, the control circuit 14 initializes at the timing when the mode decision signal 16 is input, and as described above, the constant, for example, the bus master 2 is always given the highest priority and the operation is restarted.

FIG. 7 is an operation time chart when the priority order is succeeded. As shown in (b) of FIG. 7, before the low power consumption mode signal 13 is asserted at time t2, (c)
As shown in, at time t1, PSM priority select signal 1
When 5 is asserted from "0" to "1", the flip-flop 32 shown in FIG. 2 fetches the signal having the content "1". Then, when the low power consumption mode signal 13 is asserted from "1" to "0" at time t2, the output of the flip-flop 32 is permitted, and the content output from the flip-flop 32 at the time t3 at the next timing is ". The 1 ″ signal is input to the OR circuit 33. As a result, even if the low power consumption mode signal 13 is asserted, the content of the mode determination signal 16 is "1" due to the output of the flip-flop 32.
Left untouched. That is, the mode decision signal 16 is as shown in FIG.
As shown in (d), it remains "1" regardless of the content of the low power consumption mode signal 13. As a result, the control circuit 14 shown in FIG. 2 is not notified of the transition to the low power consumption mode,
The operation is stopped while maintaining the previous priority. Then, when the operation is resumed, the bus master, which had the previous right, is given the right again.

<Effects of Concrete Example 1> As described above, the low power consumption signal mode signal and the PSM priority select signal are received inside the arbitration module 1 shown in the concrete example 1, and the contents of the PSM priority select signal are changed. Since the determination circuit 17 that outputs the mode determination signal is provided in response, the priority order of the bus master at the time of the transition to the low power consumption mode is inherited from the state before the mode transition, or the preset constant bus master is given priority. You can freely set the ranking. As a result, the degree of freedom in system control is increased, and the operation can be optimized.

<Specific Example 2> FIG. 8 shows a bus use right arbitration circuit of a specific example 2. This circuit is different from the circuit of the concrete example 1 shown in FIG. 1 in that a bus master select signal (REQ) is newly added.
SEL) 18 is input. The bus master select signal 18 is a signal for arbitrarily designating the priority order of the bus master when the low power consumption mode is released. That is, when the bus master select signal 18 is "0", for example, the priority order of the bus master 2 is 1, and when it is "1", the priority order of the bus master 3 is 1.
When it is "2", the priority of the bus master 4 is set to 1. The role of the PSM priority select signal 15 is the same as in the first specific example.

FIG. 9 shows a specific example 2 for realizing this.
2 shows an internal circuit of the arbitration module of FIG. As shown in the figure, in the decision circuit 17, a flip-flop 34 is newly added to the circuit shown in FIG. The bus master select signal (REQSEL) 18 is input to the flip-flop 34. The low power consumption mode signal 13 is input to the enable terminal EN of the flip-flop 34. The flip-flop 34 receives the bus master select signal 18, and when the low power consumption mode signal 13 is "0", the operation clock 12
The stored signal is output from the Q terminal according to the timing. The output is the select signal (REQOUT) 1
It becomes 9 and is input to the control circuit 14. Other connections are the same as in the case of the specific example 1 already described.

FIG. 10 shows an operation time chart of the circuit of the second specific example. In the figure, (a) is the operation clock 12, (b)
Is a low power consumption mode signal 13, (c) is a PSM priority select signal 15, (d) is a mode determination signal 16, (e) is a bus master select signal 18, and (f) is a select signal 1.
9, (g), (h) and (i) are the bus master 2 and
3, 4 processor bus request signals, (j), (k),
(L) shows the processor bus use permission signals of the bus masters 2, 3 and 4.

As shown in the figure, the operation clock 12 stops its operation at time t8 due to the low power consumption mode signal and resumes its operation at time t9. The content of the PSM priority select signal 15 remains "1". Therefore, when the low power consumption mode signal 13 switches from "1" to "0" at time t4, the mode determination signal 16 switches from "1" to "0" at time t5 one clock later. This is the same operation as described in the specific example 1. Here, (e)
As shown in, the content of the bus master select signal 18 is switched from "0" to "1" at time t3.

This signal is stored in the flip-flop 34 shown in FIG. 9, but since the low power consumption mode signal 13 switches from "1" to "0" at time t4, the output of the flip-flop 34 becomes possible. Then, the select signal 19 in (f) switches from "0" to "1" at time t5. Here, for example, as shown in (g), the processor bus request signal 5 from the bus master 2 is stopped at time t1, and in response to this, the processor bus use permission signal 6 is sent at time t2 as shown in (j). Switched from "0" to "1". This completes the processing of the bus master 2. At this time, as shown in (i), the processor bus request signal 9 of the bus master 4
Is "0" and the bus right is being requested. As shown in (h), the bus master 3 is also requesting the bus right.

At this timing, since the bus master 3 has a higher priority than the bus master 4, the processor bus use permission signal 8 is "1" at time t2 as shown in (k).
From "0", the bus master 3 is given permission to use the bus. The bus master 4 temporarily stops the request for the processor bus at time t5. Further, the bus master 3 releases the use of the bus at time t6, and one clock later,
As shown in (k), the processor bus use permission signal also returns from "0" to "1". Thus, the low power consumption mode is entered.

After that, when the low power consumption mode signal 13 rises from "0" to "1" at time t9, the operation of the operation clock 12 starts. Here, since the content of the bus master select signal 18 is "0" as in (e) and the content of the select signal 19 is "1" as in (f), it is specified that the request from the bus master 3 is given the highest priority. Is done. As shown in the figure, even if the bus masters 2, 3 and 4 simultaneously make a bus right request at time t9, the request from the bus master 3 is preferentially accepted and the processor bus use permission signal 8 is set to "1". To "0".

That is, according to the circuit shown in FIG. 9, in the portion other than the flip-flop 34 of the determination circuit 17, the operation of inheriting the state before the transition to the low power consumption mode is performed as in the case of the concrete example 1. You can select the operation not to inherit. Further, even if the state before the transition is not succeeded, not only the bus master 2 defined in the initial setting is always given the priority right, but also the bus master select signal 18 is switched so that the bus master 3 is always given the priority right. Can be set to give. If the bus master select signal 18 has a 2-bit configuration and can be switched between 0, 1 and 2, when the low power consumption mode ends, the bus master 2 is given priority and the bus master 3 is given priority. Can be freely selected, or a state in which the bus master 4 is given priority can be freely selected.

FIG. 11 is an explanatory diagram of the arbitration method of the specific example 2 when such a bus master select signal has a 2-bit configuration. In each of the examples shown in this figure, since the operation before the transition to the low power consumption mode is not succeeded, the contents of the PSM priority select signal (PSMSET) 15 are all "0". In this example, when the bus master select signal (REQSEL) 18 is "0", the previous bus master (BM3 → BM2) is changed to "1".
In the case of, the priority is transferred to itself (BM3 → BM3), and in the case of “2”, the priority is set to the next bus master (BM3 → BM4).

FIG. 12 is an explanatory diagram of the priority order change of the concrete example 2 as described above. In (a), the priority is set in the order of the bus masters 2, 3 and 4 by the round robin method in the normal operation. On the other hand, as shown in (b), when the content of the bus master select signal is set to "0" and the low power consumption mode is entered with the priority given to the bus master 3, when the operation is started again, 2 is given priority first. On the other hand, as shown in (c),
When the content of the bus master select signal 18 is "1", when the bus master 3 shifts to the low power consumption mode in the state where the bus master 3 has the priority right, when the operation is restarted, the priority right is given to the same bus master 3 first. Given. Further, as shown in (d), when the content of the bus master select signal 18 is "2" and the operation is restarted in the same state, the next bus master 4 is given the priority right first. Such control is realized by incrementing the value of the priority setting counter 35 shown in FIG. 3 by the value specified when the operation is restarted.

<Effect of Concrete Example 2> As described above, P
When the operation is restarted after shifting to the low power consumption mode by adding the bus master select signal to the SM priority select signal, it becomes possible to first give priority to any bus master. Further, since the designated switching can be performed in a programmable manner under the control of the host processor, the degree of freedom of system operation is expanded.

<Specific Example 3> FIG. 13 shows a bus use right arbitration circuit of a specific example 3. In this example, an interrupt signal (NMINT) is added to the circuit of the concrete example 2 described with reference to FIG.
Is input. Other parts are the same as those of the first and second specific examples.

FIG. 14 shows an internal circuit block diagram of the arbitration module of the third specific example. As shown in this figure, in the third specific example, the configuration of the determination circuit 17 is the second specific example.
Is exactly the same as The interrupt signal (NMINT) 20 is input to the control circuit 14. This specific example has a configuration capable of switching to the low power consumption mode by the low power consumption mode signal 13 similarly to the specific examples 1 and 2 already described. However, the purpose of this example is to input the interrupt signal 20 to the control circuit 14 at an arbitrary timing when the round-robin arbitration method is executed, and unconditionally give priority to a predetermined bus master set in advance. The purpose is to give the right. Therefore, this specific example can be implemented without necessarily shifting to the low power consumption mode. In this specific example, which bus master is given priority when the interrupt signal 20 is input can be determined by the content of the select signal 19 by the bus master select signal 18 described in the specific example 2. The point is characteristic.

FIG. 15 shows an operation time chart of the circuit of the third specific example. (A) to (h) are signals of various parts of the circuit,
(A) is the operation clock 12, (b) is the interrupt signal 2
0, (c), (d) and (e) show processor bus request signals 5, 7, 9 and (f), (g) and (h) show processor bus use permission signals 6, 8 and 10. . Here, for example, it is assumed that the processor bus request signals 5, 7, 9 are simultaneously output from all the bus masters 2, 3, 4 at time t1.
That is, at time t1, these signals simultaneously switch from "1" to "0". At this point, the bus master 2 has priority, so that the processor bus use permission signal switches from "1" to "0" at time t2 one clock later, as shown in (f).

Next, as shown in (c), when the bus master 2 releases the bus right at time t3, as shown in (f), time t is reached.
4, the processor bus use permission signal 6 is changed from "0" to "1"
Switch to. At the same time, as shown in (g), the processor bus use permission signal 8 switches from "1" to "0" and gives the bus right to the bus master 3. After that, at time t5, the interrupt signal was asserted for only one clock. At this time, as shown in (c), (d), and (e),
It is assumed that all the bus masters 2, 3, 4 are outputting the processor bus request signals 5, 7, 9. However, since the priority is transferred to the bus master 2 designated in advance by the input of the interrupt signal 20, the processor bus use permission signal 6 is changed from "1" to "0" at time t7 as shown in (f) of the figure.
Switch to. In this way, the bus master 2 is forcibly given permission to use the bus. After that, when the bus master 2 releases the bus right at time t8, the bus right is given to the bus master 4 again as shown at time t9 in the previously set order. Note that such control is realized by resetting the priority setting counter 35 of the control circuit shown in FIG. 3 with an interrupt signal.

FIG. 16 is an explanatory diagram of the arbitration method of the third specific example. As described above, in this example, the priority is controlled so that the bus master 2 is always given priority when an interrupt occurs. That is, as shown in FIG.
Even if an interrupt occurs while 3 and 4 have the usage right, the usage right is always transferred to the bus master 2.

FIG. 17 is an explanatory diagram of the priority order change of the third specific example. (A), (b), (c), and (d) in the figure are of the same format as described in the concrete example 1 and the concrete example 2 so far. This example shows that the priority is transferred to the bus master 2 whenever an interrupt occurs. This is constant regardless of the presence or absence of the low power consumption mode. Here, for example, according to the contents of the bus master select signal 18 and the select signal 19 shown in FIG. 14, the bus master 3 and the bus master 4 other than the bus master 2 are given the highest priority after the interrupt is generated in the same manner as in the second specific example. Control is also possible.

<Effect of Concrete Example 3> As described above,
According to the third specific example, an interrupt signal is input to the control circuit 14 of the arbitration module, and when the interrupt signal is input, a certain bus master can be immediately given priority. When an interrupt occurs and it is desired to quickly process the interrupt, it is possible to appropriately deal with the problem and perform an efficient process.

<Fourth Embodiment> FIG. 18 shows a block diagram of a bus use right arbitration circuit of a fourth embodiment. This circuit is
For the circuit of the concrete example 3 shown in FIG.
NTSET) 21 has been entered. The other circuit configuration is exactly the same as that of the third embodiment.

FIG. 19 shows an internal circuit of the arbitration module of the fourth specific example. In this figure, the difference from the third embodiment is that a mask circuit 22 is provided. An interrupt signal (NMINT) 20 and an interrupt determination signal 21 are input to the mask circuit 22. In this case, when the interrupt determination signal 21 is "0", the interrupt select signal (INTOUT) 23 is set to "0" to notify the control circuit 14 of the interrupt. On the other hand, when the interrupt determination signal 21 is “1”, the mask circuit 22 interrupts the interrupt signal 20, the interrupt select signal 23 remains at the high level, and the control circuit 14 is not notified of the interrupt.

That is, the operation similar to that in the concrete example 3 is performed in the state where the interrupt is notified, and the operation similar to that in the concrete example 2 is performed in the state where the interrupt is not notified. Of course, this specific example does not necessarily require the transition to the low power consumption mode signal. That is, by appropriately interrupting the interrupt signal, forcible change of the priority order due to the occurrence of the interrupt is prevented as necessary, or the priority order switching by the interrupt is permitted. Other circuit configurations and operations are similar to those shown in the third specific example.

FIG. 20 shows an interrupt processing operation time chart of the fourth specific example. As shown in the figure, the operation clock 12 is shown in (a), the interrupt determination signal 21 is shown in (b), the interrupt signal 20 is shown in (c), and the interrupt select signal 23 is shown in (d) to show the operation. As shown in this figure,
When the interrupt determination signal is switched from “1” to “0” and asserted at time t1, interrupt signal 2 is output at time t2.
When 0 is input and is switched from "1" to "0", the interrupt select signal 23 is also switched from "1" to "0" at the same time. As a result, the control circuit is notified of the interrupt.

FIG. 21 shows an interrupt mask operation time chart. Here, the operation when the interrupt signal 20 is masked is shown. The signals shown in (a) to (d) are the same as those shown in FIG. In the figure, the interrupt determination signal shown in (b) remains at the level of "1". Therefore, even if the interrupt signal 20 is switched from "1" to "0" at time t1 as shown in (c), the interrupt select signal 2 is changed as shown in (d).
There is no change in 3. Therefore, the interrupt signal is masked.

<Effect of Concrete Example 4> As described above,
According to the specific example 4, since the interrupt signal can be masked at an arbitrary timing, it is possible to freely select forcible priority order switching by the interrupt signal and normal operation not using the interrupt signal.

[Brief description of drawings]

FIG. 1 is a bus usage right arbitration circuit according to a specific example 1;

FIG. 2 is an internal circuit of an arbitration module of Specific Example 1.

FIG. 3 is a block diagram of a control circuit.

FIG. 4 is an explanatory diagram of a round robin type arbitration method.

FIG. 5 is an explanatory diagram of priority change according to the first specific example.

FIG. 6 is an operation time chart when priority is not inherited.

FIG. 7 is an operation time chart when the priority order is succeeded.

FIG. 8 is a bus use right arbitration circuit according to a specific example 2;

FIG. 9 is an internal circuit of an arbitration module of Concrete example 2.

FIG. 10 is an operation time chart of the circuit of the second specific example.

FIG. 11 is an explanatory diagram of an arbitration method of specific example 2.

FIG. 12 is an explanatory diagram of priority change according to the second specific example.

FIG. 13 is a bus right-of-use arbitration circuit of the third specific example.

FIG. 14 is an internal circuit of an arbitration module of Concrete Example 3.

FIG. 15 is an operation time chart of the circuit of the third specific example.

16 is an explanatory diagram of an arbitration method of specific example 3. FIG.

FIG. 17 is an explanatory diagram of priority change according to the third specific example.

FIG. 18 is a bus right-of-use arbitration circuit of the fourth specific example.

FIG. 19 is an internal circuit of an arbitration module of Concrete Example 4.

FIG. 20 is an interrupt processing operation time chart of the circuit of the fourth specific example.

FIG. 21 is an interrupt mask operation time chart of the circuit of specific example 4;

[Explanation of symbols]

 1 Arbitration Module 2, 3, 4 Bus Master 5, 7, 9 Processor Bus Request Signal 6, 8, 10 Processor Bus Use Enable Signal 11 Processor Bus 12 Operation Clock 13 Low Power Consumption Mode Signal 15 PSM Priority Select Signal

Claims (4)

[Claims] 1. A plurality of bus masters connected via a processor bus, and an arbitration module that arbitrates the processor bus usage right of these bus masters, wherein the arbitration module prioritizes each bus master in a round robin manner. When the system enters the low power consumption mode and exits the low power consumption mode, it takes over the prioritization immediately before the transition to the low power consumption mode or always gives priority to a certain bus master first. A bus use right arbitration circuit, which is provided with a determination circuit for determining whether to give the right. 2. A plurality of bus masters connected via a processor bus, and an arbitration module for arbitrating processor bus usage rights of these bus masters, wherein the arbitration module prioritizes each bus master in a round-robin manner. In addition to the above, when the system shifts to the low power consumption mode and ends the low power consumption mode, a determination circuit for determining the bus master designated to give the priority right first is provided. Bus right arbitration circuit. 3. A plurality of bus masters connected via a processor bus, and an arbitration module that arbitrates the processor bus use right of these bus masters, wherein the arbitration module prioritizes each bus master in a round robin manner. And a bus right arbitration circuit which, when a predetermined interrupt signal is input, gives priority to a bus master designated in advance corresponding to the interrupt signal. 4. The bus use right arbitration circuit according to claim 3, further comprising a mask circuit for masking the interrupt signal at an arbitrary timing.