JPH09326444A - Semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the operation speed, without increasing the channel width of row selectors by arranging nonvolatile memory cells of MIS transistors and row selectors so that channels directions are orthogonal and placing the channel width of the row selectors in the length direction of row selection wirings. SOLUTION: Memory cells MC are disposed near cross points of rectangular sub-data lines SDL extending vertically on a semiconductor substrate 1 and rectangular word lines WL extending perpendicularly to the SDL. Sub-data selection MOSFET QS, QD are series connected to sub-data line selection MOSFET QSO, QDO along memory cell current paths. This reduces the capacitance, compared with that in the case where the mutually adjacent MOSFET Qs are isolated by forming them on different conductivity types semiconductor regions. Thus the load capacitance of the sub-data line SDL is reduced to improve the operation speed of the MOSFET Q.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and more particularly to a semiconductor integrated circuit device having a NOR gate type mask ROM and a technique effectively applied to the manufacturing method thereof. .

[0002]

2. Description of the Related Art With improvements in the performance and functions of microprocessors and the like, the performance of devices having microprocessors has been remarkably improved, and along with this, there has been a demand for faster mask ROM access speeds.

Techniques examined by the inventor of the present invention for a mask ROM that realizes such high-speed access include, for example, the Institute of Electronics, Information and Communication Engineers, published in September 1992,
Technical report of IE, technical report of eye
TECHNICAL REPORT OF IEICE, SDM 92-68 (SDM92-68), ICD 92-67 (ICD92-67), P35-P41, "Access time 65ns 16Mbit CMOS mask ROM "
, Which is a NOR gate type CMOS (Complimentary Metal Oxide Semiconducto).
r) Mask ROM has been described.

The layout of the memory cell array of the mask ROM and its peripheral circuits is as follows.

In the memory cell array of the mask ROM, a plurality of word lines and a plurality of sub bit lines are arranged so as to be orthogonal to each other. A memory cell is arranged near the intersection of the word line and the sub bit line.

The sub bit line is formed of an N ⁺ diffusion layer, and one end side thereof is electrically connected to the main bit line via a bank selection transistor.

The bank selection transistor is arranged so that the direction in which the channel current flows (channel direction) is the same as the channel direction of the memory cell, and the channel width thereof is the bank selection for forming the gate electrode. It is arranged so as to be set in the width direction of the line. The source / drain region of this bank select transistor is formed of the same diffusion layer as the sub bit line.

[0008]

However, the present inventor has found that the above-mentioned mask ROM structure has the following problems in an attempt to improve the operating speed and reduce the power consumption.

In order to increase the driving ability of the bank selection transistor, it is necessary to increase its transconductance.
For that purpose, it is effective to increase the channel width.However, in the case of the above technique, since the channel width is set in the width direction of the bank select line, the channel width is increased to increase its mutual conductance. In that case, the width of the bank selection line must be widened, which leads to an increase in chip size.

Therefore, the mutual conductance cannot be easily changed. Therefore, the read current of the memory cell is reduced by the amount corresponding to three stages of the memory cell. That is, there is a problem that power consumption cannot be reduced and the driving capability of the bank selection transistor cannot be improved unless the chip size is increased.

Further, the source of the bank selection transistor
Since the impurity introduction step for forming the drain region is usually formed at the same time as the impurity introduction step for forming the sub-bit line having a relatively high resistance, the power consumption is reduced and the driving capability of the bank select transistor is reduced. There is a problem that it cannot be improved.

An object of the present invention is to provide a technique capable of improving the operation speed of a semiconductor integrated circuit device having a mask ROM without causing a significant increase in chip size.

Another object of the present invention is to provide a technique capable of reducing power consumption in a semiconductor integrated circuit device having a mask ROM without causing a significant increase in chip size.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0015]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

According to another aspect of the semiconductor integrated circuit device of the present invention, a plurality of word lines arranged on a semiconductor substrate, a plurality of data lines intersecting with the extending direction of the plurality of word lines, A plurality of nonvolatile memory cells arranged near the intersections of the plurality of word lines and the plurality of data lines, and connected in series to each data line for selecting a predetermined data line from the plurality of data lines. A plurality of column selection MIS transistor portions, the plurality of data lines are formed by introducing a predetermined impurity into the semiconductor substrate, and each of the plurality of nonvolatile memory cells is one of two different types of information. The column selection MIS transistor section is constituted by a part of column selection wirings whose gate electrodes extend in a direction intersecting the plurality of data lines. (A) the MIS transistors forming the plurality of nonvolatile memory cells and the plurality of column selection MIS transistor portions are arranged such that their channel directions are orthogonal to each other. (B) The plurality of column selection MIS transistor portions are arranged such that the channel width thereof is set in the longitudinal direction of the column selection wiring.

In the semiconductor integrated circuit device of the present invention, an element isolation portion having a field insulating film is provided between the plurality of column selection MIS transistor portions.

Also, in the method of manufacturing a semiconductor integrated circuit device of the present invention, an impurity introducing step for forming the plurality of data lines and a source / source of the column selection MIS transistor section are performed.
The impurity introducing step for forming the drain region is separately performed.

Also, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the same impurity is added to the channel region of the second column selection MIS transistor during the impurity introducing step for forming the plurality of data lines. It has a step of introducing the same concentration at the same time.

Also, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the source / drain regions of the first column selection MIS transistor, the first and second regions of the first column select MIS transistor, and the first and second column select MIS transistors are included in the impurity introduction step for forming the plurality of data lines. The second column selection MIS transistor has a step of simultaneously introducing the same impurity into the source / drain region of the second column selection MIS transistor and the channel region of the second column selection MIS transistor at the same concentration.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings (note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments. , The repeated explanation is omitted).

(Embodiment 1) FIG. 1 is an explanatory diagram of a configuration of a semiconductor integrated circuit device which is an embodiment of the present invention, and FIG. 2 is a main part of a memory area of the semiconductor integrated circuit device of FIG. 1 and its periphery. FIG. 3 is a circuit diagram of a region, FIG. 3 is a state diagram of the semiconductor integrated circuit device of FIG. 1 at the time of reading, FIG. 4 is a plan view of essential parts of the semiconductor integrated circuit device of FIG. 1, and FIG. 5 is a cross section taken along line V-V of FIG. Fig. 6, Fig. 6 is a sectional view taken along line VI-VI of Fig. 4, and Fig. 7 is VII of Fig. 4.
-VII is a sectional view taken along the line VII, and FIG. 8 is a sectional view taken along the line VIII-VIII in FIG.

The semiconductor integrated circuit device according to the first embodiment is
For example, a NOR gate type mask RO as shown in FIG.
M (Mask Read Only Memory; hereinafter abbreviated as MROM)
It is.

Address buffer circuit AB of this MROM
Is a circuit for converting the address signals A0 to A18 inputted from the outside of the semiconductor integrated circuit device into internal address signals, and then transmitting them to the row decoder circuit XD and the column decoder circuit YD.

The address buffer circuit AB is divided into a row address buffer circuit and a column address buffer circuit. The row address buffer circuit is a circuit for selecting a word line, and the column address buffer circuit is a circuit for selecting a data line.

The row decoder circuit XD is a circuit which receives a signal from the address buffer circuit AB and selects a predetermined one word line. The column decoder circuit YD is a circuit that receives a signal from the address buffer circuit AB and selects a predetermined one column selection wiring.

In the memory area MA, a plurality of word lines extending in the horizontal direction in FIG. 1, a plurality of data lines extending in a direction orthogonal to the word lines, and a plurality of data lines are arranged in the vicinity of an intersection of the word lines and the data lines. And a plurality of memory cells (nonvolatile memory cells) are formed.

This memory cell has a High (hereinafter simply referred to as "H") signal or a Low (hereinafter simply referred to as "L") signal.
It is a minimum unit of a memory that stores either one of the binary data of the signal.

The column gate circuit YG is a circuit for a selection switch for selecting a predetermined data line in the memory area MA.

The sense amplifier circuit SA is a circuit for detecting and amplifying a minute voltage (or current) transmitted to the data line, and is electrically connected to the 3-state output buffer circuit DOB.

This 3-state output buffer circuit DOB is
It is a circuit that amplifies a signal read from a memory cell so that it can be transmitted to an external device without being attenuated in an intermediate wiring path, and the amplified signal is output signals D0 to D31 according to a control signal from a control circuit section C. Is a circuit for outputting to outside.

The control circuit section C includes an address buffer circuit A
A circuit section for controlling the output of the MROM by controlling the operations of the B and 3-state output buffer circuits DOB, etc.
Control logic circuit CL, inverter circuit CINV,
It has an AND circuit CAND. In addition, the bar O of the code
E is an output enable signal, a symbol bar CE
Indicates a chip enable signal.

Next, FIG. 2 shows a circuit diagram of one unit of memory block in the memory area MA and its peripheral circuit area.

In this memory cell block, for example, 32
Word lines WL0 to WL32 and a plurality of sub data lines S
DL are arranged so as to be orthogonal to each other, and the word lines WL0 to WL32 and sub data lines SDL are arranged.
For example, the one-transistor type memory cells MC (MC1 to MC4) are arranged in the vicinity of the intersection with.

The word lines WL0 to WL32 are made of, for example, low resistance polysilicon, and a part thereof also serves as the gate electrode of the memory cell MC.

The sub-data line SDL is composed of, for example, an n-type semiconductor region formed on a semiconductor substrate, and a part thereof also serves as the source / drain region of the memory cell MC.

Each sub-data line SDL has a column selection M.
It is electrically connected to the main data line MDL via the OS / FET section Q. In this case, the two sub data lines S
Each of the DLs is electrically connected to one main data line MDL via the column selection MOS / FET section Q.

The column selection MOS / FET section Q has a predetermined sub-data line SDL among a plurality of sub-data lines SDL.
Is a switching element for selecting a sub data line selection MOS / FET (first column selection MOS transistor) QS, QD, and a sub data line selection MOS / FET (second Column select MOS transistor).

One sub-data line selection MOS / FETQ
The threshold voltages of S and QD are column selection wirings YLS0 and YLS.
It is composed of an enhancement type MOS-FET set higher than the steady-state potential of 1, YLD0 and YLD1.

On the other hand, the other sub data line selection MOS · F
The threshold voltage of ET is column selection wiring YLS0, YLS1,
It is composed of a depletion type MOS-FET set to be lower than the steady potential of YLD0 and YLD1. Therefore, it is not shown in the circuit diagram of FIG.

Sub-data line selection MOS / FET QS, QD
And a sub data line selection MOS connected in series to this
The gate electrodes of the FETs are the source side column selection wirings YLS0, YLS1 and the data side column selection wirings YLD0,
It is electrically connected to YLD1.

The source side column selection wirings YLS0, YLS1
Also, two column selection wirings YLD0 and YLD1 on the data side are provided on each of the source side and the data side so as to sandwich a group of word lines WL0 to WL32.
It is arranged parallel to L32.

The main data line MDL is made of, for example, aluminum (Al) or an Al alloy, and is electrically connected to the ground potential G or the sense amplifier circuit SA via the main data line selection MOS • FETQMS, QMD.

Main data line selection MOS / FET QMS,
QMD is a switching element for selecting one of the plurality of main data lines MDL, and each gate electrode thereof has a main column selection wiring YMLS on the source side.
And the main column selection wiring YMLD on the data side.

The memory cell MC is a minimum unit of a memory for storing the above-mentioned "H" or "L" signal, and is an enhancement type MOS.FET (Enhancement Type MOSFE).
T, hereafter referred to as EMOS) and enhancement type MOS-FET (Enhancement Enhancemen)
t Type MOSFET, hereinafter referred to as EEMOS).

In this EMOS, a current flows between the source and the drain when a voltage higher than the threshold voltage is applied between the source and the drain. In the EEMOS, no current flows between the source and the drain even if a voltage equal to or higher than the threshold voltage equal to that of the EMOS is applied between the source and the drain. As a result, the "H" or "L" signal is stored. Note that, in FIG. 2, the memory cells MC of EEMOS are hatched.

Next, the data read operation will be described with reference to FIG.
This will be described with reference to FIG.

When the memory cell MC2 is selected, for example, the following is performed. First, the word line WL1 connected to the gate electrode of the memory cell MC2 and the memory cell MC2
The main column selection wirings YMLS1 and YMLD1 for selecting the memory cell group of the predetermined bit to which is belongs are selected.

Then, of the plurality of main data lines MDL, one source-side main data line MDL S1 is GND.
By connecting to the potential and another main data line MDLD1 on the data side to the sense amplifier circuit SA, the 4-bit memory cells MC1 to MC4 can be selected.

Then, a column selection wiring YSL1, for selecting the connected sub data line SDL of the memory cell MC2.
By selecting YDL1, one of the 4-bit memory cells MC1 to MC4 can be selected.

Since this memory cell MC2 is an EMOS, a current flows from the sense amplifier circuit SA side to the ground potential G via the memory cell MC2 as shown by the memory cell current path. This is detected by the sense amplifier circuit SA,
Take out as "H" signal output.

Similarly, memory cells MC1, MC3, MC
When selecting 4, the main column select wirings YMLS0 to YMLS0 to YML are selected as shown in FIG. 3 with the word line WL1 selected.
MLS3, YMLD0 to YMLD2 and column selection wiring YSL0,
Set the potential of YSL1, YDL0, YDL1.

Next, FIG. 4 shows a plan view of the main parts of the memory block and peripheral circuits in the memory area MA, and FIGS. 5 to 8 are sectional views thereof.

On the semiconductor substrate 1, the memory cells MC of the memory block include a plurality of sub-data lines SDL each having a rectangular plane shape extending in the vertical direction in FIG. 4 and a rectangular sub-data line extending in a direction orthogonal to the sub data lines SDL. Are arranged in the vicinity of the intersections with the plurality of word lines WL. The memory cell MC0
Indicates the selected memory cell. The arrows indicate the memory cell current paths.

Each memory cell MC is set to EMOS or EEMOS by a predetermined impurity introduced into its channel region by a predetermined amount, and in each case, a pair of sub data lines SDL and, for example, silicon dioxide (SiO ₂ ) are formed.
And a gate electrode 3g formed of a part of the word line WL.

The sub-data line SDL is formed by introducing, for example, n-type impurity phosphorus or arsenic (As) into the upper portion of the semiconductor substrate 1, and its resistance value is, for example, 100 Ω to 400.
It is set to about Ω.

One end of each sub-data line SDL is connected to the main data line M via the sub-data line selection MOS-FETs QS and QD and the sub-data line selection MOS-FETs QS0 and QD0.
It is electrically connected to the DL.

This sub data line selection MOS • FET QS,
The QD and the sub data line selection MOS • FETs QS0 and QD0 are connected in series along the memory cell current path. However, the sub-data line selection MOSs adjacent to each other
The FETs QS and QD and the sub-data line selection MOS • FETs QS0 and QD0 adjacent to each other are arranged so as to be oblique to each other.

Further, the column selection MOS / FE adjacent to each other
A field insulating film 4 for element isolation made of, for example, SiO ₂ is formed between the T portions Q. A channel stopper region is formed in the semiconductor substrate 1 below the field insulating film 4 by introducing, for example, p-type impurity such as boron.

As a result, the column selection MOSs adjacent to each other are
The capacitance can be reduced as compared with the case where the FET part Q is separated by forming semiconductor regions of different conductivity types. Therefore, the load capacitance of the sub data line SDL can be reduced. Further, the driving force of the column selection MOS / FET section Q can be improved. Therefore, the column selection MO
It is possible to improve the operating speed of the S-FET section Q.

The sub-data line selection MOS • FETs QS, QD, QS0, QD0 of each column selection MOS • FET section Q has a memory cell M whose channel direction (direction in which channel current flows).
It is arranged so as to be orthogonal to the channel direction of C, and the channel width of the column selection wirings YSL0, YSL1,
It is arranged so as to be set in the extending direction of YDL0 and YDL1.

In this way, the channel width is set to the column selection wiring YSL.
By setting 0, YSL1, YDL0, YDL1 in the extending direction, the channel width can be made relatively wide. Therefore, the drive current of the column selection MOS / FET section Q can be increased, so that the sub data line selection MOS
・ It is possible to improve the operating speed of FET QS and QD.

Such a sub data line selection MOS / FE
TQS, QD, QS0, and QD0 are a pair of semiconductor regions 5a formed on the semiconductor substrate 1, a gate insulating film 2 made of, for example, SiO ₂ , and column selection wirings YSL0, YSL1, and YDL.
0, YDL1 and gate electrodes 6g1 and 6g2.

It should be noted that the sub data line selection M adjacent to each other is selected.
OS / FET QS, QD and sub data line selection MOS / FE
The common semiconductor region 5a between TQS0 and QD0 also has a function as a wiring for connecting both MOS • FETs.

Into the semiconductor region 5a, for example, the same n-type impurity phosphorus or As as the impurities contained in the sub data line SDL is introduced. However, the semiconductor region 5a is formed in a formation process different from that of the sub data line SDL. The impurity concentration is set separately from the impurity concentration of the sub data line SDL,
The resistance is set to be as low as about 50Ω to 70Ω.

That is, the sub data line selection MOS / FE
The resistance of the semiconductor regions 5a of TQS, QD, QS0, QD0 can be lowered as compared with the case where the semiconductor regions 5a are formed at the same impurity concentration at the same time when the sub data lines SDL are formed.

Therefore, the overall load resistance and load capacitance of sub data line SDL can be reduced. Also,
It is possible to improve the driving force of the sub data line selection MOS • FETs QS, QD, QS0, QD0. Therefore, it is possible to improve the operating speed of the sub data line selection MOS • FETs QS, QD, QS0, QD0.

Further, the sub data line selection MOS / FETQ
A predetermined amount of n-type impurity is introduced into the channel region below the gate electrodes 6g2 of S0 and QD0 so as to be a depletion type. Reference numeral 5b in FIGS. 7 and 8
Indicates the semiconductor region. The semiconductor region 5b is formed in a different forming process from the semiconductor region 5a and the sub data line SDL.

Such sub-data line selection MOS / FE
The semiconductor regions 5a of TQS, QD, QS0 and QD0 are electrically connected to the main data line MDL through the connection holes 8 (see FIG. 4) formed in the insulating film 7a (see FIGS. 5 to 8) on the semiconductor substrate 1. It is connected.

The insulating film 7a is made of, for example, SiO ₂ , and is thereby used for the word line WL and the column selection wiring YSL.
0, YSL1, YDL0, YDL1 etc. are covered.

As described above, according to the first embodiment, the following effects can be obtained.

(1). The sub-data line selecting MOS FETs QS, QD, QS0, QD0 of each column selecting MOS FET unit Q has a channel width of column selecting wirings YSL0, YSL1, YDL0, YD.
By arranging so as to be set in the extending direction of L1, the channel width can be made relatively wide without significantly increasing the chip size, so that the drive current of the column selection MOS / FET section Q is Can be increased.

(2). Sub data line selection MOS • FET QS,
The semiconductor region 5a of QD, QS0, QD0 and the sub data line SD
Since L and L are formed in different formation steps, compared with the case where the semiconductor region 5a of the sub data line selection MOS • FETs QS, QD, QS0, QD0 is formed at the same impurity concentration at the same time when the sub data line SDL is formed. It is possible to reduce the resistance of the semiconductor region 5a.

(3). Column selection MOS FETs adjacent to each other
By separating the section Q by the field insulating film 4, it is possible to reduce the capacitance as compared with the case where the column selecting MOS / FET sections Q adjacent to each other are separated by forming semiconductor regions of different conductivity types. .

(4). By the above (2) or (3), it is possible to reduce the overall load resistance and load capacitance of the sub data line SDL.

(5). By the above (2) or (3), it becomes possible to improve the driving force of the sub data line selection MOS • FETs QS, QD, QS0, QD0.

(6). Due to the above (1) to (5), the information read speed of the MROM can be improved without causing a large increase in the chip size of the MROM.

(7) The power consumption of the MROM can be reduced by the above (1) to (5).

(Embodiment 2) FIGS. 9 and 10 are plan views of essential parts during a manufacturing process of a semiconductor integrated circuit device according to another embodiment of the present invention.

In the second embodiment, the configuration of the semiconductor integrated circuit device is the same as that of the first embodiment. The difference is the method of manufacturing the semiconductor integrated circuit device. This will be described with reference to FIGS. 9 and 10.

First, as shown in FIG. 9, a field insulating film 4 made of, for example, SiO _{2 is} formed on the main surface of the semiconductor substrate 1.
Is formed by the Locos method or the like.

Then, during the impurity introducing step for forming the sub data line, for example, an n-type impurity phosphorus is added to the sub data line forming region and the channel region of the sub data line selecting MOS • FETs QS0 and QD0 shown in FIG. Alternatively, As is simultaneously implanted at the same concentration by an ion implantation method or the like.

As a result, the number of photomasks can be reduced by one, and the number of photolithography steps involving complicated processes such as photoresist coating, development, and baking can be reduced by one time, so that the semiconductor integrated circuit device can be manufactured. The cost can be reduced, and the reduction of the manufacturing time of the semiconductor integrated circuit device can be promoted.

After that, by subjecting the semiconductor substrate 1 to a predetermined heat treatment, the sub data line SDL is formed, and at the same time, the sub data line selection MOS • FETs QS0, QD0.
A semiconductor region 5b is formed in the channel region (see FIG. 4).

Next, the memory cell is set to EMOS or EE.
Impurity introduction processing for forming MOS is performed.

Then, for example, low resistance polysilicon is deposited on the semiconductor substrate 1 by the CVD method or the like, and then the low resistance polysilicon is patterned by the photolithography technique and the dry etching technique, as shown in FIG. Column select wirings YSL0, YSL1,
YDL0, YDL1 and word line WL are formed simultaneously.

After that, a photoresist pattern is formed so as to cover the memory cell region, and then the photoresist pattern and column selection wirings YSL0, YSL1, YDL are formed.
After the n-type impurity phosphorus or As is introduced into the semiconductor substrate 1 by the ion implantation method or the like using the 0, YDL1 as a mask, the semiconductor substrate 1 is heat-treated to form the semiconductor region 5a shown in FIG. Form.

Since the subsequent steps are the same as the normal manufacturing process of the semiconductor integrated circuit device, the description thereof will be omitted.

As described above, according to the second embodiment, the following effects can be obtained.

(1). Impurity introduction step for forming sub data lines and sub data line selection MOS • FETs QS0, Q
By simultaneously performing the step of introducing impurities into the channel region of D0, the number of photomasks can be reduced and the number of photolithography steps involving complicated processes such as photoresist coating, development and baking can be reduced by one time. Is possible.

(2). Due to the above (1), the manufacturing cost of the semiconductor integrated circuit device can be reduced.

(3). Due to the above (1), it is possible to promote the reduction of the manufacturing time of the semiconductor integrated circuit device.

(Third Embodiment) FIG. 11 is a plan view of a principal portion of a semiconductor integrated circuit device according to another embodiment of the present invention.
2 is a sectional view taken along line XII-XII in FIG.

In the third embodiment, as shown in FIGS. 11 and 12, the sub data line selection MOS FET is used.
The semiconductor regions 5a of QS, QS0, QD, and QD0, the semiconductor regions in the channel regions of the sub-data line selection MOS • FETs QS0 and QD0, and the sub-data lines SDL are formed with the same impurities at the same concentration.

However, also in the third embodiment, each sub-data line selection MOS • FET QS, QS0, QD, QD0 is
The channel direction is arranged so as to be orthogonal to the channel direction of the memory cell MC, and the channel width is arranged so as to be set in the extending direction of the column selection wirings YSL0, YSL1, YDL0, YDL1. .

In this way, the channel width is set to the column selection wiring YSL.
By setting 0, YSL1, YDL0, YDL1 in the extending direction, the channel width can be made relatively wide. Therefore, the sub data line selection MOS / FET QS, Q
Since the drive currents of S0, QD, and QD0 can be increased, it is possible to improve the operating speed of the column selection MOS / FET section Q.

The semiconductor region 5a is formed so that its end portion slightly enters below the end portion of the gate electrode 6g1 of the sub-data line selection MOS.FETs QS and QD. Further, the semiconductor region 5a is a sub data line selection MOS / FET QS
It is also formed in the channel region below the gate electrode 6g2 of 0, QD0.

Further, the column selection MOS / FE adjacent to each other
The T portion Q is electrically isolated by the p-type semiconductor region 9 around it. Into the p-type semiconductor region 9, for example, p-type impurity boron is introduced.

To manufacture such a semiconductor integrated circuit device, for example, the following is performed.

First, on the semiconductor substrate 1, a photoresist pattern is formed by the photolithography technique so that the formation region of the sub data line SDL and the formation region of the semiconductor region 5a shown in FIG. 11 are exposed.

Subsequently, for example, phosphorus or As, which is an n-type impurity, is introduced into the semiconductor substrate 1 by an ion implantation method or the like, and then the semiconductor substrate 1 is heat-treated to form the sub data line SDL and the semiconductor region 5a. Form.

That is, in the third embodiment, the sub data line SDL and the sub data line selection MOS • FETQ are used.
Three impurity introduction processes for forming the semiconductor regions 5a of S, QS0, QD, QD0 and the channel regions of the sub data line selection MOS • FETs QS0, QD0 are simultaneously performed.

As a result, the number of photomasks can be reduced by two, and the number of photolithography steps involving complicated processing such as photoresist coating, development, and baking can be reduced by two. Therefore, the semiconductor integrated circuit device can be manufactured. The cost can be reduced, and the reduction of the manufacturing time of the semiconductor integrated circuit device can be promoted.

After that, a conductor film made of, for example, low-resistance polysilicon is formed on the semiconductor substrate 1 by the CVD method or the like, and the conductor film is patterned by the photolithography technique and the dry etching technique. Column selection wiring YSL0, YSL1, Y
DL0 and YDL1 are formed.

Since the subsequent steps are the same as the method for manufacturing a normal semiconductor integrated circuit device, the description thereof is omitted.

As described above, in the third embodiment,
The following effects can be obtained.

(1). The sub-data line selection MOS • FETs QS, QD, QS0, QD0 of each column selection MOS • FET section Q has a channel width of column selection wiring YSL0, YSL1, YDL0, YD.
By arranging so as to be set in the extending direction of L1, the channel width thereof can be made relatively wide, so that it is possible to increase the drive current of the column selection MOS • FET section Q.

(2). By the above (1), the sub data line selection M
It is possible to improve the driving force of the OS • FETs QS, QD, QS0, QD0.

(3) Due to the above (1) and (2), the information read speed of the MROM can be improved without causing a large increase in the chip size of the MROM.

(4). The power consumption of the MROM can be reduced by the above (1) and (2).

(5). Impurity introducing step for forming sub-data lines, and sub-data-line selecting MOS • FETs QS, QD,
Impurity introduction process for forming the semiconductor regions 5a of QS0 and QD0, and sub data line selection MOS • FETs QS0 and QD0
By simultaneously performing the step of introducing impurities into the channel region, the number of photomasks can be reduced by two, and the number of photolithography steps involving complicated processes such as photoresist coating, development and baking can be reduced by two times. It will be possible.

(6). Due to the above (5), the manufacturing cost of the semiconductor integrated circuit device can be reduced.

(7). Due to the above (5), it is possible to promote the reduction of the manufacturing time of the semiconductor integrated circuit device.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above-mentioned first to third embodiments, and the scope is not deviated from the scope thereof. It goes without saying that various changes can be made.

For example, in the first embodiment described above, a case has been described in which the column selection MOS / FET portions adjacent to each other are separated by the field insulating film and the channel stopper region below the field insulating film. However, the present invention is not limited to this.
For example, it may be separated by a groove-shaped element separating portion.

Further, in the third embodiment, the case where the column selection MOS.FET parts adjacent to each other are separated by the p-type semiconductor region has been described, but the present invention is not limited to this, and for example, a field insulating film and A structure may be adopted in which the channel stopper region provided in the lower layer separates the layers.

In the above description, the case where the invention made by the present inventor is mainly applied to the mask ROM alone which is the field of use which is the background of the invention has been described, but the invention is not limited to this and, for example, a mask ROM is provided. It can be applied to a semiconductor integrated circuit device having a mask ROM such as a microprocessor.

[0118]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

(1) According to the semiconductor integrated circuit device of the present invention, the MIS transistors forming the plurality of nonvolatile memory cells and the plurality of column selection MIS transistor portions are arranged so that their channel directions are orthogonal to each other. In addition, the plurality of column selection MIS transistor portions are arranged such that their channel widths are set in the longitudinal direction of the column selection wirings, so that the channel width can be made relatively large without significantly increasing the chip size. Since it can be set to a wide range, it becomes possible to increase the drive current of the column selection MOS / FET section Q. Therefore, it is possible to provide a semiconductor integrated circuit device having a mask ROM with low power consumption and high read operation speed without causing a large increase in chip size.

(2) According to the semiconductor integrated circuit device of the present invention, since the element isolation portion having the field insulating film is provided between the plurality of column selection MIS transistor portions, the column selection MIS transistor portions adjacent to each other are provided. It is possible to reduce the capacitance as compared with the case where the semiconductor regions are separated by forming semiconductor regions having different conductivity types. Therefore, it is possible to provide a semiconductor integrated circuit device having a mask ROM with low power consumption and high read operation speed without causing a large increase in chip size.

(3). According to the method of manufacturing a semiconductor integrated circuit device of the present invention, an impurity introducing step for forming a plurality of data lines and a source / drain region for the column selection MIS transistor portion are formed. By performing the impurity introduction step separately, the source of the column selection MIS transistor section
It is possible to reduce the resistance of the source / drain regions as compared with the case where the drain regions are simultaneously formed with the same impurity concentration when forming the data lines. Therefore, it is possible to provide a semiconductor integrated circuit device having a mask ROM with low power consumption and high read operation speed without causing a large increase in chip size.

(4) According to the method of manufacturing a semiconductor integrated circuit device of the present invention, the same is applied to the channel region of the second column selection MIS transistor during the impurity introduction step for forming a plurality of data lines. By introducing impurities at the same concentration at the same time, it is possible to reduce the number of photomasks by one, and also to reduce the number of photolithography steps that require complicated processes such as photoresist coating, development, and baking by one time. Therefore, it is possible to reduce the manufacturing time of the semiconductor integrated circuit device having the mask ROM with low power consumption and high read operation speed, and to provide the semiconductor integrated circuit device at low cost.

(5) According to the method for manufacturing a semiconductor integrated circuit device of the present invention, the source / drain regions of the first column selection MIS transistor are formed during the impurity introduction step for forming the plurality of data lines. By including the step of introducing the same impurity into the source / drain region of the second column selection MIS transistor and the channel region of the second column selection MIS transistor at the same concentration at the same time, the photomask is made
In addition to reducing the number of sheets, it is possible to reduce the number of photolithography processes that require complicated processes such as photoresist coating, development, and baking by twice. Therefore,
Mask R with low power consumption and high read operation speed
The manufacturing time of the semiconductor integrated circuit device having the OM can be shortened, and the semiconductor integrated circuit device can be provided at low cost.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a configuration of a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a circuit diagram of a main part of a memory area and its peripheral area of the semiconductor integrated circuit device of FIG.

FIG. 3 is a state diagram at the time of reading of the semiconductor integrated circuit device of FIG.

FIG. 4 is a plan view of a main part of the semiconductor integrated circuit device of FIG.

5 is a cross-sectional view taken along line VV of FIG.

FIG. 6 is a sectional view taken along line VI-VI of FIG. 4;

7 is a sectional view taken along line VII-VII of FIG.

8 is a cross-sectional view taken along the line VIII-VIII of FIG.

FIG. 9 is a plan view of a main portion during a manufacturing process of a semiconductor integrated circuit device which is another embodiment of the present invention.

10 is a main-portion plan view of the semiconductor integrated circuit device during the manufacturing process, following FIG. 9; FIG.

FIG. 11 is a plan view of a principal portion of a semiconductor integrated circuit device according to another embodiment of the present invention.

FIG. 12 is a sectional view taken along line XII-XII of FIG. 11;

[Explanation of symbols]

1 semiconductor substrate 2 gate insulating film 3g gate electrode 4 field insulating film 5a semiconductor region 5b semiconductor region 6g1 gate electrode 6g2 gate electrode 7a insulating film 8 connection hole AB address buffer circuit A0 to A18 address signal XD row decoder circuit YD column decoder circuit MA Memory area YG column gate circuit SA sense amplifier circuit C control circuit section CL control logic circuit CINV inverter circuit CAND AND circuit DOB 3-state output buffer circuit D0 to D31 output signal WL0 to WL32 word line SDL sub data line MDL main data line MC , MC1 to MC4 memory cell Q column selection MOS / FET section QS, QD sub data line selection MOS / FET (first column selection MIS transistor) QS0, QD0 sub data line selection MOS / FET (second column selection MIS transistor) ) YSL0, YSL1, YDL0, YDL1 Column selection wiring QMS, QMD Main data line selection MOS / FET YMLS0 to YMLS4, YMLD0 to YMLD3 Main column selection wiring

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Kikuo Sakai 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitate Cho-LS Engineering Co., Ltd.

Claims (8)

[Claims] 1. A plurality of word lines arranged on a semiconductor substrate, a plurality of data lines intersecting with the extending direction of the plurality of word lines, a plurality of word lines and a plurality of word lines. A plurality of non-volatile memory cells arranged near intersections with the data lines, and a plurality of column selection MIS transistors serially connected to each data line for selecting a predetermined data line of the plurality of data lines And a plurality of data lines in which a predetermined impurity is introduced into the semiconductor substrate, and each of the plurality of nonvolatile memory cells holds one of two different types of information. The column selection MIS transistor section is a semiconductor integrated circuit device including a part of a column selection wiring whose gate electrode extends in a direction intersecting with the plurality of data lines. And (a) disposing the MIS transistors forming the plurality of nonvolatile memory cells and the plurality of column selection MIS transistor portions so that their channel directions are orthogonal to each other, and (b) the plurality of 2. The semiconductor integrated circuit device according to claim 1, wherein the column selection MIS transistor portion is arranged such that its channel width is set in the longitudinal direction of the column selection wiring. 2. The semiconductor integrated circuit device according to claim 1, wherein each of the plurality of column selection MIS transistor units connects a first column selection MIS transistor and a second column selection MIS transistor in series. The threshold voltage of the first column selection MIS transistor is set higher than the steady potential of the column selection wiring, and the second column selection MIS transistor has the threshold voltage of the column selection wiring. A semiconductor integrated circuit device characterized by being set lower than a steady potential. 3. The semiconductor integrated circuit device according to claim 1, wherein the plurality of data lines and the column selection MI are provided.
A semiconductor integrated circuit device characterized in that a source / drain region of an S transistor portion is formed separately. 4. The semiconductor integrated circuit device according to claim 1, wherein the plurality of data lines and the column selection MI are provided.
A semiconductor integrated circuit device, wherein a source / drain region of an S transistor portion is formed in the same step. 5. The semiconductor integrated circuit device according to claim 1, wherein an element isolation portion having a field insulating film is provided between the plurality of column selection MIS transistor portions. Integrated circuit device. 6. The method for manufacturing a semiconductor integrated circuit device according to claim 1, 2, or 3, wherein an impurity introducing step for forming the plurality of data lines and a source / drain of the column selection MIS transistor portion are included. A method for manufacturing a semiconductor integrated circuit device, which comprises separately performing an impurity introducing step for forming a region. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 2, wherein a channel region of the second column selection MIS transistor is formed in the impurity introduction step for forming the plurality of data lines. Also has a step of introducing the same impurities at the same concentration at the same time. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 1, 2, or 4, wherein the first column select MIS transistor is included in an impurity introduction step for forming the plurality of data lines. Source / drain regions of the second
2. The method for manufacturing a semiconductor integrated circuit device, further comprising the step of simultaneously introducing the same impurity into the source / drain region of the column selection MIS transistor and the channel region of the second column selection MIS transistor at the same concentration.