JPH09325830A - Clock supply system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow plural devices to obtain clocks of the same timing by distributing clocks from a clock supplying device to plural devices. SOLUTION: A clock feeder 121 is connected from the clock supplying device 100 to plural devices 141 to 143 in cascade and folded from the farmost device 143, the folded clock feeder 122 is connected to plural devices 141 to 143 in cascade in the reverse direction and an intermediate phase of a clock phase difference between both the feeders 121, 122 is used for a clock in the device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply system between devices, and more particularly to a clock timing correction device in a clock supply system.

[0002]

2. Description of the Related Art As an example of the prior art, Japanese Patent Laid-Open No. 4-728.
There is an invention described in Japanese Patent No. 37. The invention described in Japanese Patent Application Laid-Open No. 4-72837 is a data transmission system in which data is connected from a main data communication device to a plurality of sub data communication devices by a transmission path, and a plurality of main data communication devices and a plurality of predetermined ID numbers are provided. In the main data communication device, a dedicated data line for measuring the transmission delay time between the sub data communication devices and a clock line for synchronizing the main data communication device and the plurality of sub data communication devices are provided. , The delay time of the transmission line between the main data communication device and the sub data communication device is measured by using a dedicated line for measuring the transmission delay time, and the delay time of the data transmission line is preset according to the measurement result. This is a data transmission delay adjustment method that has a circuit in the main data communication device.

[0003]

In this conventional invention,
Since the synchronization adjustment circuits for compensating for the delay time are concentrated in the main data communication device as many as the plurality of sub data communication devices, there is a problem that the reliability of the system deteriorates.

Further, the ID number in the data is used to measure the delay amount between the main data communication device and the sub data communication device, and it is necessary to take in a plurality of bits of data to detect the ID number. If the transmission clock is fast or the transmission delay is very small, it is difficult to synchronize the delay times.

Furthermore, since a dedicated line for measuring the delay amount is required in addition to the transmission data line, there is a problem that the number of wirings between the main data communication device and the sub data communication device increases.

[0006]

According to the present invention, in a system for supplying a clock from a clock source device to a plurality of devices, a clock supply line is connected in cascade from the clock source device to the plurality of devices, and the farthest end is provided. Fold the clock supply line from the other device and connect the return clock supply line in cascade to multiple devices in the opposite direction, and use the middle phase of the phase difference between the clocks of the clock supply line and the return clock supply line as the internal clock of the device. It is characterized by doing.

In the present invention, the clock supply line connects a plurality of devices in a cascade, so that the wiring between the devices becomes simple. In addition, the circuit that measures the phase difference between the clocks and creates the clocks that have been subjected to the timing compensation is distributed among a plurality of devices and is highly reliable. Furthermore, since the phase difference between the clocks is directly measured, the timing can be compensated even with a high-speed clock.

[0008]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the clock supply system of the present invention. The system of FIG.
The device 100 that is the source of the clock, the clock supply line 121 from the device 100, and the return clock supply line 122 in which the clock supply line 121 is returned at the farthest end.
And the clock supply line 121 and the folded clock supply line 1
22 is configured by the devices 141, 142, 143 retracted. The devices 141, 142, 143 include
The clocks of the same phase need to be supplied, but the device 1
41, 142, 143 and the device 1 which is the supply source of the clock
Since the distance to 00 is not the same, the clock of the clock supply line cannot be used as it is.

The principle of matching the clock phases will be described with reference to FIG. The device 141 receives the clock from the point A1 of the clock supply line 121 and the clock from the point B1 of the folded clock supply line 122. The clock delay time from the device 100 to the A1 point is τ1, and the clock delay time from the A1 point to the farthest end is τ.
2. Set the clock delay time from the farthest end to point B1 to τ
3, assuming that the delay time of the clock from the B1 point to the device 100 is τ4, the clock at the A1 point is delayed by τ1.
41, and the clock at the point B1 reaches the device 141 with a delay of τ1 + τ2 + τ3. If the clock having a delay time intermediate between the delay time of the clock at the point A1 and the delay time of the clock at the point B1 is the clock at the point C1, the delay time of the clock at the point C1 is 1/2 (τ1 + τ1 + τ2 + τ).
3) and τ2 and τ3 follow the same route, so τ
2 = τ3, and the delay time at point C1 is τ1 + τ2.

In the device 142, the clock from the point A2 of the clock supply line 121 and the folded clock supply line 122.
The clock from point B2 is pulled in. Device 10
The delay time of the clock from 0 to A2 point is τ5, the delay time of the clock from A2 point to the farthest end is τ6, the delay time of the clock from the farthest end to B2 point is τ7, and the delay time from B2 point to device 100 is If the clock delay time is τ8,
The clock at point A2 arrives at device 142 with a delay of τ5, and the clock at point B2 arrives at device 142 with a delay of τ5 + τ6 + τ7. A2 point clock delay time and B
If the clock having the intermediate delay time between the two point clocks is the clock at the point C2, the delay time of the clock at the point C2 is 1/2 (τ5 + τ5 + τ6 + τ7), and τ6 and τ7 pass through the same route. Therefore, τ6 = τ7
Therefore, the delay time at the point C2 is τ5 + τ6.

The delay time at point C1 is τ1 + τ2, and C
The delay time of two points is τ5 + τ6, but τ1 + τ2 is the delay time of the clock from the device 100 to the farthest end,
It can be seen that τ5 + τ6 is also the clock delay time from the device 100 to the farthest end, and the delay time at the point C1 is the same as the delay time at the point C2. Device 1 on the same principle
Also in 43, if the clock of C3 point is created by the same method as the devices 141 and 142, the clock of C1 point, the clock of C2 point and the clock of C3 point are all clocks of the same phase regardless of the distance from the device 100. Can be obtained.

FIG. 3 is a block diagram showing an embodiment of a clock timing correction device used in the clock supply system of the present invention. The clock at the point A1 is connected to the input of the buffer 201 and the input 0 of the selector 208. The output of the buffer 201 is connected to the input of the buffer 202 and the selector 2
It is connected to the input 1 of 08. Similarly, the buffer 20
2 to the buffer 207 are connected in cascade, and the outputs from the buffer 202 to the buffer 207 are connected to the input 2 to the input 7 of the selector 208, respectively.

The output of the selector 208 is connected to the input of the buffer 209 at the same time as the clock at the point C1, and is further connected to 0 of the selector 216. Buffer 2
The output of 09 is connected to the input of the buffer 210 and the input 1 of the selector 216. Similarly, the buffers 210 to 215 are connected in cascade, and the outputs from the buffers 210 to 215 are input 2 to input 7 of the selector 216, respectively.
It is connected to the.

The output of the selector 216 is connected to the first input of the EXOR gate 217, and is connected to the EXOR gate 217.
The clock at the point B1 is connected to the second input of. The output of EXOR gate 217 is connected to the input of buffer 218 and the second input of AND gate 219, the output of buffer 218 is connected to the first input of AND gate 219, and the output of AND gate 219 is D Type flip-flop 220 connected to the data input.

The clock at point B1 is the EXOR gate 21.
7 second input and the inverter gate 221 input;
It is connected to the first input of AND gate 222. The output of the inverter gate 221 is connected to the clock input of the D-type flip-flop 220, the output Q of the D-type flip-flop 220 is connected to the second input of the AND gate 222, and the output of the AND gate 222 is the counter 2
23 clock inputs. Counter 223
Is a 3-bit counter, and outputs Q1, Q2, Q3
Are connected to the selector inputs S1, S2, S3 of the selector 208 and the selector inputs S1, S2, S3 of the selector 216, respectively.

Next, the operation of the circuit will be described with reference to FIGS. FIG. 4 shows the signal waveform of each part of FIG. The clock waveform at A1 point is A, the clock waveform at B1 point is B, the clock waveform at C1 point is C, and the selector 2
16 is D, the output waveform of the EXOR gate 217 is E, the output waveform of the buffer gate 218 is F, the output waveform of the AND gate 219 is G, and the D-type flip-flop 22.
0 output waveform is H, AND gate 222 output waveform is I,
The output value of the counter 223 is represented by J.

Buffer gates 201-207, 209-
215 and 219 use TLS LS type of the same type, and their gate delay time is about 10 nS, which is used as a delay element here. Buffer gate 2
The circuit combining 01-207 and selector 208 is
This is a variable delay circuit that can change the delay time from 0 nS to 80 nS in units of 10 nS by selecting inputs S1, S2 and S3 of the selector 208. Buffer gate 209-
The combination of 215 and selector 216 is also a variable delay circuit. Since the same signal is connected to the select inputs S1, S2, S3 of these two variable delay circuits, the delay time always has the same value.

When the circuit shown in FIG. 3 is powered on, a power reset is input to the reset input R of the counter 223, the counter 223 is reset, the D flip-flop is set, and the timing before t1 in FIG. As indicated by, the output value J of the counter 223 becomes "000".
Since the delay time value of the two variable delay circuits is 0 nS at the timing before t1, the waveform A and the waveform D have the same timing, and therefore the waveform of the exclusive OR of the waveform D and the waveform B in the EXOR gate 217 is obtained. At E, a positive pulse having a phase difference between the waveform D and the waveform B, that is, a phase difference between the waveform A and the waveform B appears. In this example, since the phase difference between the waveform A and the waveform B is 60 nS, the pulse width of the waveform E is 60 nS.

The combinational circuit of the inverter gate 218 and the AND gate 219 takes the logical product of the positive pulse of the EXOR gate 217 and the positive pulse delayed by 10 nS to obtain 10 nS or less appearing at the output of the EXOR gate 217. It is for removing the noise of. Since the waveform E is 60 nS, the inverter gate 2
08 and the AND gate 219, a positive pulse appears in the waveform G, and a signal obtained by inverting the waveform B by the inverter 221 drives the clock of the D-type flip-flop 220, that is, the D-type flip-flop at the falling edge of the waveform B. Since the waveform E of the data input of the D-type flip-flop 220 immediately before this timing is triggered by 220, the D-type flip-flop 220 is continuously set, and the waveform H of the output Q remains "1". .

The clock input to the counter 223 has a waveform B
In AND gate 222 with waveform H of "1", "0"
Since the clock is input to the counter 223 at the timing of t1, the counter 223 counts up and the output value J becomes "001". Since the output value J of the counter 223 has become “001”, the delay amounts of the two variable delay circuits are 10 nS each.
The waveform D becomes a delay of 20 nS with respect to the waveform A, the phase difference between the waveform B and the waveform D becomes 40 nS, the pulse width of the waveform E at the timing of t2 becomes 40 nS, and the combination circuit of the inverter gate and the AND gate becomes Since the D-type flip-flop is continuously set and the waveform H remains “1”, the counter 223 is counted up at the timing of t3 and the counter 223
The output value J of is "010".

Since the output value J of the counter 223 becomes "010", the delay amount of each of the two variable delay circuits becomes 20 nS, and the phase difference between the waveform D and the waveform B at t4 becomes 20 nS. Since E becomes a pulse of 20 nS and can pass through the inverter gate 218 and the AND gate 219, the D-type flip-flop 220 is continuously set and the waveform H remains “1”, so the counter 223 is counted up at the timing of t5, The output value J of the counter 223 becomes "011".

Since the output value J of the counter 223 becomes "011", the delay amount of each of the two variable delay circuits becomes 30 nS, and the phase difference between the waveform D and the waveform B is almost 0 n.
S, the waveform E is regarded as noise of 10 nS or less,
It cannot pass through the inverter gate 218 and the AND gate 219, the waveform G remains "0", the D flip-flop is cleared at the timing of t6, and the waveform H becomes "0".
become. Since the waveform H has become “0”, the clock does not appear in the waveform I, so that the counter 223 does not count up and the values of the delay amounts of the two variable delay circuits are fixed. Since the waveform C at this time has an intermediate delay amount between the waveforms A and D, that is, an intermediate phase difference between the phase difference between the clock at the A1 point and the clock at the B1 point, the waveform C can be used as the internal clock. .

The two variable delay circuits shown in FIG.
Although the delay of the buffer gate is used, the shift register can be used when the frequencies of the clock at the A1 point and the clock at the B1 point are low.

[0025]

As described above, according to the present invention, in a device supplied with a clock, a clock having an intermediate phase of the phase difference between the clocks of the clock supply line and the folded clock supply line is generated. Since the clock is the clock inside the device, the phase of the internal clock of the device to which the clock is supplied can be matched regardless of the distance between the clock supply source device and the plurality of devices to which the clock is supplied.

Further, since the circuits for generating the internal clocks are distributed and installed in a plurality of devices, the reliability of the system is improved.

Further, only a folded clock supply line is added to the wiring between the devices, and moreover, the clock supply line and the folded clock supply line connect a plurality of devices in a cascade. The clock phases can be adjusted.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a clock supply system of the present invention.

FIG. 2 is a diagram illustrating the principle of clock phase matching.

FIG. 3 is a block diagram showing an embodiment of a clock timing correction device.

FIG. 4 is a timing chart of signals of various parts in FIG.

[Explanation of symbols]

100 Clock supplying device 121 Clock supplying line 122 Folding clock supplying line 141, 142, 143 Clock receiving device 201-207, 209-215, 218 Buffer gate 208,216 Selector 217 EXOR gate 219, 222 AND gate 220 D-type flip-flop 221 Inverter gate 223 Counter

Claims (5)

[Claims] 1. A clock supply source device that supplies a clock, a plurality of devices that receive a clock from the clock supply source device, and a clock supply line that connects the plurality of devices from the clock supply source device to a cascade. And a folded clock supply line that folds the clock supply line from the end device and connects a plurality of devices in a reverse direction in a cascade. 2. The clock according to claim 1, wherein the device receiving the clock uses an intermediate phase of the phase difference between the clocks of the clock supply line and the folded clock supply line as the internal clock of the device. Supply system. 3. A first device for receiving the supply of the clock comprises a plurality of buffer gates connected in cascade and a selector, receives the clock from the clock supply line, and outputs the internal clock of the device from the selector. Variable delay circuit, a plurality of buffer gates and a selector connected in cascade, and a second variable delay circuit which is supplied with a clock from the selector of the first variable delay circuit; An EXOR gate connected to the output of the selector of the second variable delay circuit and having a second input connected to the folding clock supply line; a buffer having an input connected to the output of the EXOR gate; and a first input A first AN connected to the output of the buffer and having a second input connected to the output of the EXOR gate
A D-gate, an inverter gate whose input is connected to the folding clock supply line, a D-type flip-flop whose data input is connected to the output of the first AND gate, and whose clock input is connected to the output of the inverter gate. A first input connected to the folded clock supply line, a second input
A second AND gate whose input is connected to the output of the D-type flip-flop, and a reset input, and the clock input is the second AND gate.
A timing correction device for a clock having a counter connected to the output of the gate, the output of which is connected to the selector input of the selector of the first variable delay circuit and the selector input of the selector of the second variable delay circuit The clock supply system according to claim 1, wherein: 4. The clock supply system according to claim 3, wherein the buffer gate of the second variable delay circuit is a shift register. 5. A system for supplying a clock from a clock supply source device to a plurality of devices, wherein clock supply lines are connected in cascade from the clock supply source device to the plurality of devices, and the clock supply line is folded back from the farthest end device. By connecting the folded clock supply line in a cascade to a plurality of devices in the reverse direction, the intermediate phase of the phase difference between the clocks of the clock supply line and the folded clock supply line is used as the clock inside the device. Timing correction device.