JPH0512223A - Clock system for parallel computer - Google Patents

Abstract

PURPOSE:To supply the clock of the same phase to respective element processors so that the respective element processors are synchronously operated on a parallel computer having multiple element processors. CONSTITUTION:The respective element processors 3-5 connected in serial are composed by providing phase difference detection parts 6 which fetch the clock generated by a main oscillator 1 from both transmission lines branched with a folded point as a boundary and which obtain the middle point of the phase differences of the clocks fetched from both transmission lines, and clock oscillation parts 7 generating the clock based on the obtained middle point.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel computer having a large number of element processors, and to a structure for supplying clocks of the same phase to each element processor.

A parallel computer is a computer that operates several to several tens of thousands of element processors (hereinafter simply referred to as "processors") in parallel to perform high-speed processing. In order for a parallel computer to perform faster processing, it is necessary to speed up each processor and communication between processors. For this purpose, it is necessary to operate the processor with a high-speed clock and to have hardware that minimizes the data transfer time in the inter-processor communication.

Normally, a method is used in which the entire processor of a parallel computer is connected to a clock synchronization circuit and all the processors operate in synchronization. However, a clock that is efficient for many processors and has no phase difference is used. Distributing and supplying is important. Further, in order to increase the processing speed in applications such as signal processing, it is necessary to perform data input / output in synchronization with an external clock.

[0004]

2. Description of the Related Art FIGS. 5 to 7 are diagrams for explaining a conventional clock system. Conventionally, each processor 3
In order to supply the synchronous clocks to 5, 41 and 46, a tree-structured distribution and supply method with the main oscillators 31, 36 and 42 as the vertices was adopted.

According to the tree-structure distribution / supply method, the main clocks generated by the main oscillators 31, 36, and 42 are supplied to the m-distributor 3.
2, 38, 43 and n distributors 33, 34, 39, 40, 4
4, 45, etc. are branched by a clock branching circuit, and the generated synchronous clock is divided into the processors 35, 41,
Supply to 46.

The clock branch circuit is independent of the processors because it has a block structure according to the number of processors. Therefore, there is a drawback that the clock system hardware is inevitably large. However, this drawback has been dealt with flexibly by adjusting the size of the distributor and adjusting the number of stages of the distributor.

The conventional example shown in FIGS. 6 and 7 is used for signal processing and the like, and has means for synchronizing a synchronous clock with an external clock from the outside of the parallel computer. In the example shown in FIG. 6, a phase shift circuit 37 is provided to compensate the delay amount of the distribution system. Further, in the example shown in FIG. 7, a phase error detector 47 that detects the phase error between the synchronous clock and the external clock is provided, and the oscillation frequency of the main oscillator 42 is controlled so that the phase difference between the clock signals of both is eliminated. ing.

[0008]

In recent years, parallel computers have become larger in scale, and the number of processors has increased dramatically compared to the conventional one. As the number of processors increases, the number of branch stages in the clock distribution system must naturally be increased.
However, when the number of branch stages increases, the deviation of the delay amount of each distribution path increases, and the phase error of the synchronous clock increases. Therefore, the delay amount must be managed over all the distributors near the respective processors, but there is a problem that the number of distributors is too large to actually adjust.

In addition, in a system in which a processor is added in a timely manner, it is necessary to provide a new distribution path for supplying a synchronous clock to the processor each time the processor is added. And when a new distribution path is provided,
It is necessary to make adjustments so that the hardware amount of the clock branch circuit does not become too large. Therefore, there is a problem that the system cannot be easily expanded.

In view of the above-mentioned conventional problems, the present invention can supply accurate synchronous clocks of the same phase to a large number of processors and can easily cope with the expansion of processors. The purpose is to provide a system.

[0011]

According to the invention, the above mentioned objects are achieved by means of the patent claims.

That is, the invention of claim 1 comprises a plurality of element processors for performing parallel processing, a main oscillator for generating a main clock, and a transmission path for supplying the main clock to each element processor, A transmission path extending from a main oscillator in a clock generation system of a parallel computer that generates a synchronous clock used by each element processor from a main clock supplied through the transmission path so that a plurality of element processors operate in synchronization. Set the turning point at
A connection point with each element processor is provided on both transmission lines that are divided into two directions with the folding point as a boundary, and a phase difference of the main clock signal supplied from each connection point of the both transmission paths by any element processor. Is a clock system of a parallel computer having means for obtaining the midpoint and means for generating a synchronous clock based on the obtained midpoint.

According to a second aspect of the present invention, an external clock phase difference detecting section for detecting a phase difference between the main clock signal at the turning point and the external external clock signal is provided and the phase difference detected by the external clock phase difference detecting section. It is a clock system of a parallel computer provided with means for controlling the oscillation frequency of the main oscillator so that

[0014]

FIG. 1 is a diagram for explaining the principle of the present invention. In terms of ease of connection, division of clock system circuit blocks, and system expandability, it is best to distribute the clocks by series connection of processors. In FIG.
“Processor 0” 3, “Processor 1” 4, ..., “Processor N” 5 are connected to the transmission line 2 in series. However, in the case of serial connection, the phase difference of the clock signals is generated by the delay due to the transmission path length between the connection points.

Therefore, in order to correct this delay, as shown in FIG. 1, the transmission line 2 which passes through the processors 3 to 5 in series from the main oscillator 1 is folded back after passing through the last processor 5 and then reversed again. In this order, the processors 3 to 5 are serially passed. Hereinafter, the point where the transmission path is folded back is called a turning point, the transmission path from the main oscillator to the turning point is called a forward transmission path, and the transmission path before the turning point is called a backward transmission path.

In FIG. 1, it is assumed that the forward transmission line and the reverse transmission line have the same characteristics, and a connection point is provided at an equal distance from the turning point for both transmission lines, and the processor is provided here. 3-5 shall be connected. It is assumed that each of the processors 3 to 5 has a phase difference detector 6 and a clock oscillator, as indicated by "processor N" 5. The phase difference detection unit 6 detects the phase difference of the clock signals fetched from the transmission lines in the forward direction and the reverse direction, and obtains the midpoint of the phase difference. Further, the clock oscillating unit 7 generates a synchronous clock based on the midpoint obtained by the phase difference detecting unit 6.

Since the phase of the synchronous clock generated by the clock oscillator 7 corresponds to the midpoint of the phase difference between both connection points equidistant from the turning point, it is eventually the same as the phase of the turning point. According to the same principle, the phase of the synchronous clock generated by the clock oscillating units of the “processor 0” 3 and the “processor 1” 4 is also the same as the phase of the folding point. in this way,
The present invention provides accurate in-phase synchronous clocks based on signals having contrasting characteristics.

FIG. 2 is a diagram showing the delay amount of the main clock signal in FIG. The main clock signal generated by the main oscillator 1 is transmitted through the transmission line 2, passes through the connection point with the "processor 0" 3 and the connection point with the "processor 1" 4, and after passing the connection point with the "processor N" 5. , Reach the turning point.
The delay amount of the main clock signal at each position of the transmission line in the forward direction up to the turning point increases toward the turning point at a constant ratio as shown in the graph of FIG.

Further, the main clock signal passing through the turnaround point propagates through the transmission path in the opposite direction, passes through the connection point with "processor N" 5, and then passes through the connection point with "processor 1" 4 and then "processor 1". The connection point with 0 ″ 3 is reached. As shown in the graph of FIG. 2, the delay amount of the main clock signal at each position of the transmission path in the reverse direction from the turning point increases from the turning point toward the connection point with “processor 0” 3 at a constant ratio. To do.

As is apparent from FIG. 2, each processor 3
5 to 5 can take in main clock signals having contrasting phase characteristics from the respective connection points with the transmission line 2. Then, when the midpoint of the phase difference between the main clock signals taken in by the processors 3 to 5 is obtained, the phase of the main clock signal at the turning point can be derived, so that the processors 3 to 5 have the same phase as the turning point. A synchronous clock can be generated.

[0021]

FIG. 3 is a diagram showing an embodiment of the invention of claim 1. In FIG. 3, the transmission line 9 extending from the main oscillator 8
An example of the configuration is shown for one of the many processors connected in series with each other, but it is assumed that the other processors have the same configuration. Processor 10
To generate the synchronization clock, the phase difference detection unit 11
And a clock oscillator 12.

The phase difference detector 13 of the phase difference detector 11 is
The phase difference between the main clock signals fetched from the connection points in the forward direction and the reverse direction is detected and the phase difference is output. Multiplier 14
Halves the phase difference and outputs a phase difference signal.
Here, the distance from the turning point to both connection points is equal to L
Let n be the delay amount per unit length of the transmission line, and
The phase difference ΔΦ indicated by the phase difference signal is as follows: << Formula >> ΔΦ = τ (Ln + Ln) / 2 = τLn.

Phase difference detector 15 of clock oscillator 12
Detects the phase difference between the main clock signal fetched from the forward transmission line and the output clock signal of the clock oscillator 12, and outputs the phase difference. The adder 16 adds the above-described phase difference signal to the phase difference and outputs the addition result. The variable oscillator 17 generates an output clock of the clock oscillator 12 based on the addition result. The phase Φn of this output clock is expressed as follows: ## EQU1 ## Φn = Φr + ΔΦ, where Φr is the phase of the main clock fetched from the forward transmission path.

On the other hand, assuming that the phase of the main clock signal at the turning point is Φ, the following equation is obtained: << Equation >> Φr = Φ-τLn. In Φr of << expression a >>, add the right side of << expression c >> to << expression a >>
Substituting the right-hand side of << equation A >> into ΔΦ of {equation A >> Φn = (Φ + τLn) − (τLn) = Φ.

Therefore, the output clock of the clock oscillating unit 12 has the same phase as the main clock at the turning point, and if this is used as the synchronous clock, all the processors can be operated with the accurate synchronous clock of the same phase. The clock oscillator 12 uses a PLL (Phas
Although an e-locked loop) is configured, in this embodiment, it is assumed that an appropriate frequency divider 18 is placed in the feedback system. Therefore, an output clock having a constant frequency relationship with the main oscillator 8 can be obtained.

FIG. 4 is a diagram showing an embodiment of the invention of claim 2. The example shown in FIG. 4 is obtained by adding a means for synchronizing a synchronous clock to an external clock to the example shown in FIG. In the example shown in FIG. 3, the synchronous clock generated by each processor has the same phase as the main clock at the folding point.

Therefore, in the example shown in FIG. 4, an error between the phase of the main clock at the turning point and the phase of the external clock is detected, and the oscillation frequency of the main oscillator 19 is controlled so as to eliminate the error. A phase error detector 30 that outputs a control signal is provided.

In FIG. 4, the main oscillator 19 generates a main clock while changing the oscillation frequency according to the fed back control signal, and supplies it to the transmission line 20. Each processor is the processor 1 shown in FIG.
The configuration is the same as that of 0, and in FIG. 4, one of the many processors is illustrated.

That is, the processor 21 has a phase difference detector 22 and a clock oscillator 23. The phase difference detector 22 is composed of a phase difference detector 24 and a multiplier 25, while the clock oscillator 23 is composed of a PLL and is composed of a phase difference detector 26, an adder 27, a variable oscillator 28 and a frequency divider 29. And.

[0030]

As described above, according to the present invention,
The phase of the synchronization clock used by each processor of the parallel computer can be synchronized regardless of the number of units. It can also be synchronized with an external clock. Since each processor has a circuit for generating a clock therein, a circuit block for clock distribution supply independent of the processor is unnecessary. Therefore, the configuration of the circuit block can be simplified. Further, since all the processors have the same configuration, the cost can be reduced due to the effect of mass production. And, it is possible to easily cope with the expansion of the number of processors.

As described above, according to the present invention, since the hardware of the parallel computer can be of a synchronous type, there is a great advantage that the cost performance can be improved and various processing can be realized at higher speed in the parallel computer. is there.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a diagram showing a delay amount of a main clock signal.

FIG. 3 is a diagram showing an embodiment of the invention of claim 1;

FIG. 4 is a diagram showing an embodiment of the invention of claim 2;

FIG. 5 is a diagram illustrating a conventional clock system.

FIG. 6 is a diagram illustrating a conventional clock system.

FIG. 7 is a diagram illustrating a conventional clock system.

[Explanation of symbols]

1,8,19,31,36,42 Main oscillator 2,9,20 Transmission line 3,4,5,10,21,35,41,46 Processor 6,11,22 Phase difference detection part 7,12,23 Clock oscillator 13, 15, 24, 26 Phase difference detector 14, 25 Multiplier 16, 27 Adder 17, 28 Variable oscillator 18, 29 Divider 30, 47 Phase error detector 32, 38, 43 m Distributor 33, 34, 39, 40, 44, 45 n distributor 37 phase shift circuit

Claims (2)

[Claims] 1. A plurality of element processors for performing parallel processing, a main oscillator for generating a main clock, and a transmission line for supplying the main clock to each element processor, wherein the plurality of element processors are synchronized with each other. In the clock generation system of the parallel computer that generates the synchronous clock used by each element processor from the main clock supplied through the transmission line, the folding point is defined in the transmission line extending from the main oscillator, A connection point with each element processor is provided on both transmission lines that are divided into two directions with the folding point as a boundary, and the phase difference of the main clock signal that is supplied from each connection point on the transmission path of any element processor A clock for a parallel computer, comprising: a means for obtaining a midpoint and a means for generating a synchronous clock based on the obtained midpoint. . 2. An external clock phase difference detection unit for detecting a phase difference between a main clock signal at a turning point and an external clock signal from the outside is provided, and a phase difference detected by the external clock phase difference detection unit is eliminated. A clock system for a parallel computer comprising means for controlling an oscillation frequency of a main oscillator.