JP4226199B2 - Phase synthesis circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase synthesis circuit used for, for example, synthesizing two received signals received by two antennas.
[0002]
[Prior art]
Conventionally, there is a phase synthesis circuit as described above, for example, as shown in FIG. This phase synthesizing circuit has input terminals 2 and 4. A reception signal received by a first antenna (not shown) is input to the input terminal 2, and a second antenna (not shown) is input to the input terminal 4. The received signal is input. The first and second antennas are arranged at a predetermined interval so as to receive radio waves in the same frequency band transmitted from the same transmission source. The phase of the received signal input to the input terminal 2 is changed by the variable phase shifter 6 and supplied to the combiner 8. The synthesizer 8 is also supplied with the reception signal input to the second input terminal 4. The output signal of the synthesizer 8 is supplied to the output terminal 12 via the one branching device 10. The output signal of the synthesizer 8 branched by the one branching device 10 is detected by a detector 14, and the detected output is converted into a digital detection signal by an A / D converter 16, and this digital detection signal is, for example, a CPU. Is input to the digital arithmetic circuit 18 constituted by The arithmetic circuit 18 uses the variable phase shifter 6 necessary for making the reception signal supplied to the first input terminal 2 in phase with the reception signal supplied to the second input terminal 4 based on the digital detection signal. The phase shift amount is calculated, and the control voltage required to obtain this phase shift amount is calculated. This control voltage is converted into an analog signal by the D / A converter 20 and supplied to the control unit 22. The control unit 22 inputs a phase control signal to the variable phase shifter 6 so as to change the phase of the variable phase shifter 6 based on the control voltage. As a result, an output signal is generated at the output terminal 12 by in-phase synthesis of the received signals input to the first and second input terminals 2 and 4.
[0003]
[Problems to be solved by the invention]
In such a phase synthesis circuit, since the digital arithmetic circuit 18 is used, an A / D converter 16 is required to input data into the digital arithmetic circuit 18, and a control that is an arithmetic result in the digital arithmetic circuit 18. The D / A converter 20 is necessary to supply the voltage to the control unit 22 that is an analog circuit. Therefore, the phase synthesis circuit becomes large and the cost is high. Furthermore, in order to operate the digital arithmetic circuit 18, a high frequency clock signal is necessary, and if this has a specific relationship with the received signal supplied to the input terminals 2, 4, there is a possibility of disturbing the received signal. There is.
[0004]
An object of the present invention is to provide a small and low-cost phase synthesis circuit without using a digital arithmetic circuit or the like.
[0005]
[Means for Solving the Problems]
The phase synthesis circuit according to the present invention has a first input terminal to which a first signal is input and a second input terminal to which a second signal is input. A first signal from the first input terminal is input to the variable phase means. The variable phase means changes and outputs the phase of the first signal based on the supplied phase control signal. The phase inversion means inverts the phase of the second signal from the second input terminal. The output signal of the phase inverting means and the output signal of the variable phase means are synthesized by the first synthesis means and output. Based on the output signal of the first combining means, the control means changes the phase amount of the variable phase means. That is, the control means outputs the phase control signal so as to change the amount of phase change in the variable phase means while the output signal of the first synthesizing means is larger than the predetermined first value. The phase control signal when the output signal of the combining means becomes equal to or less than the first value is continuously supplied to the variable phase means. The output signal of the variable phase means and the second signal from the second input terminal are combined by the second combining means and output from the output terminal. The phase control signal generated by the control means is preferably changed in phase by at least 0 to 2π in the phase variable means. The first and second signals can be obtained from, for example, two antennas arranged at a predetermined interval so as to receive radio waves in the same frequency band transmitted from the same transmission source. The first value is, for example, a value that allows the first signal whose phase has been changed and the second signal to be considered to be in phase, and can be a value that allows for a margin in advance with respect to zero. Note that level adjusting means may be provided so that the levels of the first and second signals are uniform.
[0006]
In the phase synthesizing circuit configured as described above, the first synthesizing unit generates an output obtained by synthesizing the first signal whose phase is changed by the variable phase unit and the second signal whose phase is inverted. ing. The amount of phase shift in the variable phase means is changed by the control means, and the first signal whose phase is changed and the second signal are changed while the phase amount is changed. There are times when they become in-phase. At this time, the output signal of the first combining means is a value close to 0 and is smaller than the first value. At this time, the control unit stops changing the phase amount in the phase varying unit and maintains the phase at that time. Accordingly, an in-phase synthesized output signal is generated at the output terminal. In this phase synthesizing circuit, the second signal whose phase is inverted by the phase inverting means and the first signal whose phase is changed are synthesized by the first synthesizing means. The output becomes zero. Therefore, the control means does not need to perform complicated calculations, and only needs to determine whether the output signal of the first combining means is larger or smaller than the first value, and needs to perform complicated digital calculations. In addition, an A / D converter and a D / A converter are not necessary, and the size can be reduced at a low cost. In addition, since a digital arithmetic circuit is unnecessary, a high frequency clock is naturally unnecessary, and the first and second signals are not disturbed. Note that after the phase control signal to the variable phase means is fixed, the phase of the first signal supplied to the first input terminal changes, and the output signal of the first synthesizing means is less than the first value. When it becomes larger, the phase control signal starts to change again and is fixed when the output signal of the first combining means becomes smaller than the first value.
[0007]
The control means outputs the phase control signal so as to change the amount of phase change in the variable phase means even while the output signal of the second synthesizing means is smaller than a predetermined second value. it can. In the phase synthesis circuit described above, the output signal of the first synthesis means becomes zero even when the first and second signals are not supplied to the first and second input terminals. The supplied phase control signal is fixed. Of course, when the first and second signals are supplied to the first and second input terminals and the output is generated in the first combining means, the control means changes the phase control signal to the phase variable means, Some time delay occurs. Therefore, even when the output signal of the first combining means is smaller than the first value, the phase control signal is not fixed when the output signal of the second combining means is smaller than the second value. The first signal is immediately in phase with the second signal.
[0008]
The phase control circuit according to the present invention has a plurality of input terminals to which a signal whose phase is to be adjusted is input, and a reference signal input terminal to which a reference signal is input.
Signals are input from a plurality of input terminals to each of the plurality of variable phase means, and the plurality of variable phase means change the phases of these input signals based on the supplied phase control signals and output the signals. The phase inversion means inverts the phase of the reference signal from the reference signal input terminal. The output signal of the phase inverting means and the output signals of the variable phase means are combined by a plurality of first combining means and output. While the output signal of the corresponding first synthesizing unit is larger than the predetermined first value, the plurality of control units change the corresponding variable phase unit so as to change the phase change amount in the corresponding variable phase unit. The plurality of control means to the variable phase means corresponding to the phase control signal when the output signal of the corresponding first combining means falls below the first value. Will supply. The second combining means combines the output signal of each variable phase means and the reference signal from the reference signal input terminal. The output signal of the second combining means is supplied to the output terminal.
[0009]
In the phase synthesizing circuit configured as described above, the signals supplied to the input terminals are all in phase with the reference signal, the phase is adjusted by each variable phase means, and then the second synthesizing means and the reference signal. Synthesized. Therefore, in-phase synthesis can be performed even with three or more signals.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
The phase synthesis circuit according to the first embodiment of the present invention has a first input terminal 30 and a second input terminal 32 as shown in FIG. A reception signal of the first antenna 34 is input to the first input terminal 30 as a first signal. A reception signal of the second antenna 36 is input to the second input terminal 32 as a second signal. The first and second antennas 34 and 36 are for receiving radio waves in the same frequency band transmitted from the same transmission source, and constitute a phased array antenna, for example, together with this phase synthesis circuit.
[0011]
The received signal from the first input terminal 30 is supplied to variable phase means, for example, a variable phase shifter 38. The variable phase shifter 38 changes the phase of the received signal input based on the phase control signal supplied from the control unit 40 and outputs the received signal. The amount of phase shift in the variable phase shifter 38 changes based on the value of the phase control signal.
[0012]
The received signal from the second input terminal 32 is input to the one branching device 44 through level adjusting means, for example, a variable attenuator 42. The branch signal from the one branching unit 44 is inverted in phase by 180 degrees by a phase inverting unit, for example, a fixed phaser 46, and is input to a first combining unit, for example, a synthesizer 48. A branch signal obtained by branching the output signal of the variable phase shifter 38 by the one branching device 50 is also input to the combiner 48. Therefore, the combiner 48 combines the signal obtained by inverting the phase of the received signal at the second input terminal 32 and the signal obtained by shifting the phase of the received signal at the first input terminal 30 by the variable phase shifter 38. ,Output. The output signal of the synthesizer 48 is input to the control unit 40.
[0013]
Further, the output signal of the one branching device 44 and the output signal of the one branching device 50 are combined by the second combining means, for example, the combiner 52. The output signal of the synthesizer 52 is a signal obtained by adjusting the phase of the received signal at the first input terminal 30 by the variable phase shifter 38 and the received signal at the second input terminal 32. The output signal of the synthesizer 52 is output from the output terminal of the one branching unit 54 to the output terminal 56 and is input from the branching terminal of the one branching unit 54 to the control unit 40.
[0014]
As shown in FIG. 2, the control unit 40 includes detectors 58 and 60. The detector 58 outputs the output signal of the synthesizer 48 (the signal obtained by inverting the phase of the received signal at the second input terminal 32 and the signal obtained by shifting the phase of the received signal at the first input terminal 30 by the variable phase shifter 38). And a detection signal representing the level of the output signal of the synthesizer 48 is generated. Similarly, the detector 60 combines the branch signal of the branching device 54 (the signal obtained by shifting the phase of the reception signal of the first input terminal 30 by the variable phase shifter 38 and the reception signal of the second input terminal 32). And a detection signal representing the level of this branch signal is generated. These two detection signals are supplied to the determination circuit 62.
[0015]
As shown in FIG. 3, the determination circuit 62 supplies a change instruction signal to the control signal generation circuit 64 while the detection signal from the detector 58 is larger than a predetermined first value. Further, the determination circuit 62 supplies a change instruction signal to the control generation circuit 64 while the detection signal from the detector 60 is smaller than a predetermined second value. The determination circuit 62 generates a fixed instruction signal when the detection signal from the detector 58 is smaller than the first value and the detection signal from the detector 60 is larger than the second value.
[0016]
The control signal generation circuit 64 supplies a phase control signal to the variable phase shifter 38. When the change instruction signal is supplied from the determination circuit 62, for example, the control signal generation circuit 64 generates a phase control signal as shown in FIG. That is, a sine waveform phase control voltage Vφ having a minimum value of 0, a maximum value of Vc, and an intermediate value of Vc / 2 is generated. That is, an AC voltage biased at Vc / 2 is generated. This AC voltage is generated based on an AC voltage generator such as a commercial AC power source supplied to the control unit 40 from the outside.
[0017]
For example, as shown in FIG. 5, the variable phase shifter 38 to which the phase control voltage Vφ is supplied has a phase shift amount of 0 when the phase control voltage Vφ is 0 and a phase shift amount of 0 when the phase control voltage Vφ is Vc. When the phase control voltage Vφ is between 0 and Vc, the amount of phase shift is between 0 and 2π. Further, when the fixed instruction signal is supplied, the control signal generation circuit 64 maintains the phase control voltage Vφ generated immediately before it as shown in FIG. 6 and continues thereafter.
[0018]
For example, assume that in-phase received signals are supplied to the first and second input terminals 30 and 32 as shown in (a) and (b) in FIG. If the amount of phase shift in the variable phase shifter 38 is 0, the received signals at the input terminals 30 and 32 are in phase, so the output signal of the synthesizer 52, that is, the output signal of the output terminal 56 is shown in FIG. ), The amplitude of the received signal at the input terminals 30 and 32 is twice that of the received signal. On the other hand, the phase of the received signal at the input terminal 32 is inverted by the fixed phase shifter 46 and is in reverse phase to the received signal at the input terminal 30 as shown in (c) of FIG. The output signal 48 becomes zero as shown by (e) in FIG. That is, the output signal of the synthesizer 48 is a value smaller than the first value.
[0019]
On the other hand, it is assumed that the received signals inputted to the first and second input terminals 30 and 32 have a phase difference, as shown in (a) and (b) in FIG. The signals (a) and (c) in FIG. 7B are supplied to the synthesizer 48, and the signals shown in (a) and (b) in FIG. 7B are supplied to the synthesizer 52. . As a result, the output signal of the synthesizer 52 has a smaller amplitude than the case where both signals are in phase, as shown in (d) of FIG. On the other hand, the output signal of the synthesizer 48 has a value larger than zero, as indicated by (e) in FIG.
[0020]
At this time, since the first value is set so that the detection signal of the detector 58 is larger than the first value, the determination circuit 62 supplies the change instruction signal to the control signal generation circuit 64. . In response to this, the control signal generation circuit 64 supplies the variable phase shifter 38 with the variable phase control voltage Vφ whose value changes as a variable phase signal. As a result, the amount of phase shift in the variable phase shifter 38 repeatedly changes between 0 and 2π, and the output signal of the variable phase shifter 38 and the output signal of the fixed phase shifter 46 may be in phase. At this time, the detection signal of the detector 58 becomes smaller than the first value, and the determination circuit 62 supplies the fixed instruction signal to the control signal generation circuit 64. The control signal generation circuit 64 supplies the variable phase shifter 38 with the variable phase control voltage generated at that time. Therefore, the output signal of the variable phase shifter 38 and the reception signal of the second input terminal 32 are in phase, and the in-phase signal is supplied to the combiner 52, in-phase combining is performed, and the signal is output from the output terminal 56. .
[0021]
In this way, a signal that is supplied to the first input terminal 30 and whose phase is sequentially changed by the variable phase shifter 38 and a signal that is supplied to the second input terminal 32 and whose phase is inverted are provided. Since the determination circuit 62 determines whether the output signal of the variable phase shifter 38 and the reception signal of the second input terminal 32 are in phase with each other, the determination circuit 62 includes the detector. A comparison circuit that determines whether or not the 58 detection signals are smaller than the first value may be provided, and the circuit configuration is simplified. Further, since a CPU or the like as will be described later is not used, it is not necessary to use a high-frequency clock signal, and the high-frequency clock signal may adversely affect the received signals input to the first and second input terminals 30 and 32. Absent.
[0022]
For example, when the signals supplied to the first and second input terminals 30 and 32 are synthesized as they are and an attempt is made to determine whether the two signals are in phase from the detected signals, each time the amount of phase shift changes. Then, the maximum value of the detection signal at that time must be obtained, and the phase control signal when the value becomes the largest among the maximum values must be determined as a signal necessary for making it in phase. For this reason, an arithmetic circuit, an A / D converter, and a D / A converter using a CPU or the like are required, and the circuit configuration becomes complicated.
[0023]
If the determination circuit 62 is configured to generate a fixed instruction signal when the detection signal of the detector 58 is smaller than the first value, the received signal is present at the first and second input terminals 30 and 32. Even if not supplied at all, a fixed instruction signal is generated, and the phase shift amount in the variable phase shifter 38 remains fixed. This state occurs, for example, when the faced array antenna is started. However, even in such a state, when the received signal is supplied to the first and second input terminals 30 and 32 and the output signal of the synthesizer 48 becomes larger than the first value, the phase shift amount of the variable phase shifter 38 is increased. However, there is a time delay by the time until the output signal of the synthesizer 48 becomes larger than the first value.
[0024]
Therefore, even if the detection signal of the detector 58 is smaller than the first value, when the detection signal of the detector 60 is smaller than the second value, the determination circuit 62 sends the variable instruction signal to the control signal generation circuit 64. To supply. In other words, the determination circuit 62 outputs the fixed instruction signal to the control signal generation circuit when the detection signal of the detector 58 is smaller than the first value and the detection signal of the detector 60 is larger than the second value. 64. Further, since it is only necessary to determine whether or not the detection signal of the detector 60 is larger than the second value, the determination circuit 62 need only include a comparator for this determination.
[0025]
The first value is a value that allows for a predetermined margin in the detection signal of the detector 58 when the reception signals of the first and second input terminals 30 and 32 are in phase. The second value is a value that allows for a predetermined margin in the detection signal of the detector 60 when the reception signal is not supplied to the first and second input terminals 30 and 32.
[0026]
In the first embodiment, the received signals supplied to the two input terminals 30 and 32 are combined in phase, but for example, the received signals supplied to three or more input terminals can be combined in phase. For example, FIG. 8 shows a second embodiment in which the received signals supplied to the three input terminals 30, 30 a, and 32 are combined in phase, and the received signal supplied to the input terminal 30 is connected to the input terminal 32. The synthesized signal is synthesized in phase with the received signal, and the received signal at the input terminal 30a is also synthesized in phase with the received signal at the input terminal 32. And supplied to the output terminal 56. That is, the signal supplied to the input terminal 32 becomes the reference signal, and the phase of the signal supplied to the input terminals 30 and 30a is in phase with the reference signal. Since the configuration for the in-phase synthesis of the received signals at the input terminals 30 and 32 is almost the same as that of the above-described embodiment, the same parts are denoted by the same reference numerals and description thereof is omitted. The received signal supplied to the input terminal 30a and the input terminal 32 is synthesized by dividing the output signal of the fixed phase shifter 46 into two by the two dividers 60, one of which is a first synthesizer, for example, a synthesizer. 48 and also supplied to a first combining means, for example, a combiner 48 a, the received signal at the input terminal 32 is divided into two by the two distributors 62, and one of the distribution outputs is routed through the one branching device 44. Except for being supplied to the combiner 52 and the other distributed output being supplied to the combiner 52a, it is almost the same as the above-described embodiment. The description is omitted.
[0027]
In the above two embodiments, the input terminal 32 is provided with the attenuator 42 as the level adjusting means, but may not be necessary in some cases. Alternatively, an amplifier can be used instead of the attenuator. When there are four or more antennas, a plurality of phase synthesis circuits of the first embodiment are provided, and the output of the phase synthesis circuit to which the antennas are respectively connected is synthesized by a tournament method using another phase synthesis circuit. Then, the gain can be further increased.
[0028]
【The invention's effect】
As described above, according to the present invention, a small and low-cost phase synthesis circuit can be obtained without using a complicated arithmetic circuit or the like.
[Brief description of the drawings]
FIG. 1 is a block diagram of a phase synthesis circuit according to a first embodiment of the present invention.
FIG. 2 is a detailed block diagram of a control unit used in the phase synthesis circuit of FIG. 1;
FIG. 3 is a diagram illustrating a signal supplied from the determination circuit of FIG. 2 to a control signal generation circuit;
4 is a diagram showing a phase control voltage generated by the control signal generation circuit of FIG. 2; FIG.
5 is a diagram showing the relationship between the phase control voltage of FIG. 4 and the amount of phase shift in the variable phase shifter.
6 is a diagram showing a change in phase control voltage generated by the control signal generation circuit of FIG. 2; FIG.
7 is a waveform diagram of each part in the phase control circuit of FIG. 1 when signals supplied to two input terminals are in phase and in different phases.
FIG. 8 is a block diagram of a phase synthesis circuit according to a second embodiment of this invention.
FIG. 9 is a block diagram of a conventional phase synthesis circuit.
[Explanation of symbols]
30 First input terminal (signal input terminal)
30a Signal input terminal 32 Second input terminal (reference signal input terminal)
38 38a Variable phase shifter (variable phase means)
40 Control unit (control means)
46 Fixed phase shifter (phase inversion means)
48 48a Synthesizer (first synthesis means)
52 Synthesizer (second synthesis means)
64 Synthesizer (second synthesis means)

Claims (3)

A first input terminal to which a first signal is input;
A second input terminal to which a second signal is input;
Variable phase means for inputting the first signal from the first input terminal and changing the phase of the first signal based on the supplied phase control signal;
Phase inverting means for inverting the phase of the second signal from the second input terminal;
A first synthesizing means for synthesizing and outputting the output signal of the phase inverting means and the output signal of the variable phase means;
While the output signal of the first combining means is larger than the predetermined first value, the phase control signal is output so as to change the phase change amount in the variable phase means, and the output signal of the first combining means Control means for continuously supplying a phase control signal when the value becomes equal to or less than a first value to the variable phase means;
Second combining means for combining the output signal of the variable phase means and the second signal from the second input terminal;
An output terminal to which an output signal of the second combining means is supplied;
A phase synthesis circuit provided. The phase synthesis circuit according to claim 1,
The control means controls the phase so that the amount of phase change in the variable phase means changes at least between 0 and 2π even while the output signal of the second synthesizing means is smaller than a predetermined second value. A phase synthesis circuit that outputs control signals. A plurality of input terminals to which a signal whose phase is to be adjusted is input;
A reference signal input terminal to which a reference signal is input;
A plurality of variable phase means for inputting a signal from each of a plurality of input terminals and changing and outputting the phase of these input signals based on the supplied phase control signal;
Phase inversion means for inverting the phase of the reference signal from the reference signal input terminal;
A plurality of first combining means for combining the output signals of the phase inverting means and the output signals of the variable phase means,
While the output signal of the corresponding first combining means is larger than the predetermined first value, the phase control signal is output to the corresponding variable phase means so as to change the phase change amount in the corresponding variable phase means. A plurality of control means for continuously supplying the corresponding phase control signal to the corresponding variable phase means when the output signal of the corresponding first combining means falls below the first value;
Second combining means for combining the output signal of each variable phase means and the reference signal from the reference signal input terminal;
An output terminal to which an output signal of the second combining means is supplied;
A phase synthesis circuit provided.

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