JP2004254200A - Polyhedral super diversity digital radio receiving apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make circuit constitution simple and easy when synchronously composing received signals of a plurality of antennas while cascade connecting a plurality of synchronous composing parts. <P>SOLUTION: A phase difference detecting circuit 22 of each synchronous composing part 2 detects a phase difference of signals inputted to a composer 21 and sends phase difference data Dp to an EPS control part 3. The EPS control part 3 selects the phase difference data Dp of the synchronous composing parts 2 in a fixed cycle, in order and in a time division manner and newly generates phase control data Dc so that a phase difference can be "0" with the phase control data Dc which are sent to the relevant synchronous composing part 2 the last time, as an initial value. The generated phase control data Dc are latched and sent to an EPS (infinite phase shifter) 23 of the relevant synchronous composing part 2. The EPS (infinite phase shifter) 23 of each synchronous composing part 2 performs phase control operation in accordance with the phase control data Dc. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a multi-plane space diversity digital radio receiving apparatus, and more particularly to a means for cascading a plurality of synchronous combining sections for synchronously combining two input signals to synchronously combine received signals of a plurality of antennas.
[0002]
[Prior art]
FIG. 4 is a block diagram showing an example of a conventional multi-plane space diversity type digital wireless receiver.
[0003]
Here, (n-1) synchronous synthesizing units 5-1, 5-2,..., 5- (n-1) for synchronizing and synthesizing the two input signals are connected in cascade to form an n-plane antenna 1 , 1-2,..., 1-n are sequentially and synchronously combined.
[0004]
First, the first synchronization synthesizing unit 5-1 synchronously synthesizes the reception signal S1 of the first antenna 1-1 and the reception signal S2 of the second antenna 1-2, and then the second synchronization synthesis unit 5-1. -2 synchronously combines the combined output signal of the first synchronous combining section 2-1 with the received signal S3 of the third antenna 1-3. In the same manner, by sequentially repeating the synchronizing in the same manner, the last synthesizing unit 5- (n-1) outputs a signal obtained by synthesizing all the reception signals S1, S2,..., Sn of the n-plane antenna.
[0005]
Further, each synchronous synthesizing unit 5 adjusts the phase of one of the input signals, a synthesizer 51 that synthesizes the two signals, a phase difference detection circuit 52 that detects the phase difference between the two signals input to the synthesizer 51. (Infinite phase shifter) 53 and an EPS control circuit 54 that controls the EPS (infinite phase shifter) 53 so that the phase difference detected by the phase difference detection circuit 52 becomes zero. . (For example, refer to Patent Document 1.)
[Patent Document 1]
JP-A-2-246528 (FIG. 3)
[0006]
[Problems to be solved by the invention]
However, in the above-described conventional example, in order to control the EPS (infinite phase shifter) of each synchronous synthesizing unit so as to converge to the in-phase point, the control speed of the synchronous synthesizing unit in the subsequent stage is higher than that of the synchronous synthesizing unit in the preceding stage. Need to be For this reason, it is necessary to operate the EPS control units of the respective synthesizing units at different clock frequencies, and even with the same circuit configuration, an EPS control circuit having a different operation speed and a clock generation circuit having a different frequency are required. Is increased.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to enable the EPS control circuits of a plurality of synchronous synthesizing units to operate at a single clock frequency, to share an EPS control circuit, an oscillation circuit for clock generation, and the like, and to increase space diversity. It is an object of the present invention to provide a multi-faceted space diversity type digital radio receiving apparatus capable of realizing the simplification and simplification of the circuit configuration by the method.
[0008]
[Means for Solving the Problems]
The first multi-plane space diversity type digital radio receiving apparatus according to the present invention is provided with a plurality of synchronous synthesizing means for adjusting and synthesizing by an EPS (infinite phase shifter) so that the phase difference between two signals to be synthesized becomes zero. In a multi-plane space diversity type digital radio receiving apparatus for connecting and synchronizing reception signals of a plurality of antennas, a plurality of the synthesizing units receive data indicating a phase difference between the two signals in a plurality of the synchronizing units. EPS control means for performing time division multiplexing control of the EPS (infinite phase shifter) of the means.
[0009]
More specifically, in a multi-plane space diversity type digital radio receiving apparatus that cascade-connects a plurality of synchronous combining sections for synchronously combining two input signals and synchronously combines received signals from a plurality of antennas, the plurality of synchronous combining sections are A combiner that combines two input signals, a phase difference detection circuit that detects a phase difference between the two signals input to the combiner and sends phase difference data to an EPS control unit, and a phase difference detection circuit that supplies the phase difference data to the EPS control unit. And an EPS (infinite phase shifter) that adjusts the phase of one of the input signals in accordance with the phase control data to be transmitted. The phase control data is generated based on the phase difference data, and time-division multiplexing control is performed on the EPSs (infinite phase shifters) of the plurality of synchronous synthesis units.
[0010]
The EPS control unit generates the phase control data by selecting the phase difference data sent from each of the plurality of synchronous synthesis units in a time-division order in a fixed cycle, and generates the phase control data. Are respectively latched and sent to the corresponding synthesizing unit.
[0011]
That is, a switch for selecting the phase difference data transmitted from each of the plurality of synchronous synthesizing units in a time-division manner, latching the phase control data and transmitting each, and a memory for temporarily storing the transmitted phase control data. A phase control data generation circuit for generating new phase control data based on the currently received phase difference data and the previous phase control data stored in the memory, a clock generation circuit for generating an operation clock signal, and the operation clock A switching control circuit for controlling the switching operation of the switch based on the signal.
[0012]
A second multi-faceted space diversity type digital radio receiving apparatus according to the present invention is a multi-faceted space diversity type digital radio receiver for synchronizing and synthesizing received signals of a plurality of antennas by cascade-connecting a plurality of synchronous synthesizing units for synchronizing two input signals. In the wireless receiving apparatus, a first synthesizing unit among the plurality of synchronizing units is a local oscillation circuit that generates a common local oscillation signal, and two mixers that convert each of the two received signals into an intermediate frequency signal. A synthesizer for synthesizing the two intermediate frequency signals output from the two mixers and sending the synthesized signal to a synchronous synthesizing unit at a subsequent stage, and detecting a phase difference between the two intermediate frequency signals input to the synthesizer to detect the phase difference. A phase difference detection circuit for transmitting phase difference data to the EPS control unit, and one of the two mixers according to the phase control data supplied from the EPS control unit And a EPS for adjusting the phase of said common local oscillation signal supplied (infinite phase shifter).
[0013]
In addition, a synchronous synthesizing section other than the first synthesizing synthesizing section synthesizes a mixer for converting a received signal into an intermediate frequency signal, an intermediate frequency signal output from the mixer, and an intermediate frequency signal from a preceding-stage synchronous synthesizing section. A synthesizer, a phase difference detection circuit that detects a phase difference between two intermediate frequency signals input to the synthesizer and sends phase difference data to an EPS control unit, and a phase control data supplied from the EPS control unit. And an EPS (infinite phase shifter) that adjusts the phase of the common local oscillation signal and supplies the adjusted local oscillation signal to the mixer. The EPS control unit is transmitted from each of the plurality of synchronous synthesis units. The phase control data is respectively generated based on the phase difference data, and time-division multiplexing control is performed on a plurality of EPSs (infinite phase shifters) of the synthesizing unit.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0015]
FIG. 1 is a block diagram showing an embodiment of the present invention, in which received signals S1, S2,..., Sn of antennas 1-1, 1-2,. , 2-2,..., 2- (n-1), and receives the phase difference data Dp from the phase difference detection circuit 22 of each of the synchronous synthesis sections 2 to perform phase adjustment. An EPS control unit 3 that generates control data Dc and controls the EPS (infinite phase shifter) 23 of each synchronous synthesizing unit in a time-division multiplex manner.
[0016]
Here, the first synchronization synthesizing unit 2-1 synchronously synthesizes the reception signal S1 of the first antenna 1-1 and the reception signal S2 of the second antenna 1-2, and then synthesizes the second synchronization synthesis unit. 2-2 synchronously combines the combined output signal of the first synchronous combining section 2-1 and the received signal S3 of the third antenna 1-3, and repeats synchronous combining in the same manner as described above, thereby obtaining the final synchronous combined. The section 2- (n-1) outputs a signal obtained by synthesizing all the received signals S1, S2,..., Sn of the n-plane antenna.
[0017]
Each synchronous synthesizing unit 2 synthesizes two input signals, and detects a phase difference between the two signals input to the synthesizer 21 and sends a phase difference data Dp to the EPS control unit 3. It has a circuit 22 and an EPS (infinite phase shifter) 23 that adjusts the phase of one input signal according to the phase control data Dc supplied from the EPS control unit 3. FIG. 2 is a block diagram illustrating an example of the EPS control unit 3.
[0018]
The EPS control unit 3 transmits the phase difference data Dp1, Dp2,..., Dp (n-1) respectively transmitted from the synchronous synthesis units 2-1, 2-2,..., 2- (n-1). , Dc (n-1) generated by the phase control data generating circuit 33, and a switch 31 for latching and transmitting the phase control data Dc1, Dc2,..., Dc (n-1). A memory 32 for temporarily storing Dc, a phase control data generating circuit 33 for generating new phase control data Dc based on the phase difference data Dp received this time and the phase control data Dp transmitted last time, and an operation clock signal Sc. It has a clock generation circuit 34 and a switching control circuit 35 that generates a switching control signal Ss for controlling the switching operation of the switch 31 based on the operation clock signal Sc.
[0019]
Here, the switching control signal Ss is generated based on control timing for time-division multiplexing control of each of the synthesizing units 2-1, 2-2,..., 2- (n-1), It is supplied to the generation circuit 33.
[0020]
The switch 31 converts the phase difference data Dp1, Dp2,..., Dp (n-1) sent from each of the synthesizing units 2-1 to 2-2,. .., Dc (n-1) generated by the phase control data generation circuit 33 are latched, respectively, in a time-division manner in a predetermined cycle in accordance with the switching control signal Ss. The latch output is always sent to the corresponding synthesizing unit.
[0021]
Next, the operation will be described.
[0022]
, 1-n on the n-plane are respectively arranged at positions that have no correlation with the spatial propagation characteristics, and synchronize the received signals S1, S2, ..., Sn with the synchronous synthesis unit 2-1. , 2-2,..., 2- (n-1).
[0023]
Here, the received signals S1 and S2 of the antennas 1-1 and 1-2 are synchronously combined in the synchronous synthesizing unit 2-1. The synthesized output signal of the synthesizing unit 2-1 is synchronously synthesized, and thereafter, the synchronizing synthesizing unit 2- (n-1) repeats the synchronizing synthesis sequentially. By combining the (n-2) combined output signal, all of the reception signals S1, S2,..., Sn of the n-plane antenna are combined.
[0024]
By the way, the phase difference detection circuit 22 of each of the synthesizing units 2-1, 2-2,..., 2- (n−1) detects the phase difference of the signal input to the synthesizer 21 and obtains the phase difference data Dp1. , Dp2, ..., Dp (n-1) to the EPS control unit 3, respectively.
[0025]
The phase control data generating circuit 33 of the EPS control unit 3 receives the phase difference data Dp received by the switch 31 in a time-division manner, and sends the phase difference data Dp to the corresponding synthesizing unit 2 within a predetermined control time allocated in a time-division manner. The phase control data Dc read out from the memory 32, and the phase control data Dc transmitted last time is used as an initial value, and the phase control data Dc is newly generated based on the received phase difference data Dp so that the phase difference becomes zero. . Then, the newly generated phase control data Dc is stored in the memory 32 and sent to the switch 31.
[0026]
By the way, the switch 31 receives the newly generated phase control data Dc, latches it, and sends it to the EPS (infinite phase shifter) 23 of the corresponding synthesizing unit 2, so that the next phase control data Dc is generated. Until the above, the latched phase control data Dc is continuously sent to the EPS (infinite phase shifter) 23 of the synchronous synthesizing unit 2.
[0027]
The EPS (infinite phase shifter) 23 of each synchronous synthesizing unit 2 performs a phase control operation by receiving the phase control data Dc latched by the switch 31 and transmitted.
[0028]
In this way, the EPS control unit 3 converts the phase difference data Dp1, Dp2,..., Dp (n-1) from each of the synchronizing synthesis units 2-1, 2-2,. .., Dc (n-1) are generated based on the phase difference data, and are latched by the switch 31 respectively. By transmitting the signals to the EPS (infinite phase shifter) 23 of the synchronous synthesizing unit 2, the control of each infinite phase shifter of the plurality of synchronous synthesizing units can be shared by one EPS control unit. Each infinite phase shifter can be converged to the in-phase point without changing the control speed of the phase shifter.
[0029]
FIG. 3 is a block diagram showing another embodiment of the present invention.
[0030]
Here, the difference from the configuration shown in FIG. 1 is that the reception signals S1, S2,..., Sn of the antennas 1-1, 1-2,. In that they are sequentially synthesized synchronously.
[0031]
The first synchronization synthesizing unit 4-1 converts a local oscillation circuit 41 that generates a common local oscillation signal So for converting a received signal into an intermediate frequency signal, and converts the received signals S1 and S2 into an intermediate frequency signal. For synthesizing the two intermediate frequency signals, detecting the phase difference between the two intermediate frequency signals input to the synthesizer 44, and transmitting the phase difference data Dp1 to the EPS control unit 3. And an EPS (infinite phase shifter) 46 for adjusting the phase of the local oscillation signal So supplied to one of the mixers 43 according to the phase control data Dc1 supplied from the EPS control unit 3. are doing. .., 4- (n-1) other than the first synthesizing unit 4-1 have the same configuration, and are supplied from the first synthesizing unit 4-1. A mixer 43 that receives a common local oscillation signal So and converts a received signal into an intermediate frequency signal, a combiner 44 that combines two intermediate frequency signals, and a phase difference between the two intermediate frequency signals input to the combiner 44 And the phase difference detection circuit 45 that sends the phase difference data Dp to the EPS control unit 3 and the phase of the local oscillation signal So supplied to the mixer 43 according to the phase control data Dc supplied from the EPS control unit 3. And an EPS (infinite phase shifter) 46 for adjustment. As shown in FIG. 2, the EPS control unit 3 selects the phase difference data Dp1, Dp2,..., Dp (n-1) respectively transmitted from the respective synthesizing units in a time-division manner, and performs phase control. .., Dc (n−1) generated by the data generation circuit 33, and a switch 31 for latching and transmitting the phase control data Dc, a memory 32 for temporarily storing the transmitted phase control data Dc, A phase control data generation circuit 33 for generating new phase control data Dc based on the received phase difference data Dp and the previously transmitted phase control data Dp, a clock generation circuit 34 for generating an operation clock signal Sc, and an operation clock signal Sc And a switching control circuit 35 that generates a switching control signal Ss for the switch 31 based on the
[0032]
With this configuration, each synchronous synthesizing unit can convert the received signal into an intermediate frequency signal by using the local oscillation signal So of the first synchronous synthesizing unit 4-1, and perform synchronous synthesizing. The EPS control unit 3 can control the infinite phase shifters of the plurality of synchronous synthesis units.
[0033]
【The invention's effect】
As described above, according to the present invention, one EPS control unit is provided in a receiving unit of a multi-plane space diversity type digital wireless receiving device that sequentially and synchronously combines received signals of a plurality of antennas by a plurality of synchronous combining units, The EPS control unit performs time-division reception while sequentially switching the phase difference data output from each of the plurality of synchronous synthesis units at a fixed period, and controls the phase difference to be 0 based on the received phase difference data. By generating the phase control data and transmitting it to the corresponding synthesizing unit, the infinite phase shifters of the plurality of synthesizing units can be time-division multiplexed and controlled by one EPS control unit. Can be simplified.
[0034]
In addition, even if the synchronous synthesizer is operated at a single frequency without changing the control speed of the infinite phase shifter, it is possible to converge the infinite phase shifter to the in-phase point, and the circuit configuration is based on multi-faceted space diversity. Simplification and simplification can be realized.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of the present invention.
FIG. 2 is a block diagram showing an example of an EPS control unit 3 shown in FIG.
FIG. 3 is a block diagram showing another embodiment of the present invention.
FIG. 4 is a block diagram showing a conventional example.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Antenna 2, 4 Synchronization synthesis part 3 EPS control part 21, 44 Synthesizer 22, 45 Phase difference detection circuit 23, 46 EPS (infinite phase shifter)
31 switch 32 memory 33 phase control data generation circuit 34 clock generation circuit 35 switching control circuit 41 local oscillation circuits 42 and 43 mixer Dc phase control data Dp phase difference data

Claims (6)

A multi-plane space diversity that cascade-connects a plurality of synchronous combining means that adjusts and combines by an EPS (infinite phase shifter) so that the phase difference between the two signals to be combined becomes zero, and synchronously combines received signals from a plurality of antennas. And a time-division multiplexing control of the EPS (infinite phase shifter) of the plurality of synchronous synthesizing means by receiving data indicating the phase difference between the two signals in the plurality of synchronous synthesizing means. A multi-plane space diversity type digital radio receiving apparatus comprising control means. In a multi-plane space diversity type digital radio receiving apparatus for synchronously combining received signals from a plurality of antennas by cascade-connecting a plurality of synchronous combining sections for synchronously combining two input signals, the plurality of synchronous combining sections include two input signals. , A phase difference detection circuit that detects a phase difference between two signals input to the combiner and sends phase difference data to the EPS control unit, and a phase control data supplied from the EPS control unit. And an EPS (infinite phase shifter) that adjusts the phase of one of the input signals in accordance with the phase difference data. A multi-plane space diversity, wherein phase control data are respectively generated and time-division multiplexing control is performed on a plurality of EPSs (infinite phase shifters) of the synchronous synthesizing units. Form digital radio receiver. The EPS control unit generates the phase control data by selecting the phase difference data transmitted from each of the plurality of synchronous synthesis units in a time-division order in a fixed cycle and generates the phase control data, respectively. 3. The multi-plane space diversity type digital radio receiving apparatus according to claim 2, further comprising means for latching and transmitting the signals to the respective synchronous synthesizing units. The EPS control unit selects the phase difference data transmitted from each of the plurality of synchronous synthesizing units in a time-division manner, latches the phase control data and transmits the data, and temporarily stores the phase control data to be transmitted. A memory for storing, a phase control data generation circuit for newly generating phase control data based on the currently received phase difference data and the previous phase control data stored in the memory, and a clock generation circuit for generating an operation clock signal. 4. A multi-plane space diversity type digital radio receiving apparatus according to claim 3, further comprising a switching control circuit for controlling a switching operation of said switch based on said operation clock signal. In a multi-plane space diversity type digital radio receiving apparatus which cascade-connects a plurality of synchronous combining sections for synchronously combining two input signals and synchronously combines received signals from a plurality of antennas, the first of the plurality of synchronous combining sections is provided. A synchronous synthesizing unit synthesizes a local oscillation circuit that generates a common local oscillation signal, two mixers that convert two received signals into intermediate frequency signals, and two intermediate frequency signals output from the two mixers. A synthesizing unit for transmitting to the subsequent synthesizing unit, a phase difference detecting circuit for detecting a phase difference between the two intermediate frequency signals input to the synthesizing unit, and transmitting the phase difference data to the EPS control unit; An EPS (infinite phase shifter) for adjusting the phase of the common local oscillation signal supplied to one of the two mixers according to the phase control data supplied from the EPS control unit; It has been multifaceted space diversity type digital radio receiver and wherein the are. A synchronous synthesizing unit other than the first synchronous synthesizing unit includes a mixer for converting a received signal into an intermediate frequency signal, and a synthesizer for synthesizing the intermediate frequency signal output from the mixer and the intermediate frequency signal from the preceding-stage synchronous synthesizing unit. A phase difference detection circuit for detecting a phase difference between the two intermediate frequency signals input to the synthesizer and sending the phase difference data to the EPS control unit; and a phase control data supplied from the EPS control unit. And an EPS (infinite phase shifter) that adjusts the phase of the common local oscillation signal and supplies the adjusted local oscillation signal to the mixer. 6. The multi-plane space die according to claim 5, wherein the phase control data is generated based on the phase difference data, and a plurality of EPS (infinite phase shifters) of the synchronous synthesizing unit are time-division multiplexed. Over City type digital radio receiver.

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