JPH09322537A - Digital-to-synchro conversion method - Google Patents

Digital-to-synchro conversion method

Info

Publication number
JPH09322537A
JPH09322537A JP8136773A JP13677396A JPH09322537A JP H09322537 A JPH09322537 A JP H09322537A JP 8136773 A JP8136773 A JP 8136773A JP 13677396 A JP13677396 A JP 13677396A JP H09322537 A JPH09322537 A JP H09322537A
Authority
JP
Japan
Prior art keywords
output
digital
conversion method
transformers
synchro
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8136773A
Other languages
Japanese (ja)
Other versions
JP3703115B2 (en
Inventor
Ryoichi Katagiri
良一 片桐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tamagawa Seiki Co Ltd
Original Assignee
Tamagawa Seiki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tamagawa Seiki Co Ltd filed Critical Tamagawa Seiki Co Ltd
Priority to JP13677396A priority Critical patent/JP3703115B2/en
Publication of JPH09322537A publication Critical patent/JPH09322537A/en
Application granted granted Critical
Publication of JP3703115B2 publication Critical patent/JP3703115B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Control Of Ac Motors In General (AREA)
  • Ac-Ac Conversion (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PROBLEM TO BE SOLVED: To avoid the discrepancies between the respective phases of the output voltages of synchro outputs, by a method in which adjusting resistors are connected in series to output terminals so as to make the respective resistance components of the secondary sides of respective transformers equal to each other when looking from the sides of the respective output terminal side. SOLUTION: In order to make the resistance components of the secondary sides 4b and 5b of respective transformers 4 and 5 equal to each other when looking from the sides of respective output terminals S1-S2, adjusting resistors +RS1 and +RS2 are connected in series to the 1st output terminal S1 and the 3rd output terminal S3. The adjusting resistors +RS1 and +RS2 are predetermined so as to be +RS1=R3-R1 and +RS2=R3-R2. Therefore, the resistance components of the secondary sides of the transformers are equal to each other when looking from the sides of the output terminals, and hence the output voltage levels of the respective phases of 3-phase synchro outputs 6 are equal to each other, so that the high precision control on the load side can be realized.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、デジタル/シンク
ロ変換方法に関し、特に、シンクロ出力を得る出力端子
側からの各抵抗分を同一とし、シンクロ出力の各相間の
出力電圧のズレを防止するための新規な改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital / synchronous conversion method, and more particularly, to prevent the deviation of the output voltage between the phases of the synchro output by making the same resistances from the output terminals for obtaining the synchro output. Regarding new improvements in.

【0002】[0002]

【従来の技術】従来、用いられていたこの種のデジタル
/シンクロ変換方法としては、一般に、図2で示す方法
が採用されている。すなわち、図2において符号1で示
されるものはデジタル角度入力2が入力されるD/A変
換器であり、このD/A変換器1から出力されるアナロ
グ信号1aはアンプ3を介して第1、第2トランス4,
5の1次側4a,5aに入力されている。前記第2トラ
ンス5の2次側5bは、第2出力端子S2が接続されて
いると共に第1トランス4の2次側4bの中点aに接続
されている。この第1トランス4の2次側4bの両端に
は第1、第3出力端子S1,S3が接続されている。
2. Description of the Related Art As a digital / synchronous conversion method of this type which has been conventionally used, the method shown in FIG. 2 is generally adopted. That is, the reference numeral 1 in FIG. 2 is a D / A converter to which the digital angle input 2 is input, and the analog signal 1 a output from this D / A converter 1 is output to the first via the amplifier 3. , Second transformer 4,
5 is input to the primary side 4a, 5a. The secondary side 5b of the second transformer 5 is connected to the second output terminal S2 and also to the midpoint a of the secondary side 4b of the first transformer 4. First and third output terminals S1 and S3 are connected to both ends of the secondary side 4b of the first transformer 4.

【0003】従って、D/A変換器1に入力されたデジ
タル角度入力2はD/A変換されて各アンプ3を経て各
トランス4,5の入力側4a,5aに入力される。各ト
ランス4,5の出力側4b,5bの各出力端子S1〜S
3には、三相交流信号からなるシンクロ出力6が出力さ
れる。
Therefore, the digital angle input 2 inputted to the D / A converter 1 is D / A converted and inputted to the input sides 4a, 5a of the transformers 4, 5 through the respective amplifiers 3. Output terminals S1 to S of output sides 4b and 5b of the transformers 4 and 5, respectively.
A synchro output 6 composed of a three-phase AC signal is output to 3.

【0004】[0004]

【発明が解決しようとする課題】従来のデジタル/シン
クロ変換方法は、以上のように構成されているため、次
のような課題が存在していた。すなわち、各トランスの
2次側においては、図2の抵抗分R1,R2,R3が存
在するが、これらの各抵抗分R1〜R3は同一ではな
く、負荷(図示せず)を接続するとシンクロ出力におけ
る出力電圧にズレが生じることになり、負荷側に供給す
るシンクロ出力6の精度が低下し、負荷側の動作精度が
低下することになっていた。
Since the conventional digital / synchronous conversion method is configured as described above, there have been the following problems. That is, on the secondary side of each transformer, the resistance components R1, R2, and R3 of FIG. 2 exist, but these resistance components R1 to R3 are not the same, and if a load (not shown) is connected, the synchro output is obtained. Therefore, the output voltage is deviated, the accuracy of the synchro output 6 supplied to the load side is decreased, and the operation accuracy of the load side is decreased.

【0005】本発明は、以上のような課題を解決するた
めになされたもので、特に、シンクロ出力を得る出力端
子側からの各抵抗分を同一とし、シンクロ出力の出力電
圧の各相間のズレを防止するようにしたデジタル/シン
クロ変換方法を提供することを目的とする。
The present invention has been made to solve the above problems, and in particular, the resistances from the output terminal side for obtaining the synchro output are made the same, and the output voltage of the synchro output shifts between the phases. It is an object of the present invention to provide a digital / synchronization conversion method for preventing the above.

【0006】[0006]

【課題を解決するための手段】本発明によるデジタル/
シンクロ変換方法は、デジタル角度信号をD/A変換器
に入力して得たアナログ信号を1対のトランスを介して
3個の出力端子から三相交流のシンクロ出力を出力する
ようにしたデジタル/シンクロ変換方法において、前記
出力端子に直列に調整用の抵抗を設け、前記各出力端子
側からみた各トランスの2次側の各抵抗分を同一とする
方法である。
Digital / digital according to the invention
The synchro conversion method is a digital / digital conversion method in which an analog signal obtained by inputting a digital angle signal to a D / A converter is output as a three-phase AC synchro output from three output terminals via a pair of transformers. In the synchro conversion method, a resistor for adjustment is provided in series with the output terminal, and the resistances on the secondary side of the transformers viewed from the output terminal side are the same.

【0007】[0007]

【発明の実施の形態】以下、図面と共に本発明によるデ
ジタル/シンクロ変換方法の好適な実施の形態について
説明する。なお、従来例と同一又は同等部分については
同一符号を用いて説明する。図1において符号1で示さ
れるものはデジタル角度入力2が入力されるD/A変換
器であり、このD/A変換器1から出力されるアナログ
信号1aはアンプ3を介して第1、第2トランス4,5
の1次側4a,5aに入力されている。前記第2トラン
ス5の2次側5bは、第2出力端子S2が接続されてい
ると共に第1トランス4の2次側4bの中点aに接続さ
れている。この第1トランス4の2次側4bの両端には
第1、第3出力端子S1,S3が接続されている。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the digital / synchronous conversion method according to the present invention will be described below with reference to the drawings. Note that the same or equivalent parts as those in the conventional example will be described using the same reference numerals. A reference numeral 1 in FIG. 1 denotes a D / A converter to which a digital angle input 2 is input. 2 transformers 4, 5
Is input to the primary side 4a, 5a of the. The secondary side 5b of the second transformer 5 is connected to the second output terminal S2 and also to the midpoint a of the secondary side 4b of the first transformer 4. First and third output terminals S1 and S3 are connected to both ends of the secondary side 4b of the first transformer 4.

【0008】さらに、第1出力端子S1及び第3出力端
子S3には、各出力端子S1〜S3側からみた各トラン
ス4,5の2次側4b,5bの各抵抗分を同一とするた
めに、調整用の抵抗+RS1及び+RS3が直列に設け
られており、出力側からみて各抵抗分が同一となるよう
に構成されている。この調整用の抵抗+RS3は+RS
3=R3−R2であると共に、抵抗+RS1は+RS1
=R3−R1として設定されている。なお、この抵抗は
第1、第3出力端子S1,S3のみではなく、他の出力
端子S2にも必要であれば設ける。
Further, in order to make the first output terminal S1 and the third output terminal S3 have the same resistance components on the secondary sides 4b and 5b of the transformers 4 and 5 viewed from the output terminals S1 to S3 side, respectively. The adjusting resistors + RS1 and + RS3 are provided in series, and the resistors are configured to be the same when viewed from the output side. This adjustment resistor + RS3 is + RS
3 = R3-R2 and the resistance + RS1 is + RS1
= R3-R1 is set. Note that this resistor is provided not only in the first and third output terminals S1 and S3 but also in the other output terminal S2 if necessary.

【0009】従って、前述の調整用の抵抗+RS1及び
+RS3を直列接続することによって各出力端子S1〜
S3側からの各抵抗分が同一に調整設定されているた
め、各出力端子S1〜S3に出力された3相交流信号か
らなるシンクロ出力6の各相の出力電圧レベルは従来の
ようなズレを伴うことなく、ほぼ同一レベルの3相交流
のシンクロ出力6を得ることができる。
Therefore, each of the output terminals S1 to S1 is connected by connecting the adjusting resistors + RS1 and + RS3 in series.
Since the respective resistance components from the S3 side are adjusted and set to be the same, the output voltage levels of the respective phases of the synchro output 6 composed of the three-phase AC signals output to the respective output terminals S1 to S3 have a conventional deviation. Without this, it is possible to obtain the synchro output 6 of the three-phase alternating current having substantially the same level.

【0010】[0010]

【発明の効果】本発明によるデジタル/シンクロ変換方
法は、以上のように構成されているため、次のような効
果を得ることができる。すなわち、各出力端子に調整用
の抵抗を直列に設けているため、出力端子側からみたト
ランスの2次側の抵抗分が同一となり、各出力端子を経
て出力される3相のシンクロ出力の各相の出力電圧レベ
ルが同レベルとなり、負荷側の制御を高精度とすること
ができる。
Since the digital / synchronous conversion method according to the present invention is configured as described above, the following effects can be obtained. That is, since a resistance for adjustment is provided in series with each output terminal, the resistance of the secondary side of the transformer seen from the output terminal side becomes the same, and each of the three-phase synchronized outputs output through each output terminal. The output voltage levels of the phases become the same level, and the load side control can be performed with high accuracy.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明によるデジタル/シンクロ変換方法を示
す構成図である。
FIG. 1 is a configuration diagram showing a digital / synchronization conversion method according to the present invention.

【図2】従来のデジタル/シンクロ変換方法を示す構成
図である。
FIG. 2 is a configuration diagram showing a conventional digital / synchronization conversion method.

【符号の説明】[Explanation of symbols]

1 D/A変換器 2 デジタル角度信号 1a アナログ信号 4,5 トランス 6 シンクロ出力 S1〜S3 出力端子 4b,5b 2次側 +RS1,+RS3 調整用の抵抗 1 D / A converter 2 Digital angle signal 1a Analog signal 4,5 Transformer 6 Synchro output S1-S3 Output terminals 4b, 5b Secondary side + RS1, + RS3 Resistance for adjustment

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 デジタル角度信号(2)をD/A変換器(1)
に入力して得たアナログ信号(1a)を1対のトランス(4,
5)を介して3個の出力端子(S1〜S3)から三相交流のシン
クロ出力(6)を出力するようにしたデジタル/シンクロ
変換方法において、前記出力端子(S1〜S3)に直列に調整
用の抵抗(+RS1,+RS3)を設け、前記各出力端子(S1〜S3)
側からみた各トランス(4,5)の2次側(4b,5b)の各抵抗分
を同一とすることを特徴とするデジタル/シンクロ変換
方法。
1. A digital angle signal (2) to a D / A converter (1)
Input analog signal (1a) to a pair of transformers (4,
In the digital / synchronous conversion method in which the three-phase AC synchro output (6) is output from the three output terminals (S1 to S3) via 5), the output terminals (S1 to S3) are adjusted in series. Resistance (+ RS1, + RS3) for each output terminal (S1 ~ S3)
A digital / synchronous conversion method characterized in that the respective resistance components on the secondary side (4b, 5b) of the respective transformers (4,5) viewed from the side are the same.
JP13677396A 1996-05-30 1996-05-30 Digital / synchro conversion method Expired - Fee Related JP3703115B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13677396A JP3703115B2 (en) 1996-05-30 1996-05-30 Digital / synchro conversion method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13677396A JP3703115B2 (en) 1996-05-30 1996-05-30 Digital / synchro conversion method

Publications (2)

Publication Number Publication Date
JPH09322537A true JPH09322537A (en) 1997-12-12
JP3703115B2 JP3703115B2 (en) 2005-10-05

Family

ID=15183186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13677396A Expired - Fee Related JP3703115B2 (en) 1996-05-30 1996-05-30 Digital / synchro conversion method

Country Status (1)

Country Link
JP (1) JP3703115B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102538832A (en) * 2011-12-23 2012-07-04 连云港杰瑞电子有限公司 Digital-shaft angle signal converting method
CN102589584A (en) * 2012-02-15 2012-07-18 连云港杰瑞电子有限公司 Method for converting high-precision single-chip digital signal into shaft angle signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102538832A (en) * 2011-12-23 2012-07-04 连云港杰瑞电子有限公司 Digital-shaft angle signal converting method
CN102589584A (en) * 2012-02-15 2012-07-18 连云港杰瑞电子有限公司 Method for converting high-precision single-chip digital signal into shaft angle signal

Also Published As

Publication number Publication date
JP3703115B2 (en) 2005-10-05

Similar Documents

Publication Publication Date Title
US4773274A (en) Electromagnetic flow meter
JPH11330966A (en) Circuit arrangement including digital-analog current converter
JPH09322537A (en) Digital-to-synchro conversion method
US6239733B1 (en) Current interpolation circuit for use in an A/D converter
US4814696A (en) Method and circuit arrangement for measuring in-phase and quadrature components of current in an electrical alternating current power supply
JP3197309B2 (en) Electrical measuring device
JP4090902B2 (en) Transformer test equipment
JPS6146566A (en) Absolute value circuit
JP2003505966A (en) Method and apparatus for converting voltage to current
JP3265269B2 (en) Power measuring method and power measuring apparatus using this method
JP3159289B2 (en) Parallel A / D converter
JP2690647B2 (en) Error compensation type transformer
JPS60174958A (en) Phase decision apparatus
SU1177767A1 (en) Device for indicating phase quadrature
JPH099505A (en) Harmonic current detecting method for active filter
JPH03153112A (en) Method and circuit for shifting bias
JPH0754987Y2 (en) Instrument transformer
JP2690646B2 (en) Electronic watt-hour meter
SU1536473A1 (en) Modulus shaping unit
SU862334A1 (en) Current regulator
JPH0998067A (en) 90-degree phase shifter
SU1430943A1 (en) Controlled device for producing alternating current
IE921394A1 (en) Interface circuit for telephone exchanges
JPH04331475A (en) Inverter current detecting method
RU2084077C1 (en) Device for regulation of frequency in n-phase electric equipment

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20050322

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050516

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050712

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050715

R150 Certificate of patent (=grant) or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080729

Year of fee payment: 3

FPAY Renewal fee payment (prs date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090729

Year of fee payment: 4

LAPS Cancellation because of no payment of annual fees