JPH09321827A5 - - Google Patents

Info

Publication number
JPH09321827A5
JPH09321827A5 JP1997023352A JP2335297A JPH09321827A5 JP H09321827 A5 JPH09321827 A5 JP H09321827A5 JP 1997023352 A JP1997023352 A JP 1997023352A JP 2335297 A JP2335297 A JP 2335297A JP H09321827 A5 JPH09321827 A5 JP H09321827A5
Authority
JP
Japan
Prior art keywords
shared memory
prefetch
address
state machine
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997023352A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09321827A (ja
JP3748308B2 (ja
Filing date
Publication date
Priority claimed from US08/601,909 external-priority patent/US5829042A/en
Application filed filed Critical
Publication of JPH09321827A publication Critical patent/JPH09321827A/ja
Publication of JPH09321827A5 publication Critical patent/JPH09321827A5/ja
Application granted granted Critical
Publication of JP3748308B2 publication Critical patent/JP3748308B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP02335297A 1996-02-15 1997-02-06 周辺装置とコンピュータ・ネットワークとをインタフェースする装置 Expired - Fee Related JP3748308B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US601,909 1996-02-15
US08/601,909 US5829042A (en) 1996-02-15 1996-02-15 Prefetch operation for network peripheral device having shared memory

Publications (3)

Publication Number Publication Date
JPH09321827A JPH09321827A (ja) 1997-12-12
JPH09321827A5 true JPH09321827A5 (enExample) 2004-11-04
JP3748308B2 JP3748308B2 (ja) 2006-02-22

Family

ID=24409241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02335297A Expired - Fee Related JP3748308B2 (ja) 1996-02-15 1997-02-06 周辺装置とコンピュータ・ネットワークとをインタフェースする装置

Country Status (3)

Country Link
US (1) US5829042A (enExample)
EP (1) EP0790560A3 (enExample)
JP (1) JP3748308B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6029226A (en) * 1996-09-30 2000-02-22 Lsi Logic Corporation Method and apparatus having automated write data transfer with optional skip by processing two write commands as a single write command
US6078402A (en) * 1997-09-24 2000-06-20 Hewlett-Packard Company Accessory based resource offset mechanism for a PCI bus in a printer
JP3573980B2 (ja) 1998-11-13 2004-10-06 富士通株式会社 情報処理装置及び情報処理システム
US6651088B1 (en) * 1999-07-20 2003-11-18 Hewlett-Packard Development Company, L.P. Method for reducing coherent misses in shared-memory multiprocessors utilizing lock-binding prefetchs
US6718454B1 (en) 2000-04-29 2004-04-06 Hewlett-Packard Development Company, L.P. Systems and methods for prefetch operations to reduce latency associated with memory access
SG143051A1 (en) * 2000-06-30 2008-06-27 Silverbrook Res Pty Ltd A print engine for a pagewidth printhead incorporating micro- electromechanical nozzle arrangements
US6792496B2 (en) * 2001-08-02 2004-09-14 Intel Corporation Prefetching data for peripheral component interconnect devices
CA2378777A1 (en) * 2002-03-25 2003-09-25 Catena Networks Canada Inc. Shared program memory with fetch and prefetch buffers
US6931494B2 (en) * 2002-09-09 2005-08-16 Broadcom Corporation System and method for directional prefetching
JP2004220575A (ja) * 2002-12-27 2004-08-05 Ricoh Co Ltd カード型メモリのインターフェース回路、その回路を搭載したａｓｉｃ、及びそのａｓｉｃを搭載した画像形成装置
US7827387B1 (en) * 2006-09-08 2010-11-02 Marvell International Ltd. Communication bus with hidden pre-fetch registers
US7917502B2 (en) * 2008-02-27 2011-03-29 International Business Machines Corporation Optimized collection of just-in-time statistics for database query optimization
JP5052592B2 (ja) * 2009-12-28 2012-10-17 株式会社日立製作所 ストレージ管理システム、ストレージ階層管理方法及び管理サーバ
US8775699B2 (en) * 2011-03-01 2014-07-08 Freescale Semiconductor, Inc. Read stacking for data processor interface
US10613992B2 (en) * 2018-03-13 2020-04-07 Tsinghua University Systems and methods for remote procedure call

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5835627A (ja) * 1981-08-26 1983-03-02 Toshiba Corp メモリデ−タ先取り制御方式
US4535404A (en) * 1982-04-29 1985-08-13 Honeywell Information Systems Inc. Method and apparatus for addressing a peripheral interface by mapping into memory address space
KR940002905B1 (en) * 1989-12-15 1994-04-07 Ibm Apparatus for conditioning priority arbitration in buffered direct memory addressing
US5101477A (en) * 1990-02-16 1992-03-31 International Business Machines Corp. System for high speed transfer of data frames between a channel and an input/output device with request and backup request count registers
US5197128A (en) 1991-03-04 1993-03-23 Hewlett-Packard Company Modular interface
JP2703668B2 (ja) * 1991-03-18 1998-01-26 株式会社日立製作所 データ転送制御装置および磁気ディスク制御装置
US5392412A (en) * 1991-10-03 1995-02-21 Standard Microsystems Corporation Data communication controller for use with a single-port data packet buffer
US5440691A (en) * 1992-02-27 1995-08-08 Digital Equipment Corporation, Pat. Law Group System for minimizing underflowing transmit buffer and overflowing receive buffer by giving highest priority for storage device access
US5412782A (en) * 1992-07-02 1995-05-02 3Com Corporation Programmed I/O ethernet adapter with early interrupts for accelerating data transfer
US5307459A (en) * 1992-07-28 1994-04-26 3Com Corporation Network adapter with host indication optimization
US5299313A (en) * 1992-07-28 1994-03-29 3Com Corporation Network interface with host independent buffer management
US5434872A (en) * 1992-07-28 1995-07-18 3Com Corporation Apparatus for automatic initiation of data transmission
US5546543A (en) * 1993-03-26 1996-08-13 Digital Equipment Corporation Method for assigning priority to receive and transmit requests in response to occupancy of receive and transmit buffers when transmission and reception are in progress
WO1994027216A1 (en) * 1993-05-14 1994-11-24 Massachusetts Institute Of Technology Multiprocessor coupling system with integrated compile and run time scheduling for parallelism

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