JPH09319650A - Circuit for interface between 8-bit block and 8-bitx(n) blocks - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time of exchange generated on the side of a system in the case of exchanging data between subsystems by exchanging the data through a dual port RAM composed of specified number of bits. SOLUTION: Concerning the exchange of data from a 16-bit block, firs of all, addresses (1) are outputted from 8-bit×(n) blocks 4, and these addresses are simultaneously inputted to (n) pieces of 8-bit dual port RAM 2. Next, WR signals and RAM select signals are simultaneously outputted from the 8-bit×(n) blocks 4 to (n) pieces of dual port RAM 2. At such a time, since data are simultaneously written into (n) pieces of dual port RAM 2, one time of write is enough for the side of [8-bit×(n) blocks]. When reading the data, just a write signal changes into read signal and the same operation is shown. Thus, data can be exchanged for 1/n time of conventional case in a system composed of 8-bit×(n) blocks.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface circuit between a block of 8 bits and a block of 8 bits.times.n bits.

[0002]

2. Description of the Related Art Conventional 8-bit block, 8 bits × n
In the block, when data is transferred via the dual port RAM, the circuit configuration is as shown in FIG. This will be described with reference to the timing charts of FIGS. First, when data is transferred from the 8-bit block 3 to the 8-bit × n block 4 by the conventional method, the timing shown in FIG. 4 is obtained. Here, for data transfer, the address signal (1) and the RD signal (2) are output from the 8-bit × n block 4 side to the timing generation circuit 1.

The timing generation circuit 1 has (1) and (2)
When the address signal is the address of the data transfer area, the WAIT signal (3) is returned to the 8-bit × n block 4. This W until the series of operations after this end
The AIT signal continues to be output. At the same time as outputting the WAIT signal (3), the timing generation circuit 1 outputs the B address (7), the B data RD (8), and the BRAM select (9).
Is output to the dual port RAM 2 and the # 1 latch signal (4) falls. Here, as the B address, the address of the data transfer area is output, and the address is sequentially increased.

Next, after the data is output from the dual port RAM 2, the latch signal for # 1 rises and the data at address (A) +0 is latched in the # 1 latch 5-1. This operation is repeated up to the #n latch 5-n, the output of the WAIT signal (3) is stopped when n pieces of data are gathered, and the 8-bit × n block 4 takes in the data from the 8-bit side. Up to this time (access time of the dual port RAM 2) × n is required.

As shown in the timing chart of FIG. 5, the movement from the 8 bit × n block 4 to the 8 bit block 3 is such that the previous RD signal (2) becomes the WR signal (2) 'and the # 1 latch signal (4 )-# N Latch signal (6) outputs # 1 (4) '-#
B data RD (8) is output to B data WR at the n output (6) '
It changes to (8) ', the data flow is reversed, and the write cycle of the 8-bit × n block 4 is (access time of the dual port RAM 2) × n until the writing to the dual port RAM 2 is completed n times. Meet up.

[0006]

Therefore, at the time of data transfer, the system on the side of 8 bits × n block 4 continues to wait, which causes a problem that the processing time is long in a system requiring high speed operation.

An object of the present invention is to provide a problem in the prior art in the side of a system composed of 8 bits × n when transferring data between a block composed of 8 bits × n and a subsystem composed of 8 bits. The delivery waiting time that occurs is 1 /
An object is to provide an interface circuit between 8 bit blocks and 8 bit × n blocks which can be shortened to n.

[0008]

In order to solve this problem, the 8-bit block-to-8-bit × n-block interface circuit according to the present invention has a data transfer interface with the outside and a block with an 8-bit data transfer interface. In a system in which the transfer interface is configured by combining a block of 8 bits × n (n is an integer multiple), data transfer is performed by the block of 8 bits and the block of 8 bits × n.
N 8 connected in parallel to both block and
It is configured to be done via a bit-width dual port RAM.

[0009]

BEST MODE FOR CARRYING OUT THE INVENTION In the present invention, when data is mutually transmitted between an 8-bit block and an 8-bit × n block, the 8-bit block and the 8-bit × n block are connected in parallel. It is configured to be performed via n 8-bit wide dual port RAMs. As a result, the data transfer time between both blocks can be reduced to 1 / n of the data transfer time in the conventional technique.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention reduces the waiting time for waiting n hours to 1
In order to reduce to / n, as shown in FIG. 1, n 8-bit wide dual port RAMs connected in parallel to both 8-bit block 3 and 8-bit × n block 4
I tried to have 2. The operation of this configuration is shown below. 1
For data transfer from the 6-bit block, first, an address is output from the 8-bit × n block 4, and this address is simultaneously input to the n 8-bit dual-port RAMs 2.

Next, the WR signal and the RAM select signal are simultaneously output from the 8 bit × n block 4 to the n dual port RAMs 2. At this time, in order to simultaneously write data to the n dual port RAMs 2 (8 bits x
(n block side) ends with one write. When reading data, the write signal becomes the read signal and the same movement is shown.

[0012]

As described above, by implementing the present invention, data can be transmitted / received in 1 / n the time of the conventional system in a system composed of 8 bit blocks and 8 bit × n blocks.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a timing diagram for explaining the operation of the circuit of the present invention.

FIG. 3 is a block diagram showing a configuration example of a conventional 8-bit block to 8-bit × n inter-block interface circuit.

FIG. 4 is a timing chart for explaining the operation of the conventional example of FIG.

5 is a timing chart for explaining the operation of the conventional example of FIG.

[Explanation of symbols]

 1 Timing Generation Circuit 2 8-bit Width Dual Port RAM 3 8-bit Block 4 8-bit × n Block 5-1 ... 5-n Latch

Claims (1)

[Claims] 1. In a system in which a block having an 8-bit external data transfer interface and a block having a 8-bit external data transfer interface (n is an integer multiple) are combined, data transfer is performed. An 8-bit block configured to be performed via n 8-bit wide dual port RAMs connected in parallel to the 8-bit block and the 8-bit × n block. Interface circuit between 8 bits × n blocks.