JPH09311844A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To easily perform a test for detection of a fault, etc., by assigning a common device number to all processors which are simultaneously operating and also assigning an inherent device number to every processor. SOLUTION: The processors 10-1 to 10-n have different inherent device numbers 11 and also have a common device number 12 which is given in common to all processors and validated when these processors are simultaneously carrying out the same process. When a request is received via a bus 40 to designate the device numbers, the comparators 13 and 14 compare the requested device numbers with the numbers 11 and 12 respectively to decide the coincidence between them and then give answers to the bud 40 only when the coincidence is confirmed between those numbers. If a certain processor has a fault, the reference is given to this processor by means of its inherent number 11. Thus, only the relevant processor can be accessed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a high reliability in which at least two processing devices (processors) are connected by a bus and the same processing is executed at the same time, thereby detecting a failure and performing necessary disconnection processing and the like. The present invention relates to an information processing device.

Currently, information processing devices are widely used in various fields, and a failure of the information processing device has a serious social and economic impact. Therefore, when a failure occurs, there is a need for an information processing apparatus with high fault tolerance that can replace the failed processing apparatus and continue processing without stopping the entire processing apparatus.

[0003]

2. Description of the Related Art FIG. 7 shows an example of a conventional highly reliable information processing apparatus. The processing devices 10-1 to 10-3 are connected by the bus 40 and execute the same processing at the same time. Bus 4
The processing results flowing to 0 are compared, and if the processing results do not match, it is determined that there is a failure. In particular, when the number of processing devices is three or more, the majority processing logic of the processing results detects a processing device that gives a processing result that does not match the processing results of other processing devices as a failure, and the processing device is detected by the bus 40. Disconnect from.

To detect this failure, for example, the processing device 10-1 serves as a master, and the processing results are compared by the following procedure. First, each processing device 1
0-1 to 10-3 input the data of the processing request flowing through the bus 40 (FIG. 7) and simultaneously execute the data processing requested by the processing circuits 80 (FIG. 7). Data output to the bus 40 is performed only by the master processing device 10-1. Master processor 10
When -1 sends the processing result of the data to the bus 40 (in FIG. 7), the other processing devices 10-2 and 10-3 respectively input the processing result to the failure detection circuit 70 in its own device.

On the other hand, the processing circuit 80 of each of the processing devices 10-2 and 10-3 outputs the processing result for the previous data input to the bus 4
It is output to the failure detection circuit 70 of its own device without flowing to 0 ('in FIG. 7).

The fault detection circuit 70 in each of the processing devices 10-2 and 10-3 is the same as the processing device 10 input from the bus 40.
The processing result of -1 is compared with the processing result processed by the own device, and the comparison result is mutually transmitted and received (in FIG. 7).

As a result of comparing the processing results, if all the processing results match, it can be determined that all the processing devices 10-1 to 10-3 are normal. If processing device 1
If the comparison result by the failure detection circuit 70 of either 0-2 or 10-3 does not match, the processing device 10-2
Alternatively, the processing device 10-3 is out of order. If the comparison results of the failure detection circuits 70 of the processing devices 10-2 and 10-3 do not match, it is determined that the processing device 10-1 has failed.

The processing device determined to be out of order is automatically disconnected from the bus 40, and the remaining two processing devices continue the processing by the simultaneous operation.

[0009]

In the high-reliability information processing apparatus as described above, since a plurality of processing devices simultaneously perform the same processing operation, conventionally, only a specific processing device performs a different processing operation from others. I couldn't do that. Further, when a processor is disconnected from the bus due to a failure, the registers and the like of the processor cannot be referenced, and the processor that has recovered from the failure is reconnected to the bus without stopping the entire information processing apparatus. The recovery process was difficult. Also, when performing a failure detection test or debug for whether or not the failed processing unit is automatically disconnected from the bus, all the processing units operate in the same way at the same time, so the failure detection test or debugging is performed. There was a problem that it was difficult.

The present invention solves the above problems and enables a specific processing device to perform an operation different from the others in a high reliability information processing device, and a process separated from a bus. Even in a device, a specific register can be referred to from another device, and when a new processing device is connected to a bus, information is transmitted and connected to another processing device through a specific register. The purpose is to match the state of the processing device with the states of other processing devices that are currently operating at the same time, to operate them at the same time, and to easily perform a failure detection test or the like.

[0011]

FIG. 1 shows a configuration example of the present invention. In FIG. 1, 10 is a multiplexing unit composed of a plurality of processing devices, 10-1 to 10-n are processing devices that simultaneously execute the same processing in synchronization with the same clock, and 11 is a number assigned to each processing device. The assigned unique device number (unique device identifier), 12 is a common device number (common device identifier) to which the same number is given to all processing devices, 13
Reference numeral 14 is a comparison circuit, 20 is various processing circuits for performing processing required by a decoder and an arithmetic circuit, and 21 is a bus connection for disconnecting or connecting its own device to a bus.
Detachment means, 22 is a decoder for decoding addresses of registers and memories, 30 is a bus connection register for notifying another processing device whether its own device is connected to the bus or disconnected from the bus, and 31 is each process A bus status register indicating the bus connection status of the device, 32 is a handshake register for notifying whether data is ready when communicating with another processing device, and 33 is communication with another processing device A data communication register 40 for storing data to be stored represents a bus composed of data lines and control signal lines.

In the first invention, the processing devices 10-1 to 10-10
-N is a unique device number 11 which is different for each processing device,
It has a common device number 12 which is given in common to each processing device and is effective when the same processing is being executed simultaneously with other processing devices. When there is a request for specifying the device number via the bus 40, the comparison circuits 13 and 14 compare whether the requested device number and the unique device number 11 / common device number 12 match, A response is returned to the bus 40 only when either of them matches.

In addition to the unique device number 11 for each processing device, by having a common device number 12 that is effective when the processing devices are simultaneously executing the same processing, other processing devices (for example, not shown) are provided. When referred to from (input / output device), the processing devices in the multiplexing unit 10 operating simultaneously appear as one processing device. Further, when a certain processing device fails, it is possible to access only that processing device by referring to the unique device number 11 unique to that processing device.

Further, in the second invention, each processing unit 10
-1 to 10-n have bus connection / disconnection means 21,
This allows the processors 10-1 to 10-n to be logically disconnected from the bus 40. The processing device is disconnected from the bus 40 by writing "0" in the bus connection register 30, for example. Then, in response to the request specifying the unique device number 11, even if the processing device having the unique device number 11 is disconnected from the bus 40, a response is returned. Therefore, unique device number 11
By issuing a request specifying, even if the processing device is disconnected due to a failure, necessary information can be obtained from the processing device.

Further, in the third invention, as the request specifying the unique device number 11 in the second invention, for example, the bus status register 31, the handshake register 3 are used.
2. It is possible to refer to a specific register such as the data communication register 33. That is, when the comparison result of the comparison circuit 13 indicates “match”, an instruction is issued to the decoder 22 in each processing circuit 20, and the value of the specific register requested from the decoding result is sent to the bus 40.

In the fourth aspect of the invention, when a processing device separated from the bus 40 or a new processing device is connected to the bus 40, the bus connection / disconnection means 21 sets "1" to the bus connection register 30, for example. By setting, it is possible to connect without stopping the operation of the multiplexing unit 10. At this time, using the handshake register 32 and the data communication register 33,
A means for transmitting information to another processing device is provided.

According to the fifth aspect of the invention, a processing unit separated from the bus 40 or a new processing unit is connected to the bus.
A means for connecting to the bus 40 by the disconnecting means 21 is provided, and at this time, means for notifying other processing devices that the own device has been added is provided. Specifically, when "1" is set in the bus connection register 30 and it is written that the own device is connected, the value is reflected in the bus status register 31 of another processing device via the bus 40. It has become. That is, the bus status register 31 always holds information as to whether each processing unit is currently connected to the bus 40 or disconnected from the bus 40.

According to the sixth aspect of the invention, the various processing circuits 20 of the respective processing devices have their own registers (for example, data By writing a value to the communication register 33), a means for notifying the other operating processing devices that the initialization process of the own device is completed is provided.

When a new processing device is connected instead of the processing device which has been broken down and has been disconnected, the fact that the processing device has been connected is notified. At this time, since the state of the connected processing unit is different from the state of the processing unit that is currently operating, communication is performed between the processing unit that is currently operating and the connected processing unit, and the states match. It is necessary to carry out the procedure. According to the fifth and sixth inventions, the processing for matching the states can be performed while the multiplexing unit 10 is operating. When the procedure for matching the states is completed, the connected processing device is made to have the same operation as the currently operating processing device, and the failure detection operation by the entire processing device is restarted.

According to the seventh aspect of the present invention, means for referring to the processing device by designating a unique device number in a state where the processing devices in the multiplexing unit 10 are simultaneously performing the same processing operation, Since only the processing device having the unique device number 11 that matches the specified unique device number responds, only the responding processing device is the other processing device from the state where the processing devices are simultaneously performing the same processing operation. And a means for automatically disconnecting the processing device from the bus 40 when the processing device performs another operation.

By referring to the device number unique to each processing device and intentionally shifting the operations of the processing devices that are simultaneously performing the same processing, the failure detection test of the processing device can be easily performed. Become.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram showing an example of a bus configuration and packets in the embodiment of the present invention.

The bus 40 shown in FIG. 1 is, for example, as shown in FIG.
As shown in FIG. 5, the data line 40a has a width of 64 bits, the bus connection state signal line 40b for n lines (n is the number of processing devices in the multiplexing unit 10), and the other control signal line 40c. As the other control signal line 40c, for example, a signal line indicating whether or not each processing device is mounted,
There is a signal line or the like indicating whether or not each processing device is operating simultaneously. The bus connection state signal line 40b is a signal line that connects the bus connection register 30 and the bus state register 31 of each processing device to each other.

The data flowing through the data line 40a is
There are request packets as shown in FIG. 2B and response packets as shown in FIG. The request packet includes a command indicating a request type such as a read request and a write request, a device number of a request destination (unique device number 11 or common device number 12), a register or a memory to be read or written, and the like. It is composed of an address and write data when the request is a write. Also, the response packet is
The type of reply indicating the response, the device number,
It is composed of read data and the like when the request is a read.

FIG. 3 shows a detailed configuration of the processing apparatus according to the embodiment of the present invention. In FIG. 3, those having the same reference numerals as those in FIG. 1 correspond to those shown in FIG.
50 is a request address in the request packet, 51 is a simultaneous operation signal indicating that they are operating at the same time, 52 is a memory in the processing device, 53 and 54 are bidirectional buffers, and 55 is a device number in the request packet.

In this example, three processing devices 10-1 to 10-1 are used.
Let 0-3 form a multiplexing unit. “01” as the unique device number of the processing device 10-1, the processing device 1
"10" as the unique device number of 0-2, the processing device 10-
“11” is given from the outside as the unique device number of 3. By giving a unique device number from the outside, the structures of the processing devices 10-1 to 10-3 can be made common. Here, the signal generation circuit of the unique device number corresponding to each slot is set so that these numbers “01” to “11” are automatically determined, for example, by the slot into which the board mounting each processing device is inserted. It is provided outside of.

On the other hand, the common device number is the processing device 10-
“00” is commonly given to 1 to 10-3. This common device number is valid only when the simultaneous operation signal 51 is validly input by the gate circuit 15.

By the device number 55 in the request packet,
When there is a request to access the internal resources of the processing devices 10-1 to 10-3, the comparison circuit 13 causes the device number 55
Is detected to match the unique device number, or the comparison circuit 14 detects that the device number 55 matches the common device number, and the simultaneous operation signal 51 is valid and the gate circuit 15 is open. The response to the request is returned only to.

The bidirectional buffers 53 and 54 can be controlled by the instructions of the various processing circuits 20 to disconnect the processing device from the bus 40. Each processing circuit 20 has a decoder and receives the setting of the bus connection register 30 to determine whether or not the processing device is disconnected from the bus 40 during normal operation.
However, even in the disconnected state, if the requested device number 55 matches the unique device number of the own device, the registers 31 to 33 (excluding the bus connection register 30) are referenced via the bidirectional buffer 54. And respond.

The handshake register 32 and the data communication register 33 are registers that can be arbitrarily referred to by another processing device and can be written with a value. These registers 32 and 33 are used for exchanging information with a set of processing devices operating simultaneously with the added processing device when another processing device is added instead of the processing device separated due to a failure. To be done.

FIG. 4 is an explanatory diagram of bus connection / disconnection according to the embodiment of the present invention. The disconnection of the processing device from the bus 40 is performed by setting the bus connection register 30 of each processing device. For example, the bus connection register 30
A value of "1" indicates a bus connection state, and a value of "0" indicates a bus disconnection state. As shown in FIG. 4A, the signal of the bus connection register 30 is notified to the bus status register 31 of another processing device via the bus connection status signal line 40b.

As shown in FIG. 4B, the bus status register 31 holds information on the bus connection / disconnection status from the bus connection register 30 of each processing unit. Each processing device can determine the processing device connected to the bus 40 from the bus status register 31.

FIG. 5 shows a communication processing flow when a processing device is newly added to the processing devices which are simultaneously operating. For example, assume that two of the processing devices 10-1 to 10-3 shown in FIG. 3 are operating at the same time, and a new processing device is added after one is disconnected due to a failure. The newly added processing device first performs internal initialization when connecting to the bus (S20 in FIG. 5), and sets "1 (bus connection)" in the bus connection register 30 when the initialization is completed. (S21). As a result, the connection status is notified to the bus status register 31 of the existing simultaneous processing device by the bus connection status signal line 40b described in FIG.

When the existing processing device confirms the insertion of a new processing device by the bus status register 31 in the state of waiting for time (S10) (S11), the handshake register 32 and data communication of the newly connected processing device. Communication is started using the register 33 for use.

The handshake register 32 and the data communication register 33 can read and write mutually set values from a new processing device and an existing processing device.
Here, assuming that the initial value of the handshake register 32 is "0", after reading the handshake register 32 and confirming that the value is "0" (S12, S
13) Write a command of a predetermined format to the data communication register 33 of the new processing device (S1
4), The handshake register 32 is set to "1" (S15).

The new processing device waits for the existing processing device to set "1" in the handshake register 32, and when it confirms that "1" has been reached (S22,
S23), read the data communication register 33 (S23)
24). Then, the received command read from the data communication register 33 is analyzed and executed (S25). When notifying the existing processing device of the execution result, the information to be notified is written in the data communication register 33 (S26), and "0" is set in the handshake register 32 (S27). Then, the process returns to step S22 and waits until the handshake register 32 becomes "1".

The existing processor sets "1" in the handshake register 32 (S15), waits for it to change to "0" (S16, S17), and then "0".
If it is confirmed, the data communication register 33 is read to read the data written by the new processing device (S18), the received data is analyzed, and necessary processing is executed (S19). The above sequence is repeated a predetermined number of times until the setting of the new processing device is completed and the new processing device and the existing processing device are in the same state.

By communication via the data communication register 33, system environment information from an existing processing device to a new processing device (for example, information on a connected input / output device,
(Memory capacity information, etc.) can be notified.

FIG. 6 illustrates a failure test for confirming that the processing device is disconnected from the simultaneous operation when any one of the processing devices performing the simultaneous operation performs another operation. FIG.

According to the present invention, a fault test for artificially causing a fault state and confirming whether or not the processing devices are separated from the simultaneous operation can be easily performed as follows. In the failure test, first, as shown in FIG. 6A, a predetermined failure test program 61 is executed by the entire processing unit 1 according to an instruction from the console 60 connected to the bus 40.
The data is loaded into the memory 52 of 0-1 to 10-3, and all the processing devices 10-1 to 10-3 execute the failure test program 61 at the same time.

The processing flow is shown in FIG. 6 (B). In this example, it is assumed that the processor having the unique device number “01”, that is, the processor 10-1 is put into a pseudo failure state. By changing the value of the unique device number, other processing devices can be brought into a failed state and disconnected.

When there is a request for reference by the unique device number "01" via the bus 40 (S30, S31), by comparison with the unique device number of the own device in each processing device (S3).
2), the processing devices 10-2 and 10-3 execute the processes of S32 to S34, and the processing device 10-1 executes the processes of S35 to S37.

That is, the processing devices 10-2 and 10-3
Since the requested unique device number is different from the unique device number of its own device, does not respond to the request and continues the normal simultaneous operation (S32). On the other hand, the processing device 10
Since -1 has the same unique device number, by responding to the request, the operation becomes different from that of other processing devices (S35).

The processing devices 10-2, 1 operating simultaneously by the processing device 10-1 executing processing different from other processing.
By comparing the operation with 0-3, it is considered that a mismatch occurs and the failure detection circuit 70 causes the processing device 10-1 to fail. Since the failure detection logic of the failure detection circuit 70 is the same as that of the conventional technique described in FIG. 7, detailed description thereof will be omitted here. When the processing device 10-1 is considered to be in failure, the processing device 10-1 is automatically detached from the processing devices operating simultaneously.

The processing units 10-2 and 10-3 use the bus status register 31 shown in FIG. 1 or another register similar thereto to indicate that the processing unit 10-1 having the unique unit number "01" has been disconnected. Confirm (S33). The confirmed result is written in a predetermined area of the memory 52 and logged (S34).

On the other hand, the processing device 10-1 confirms that it has been disconnected by the register set by the failure detection circuit 70 (S36), and similarly, the processing device 10-1.
The confirmation result is written and logged in a predetermined area of the memory 52 in 0-1 (S37).

After that, from the console 60, each processing unit 10
-1 to 10-3, by reading the logging information collected in the memory 52, it is checked whether or not the processing device 10-1 having the unique device number "01" is certainly disconnected, and the failure detection operation is verified. You can

[0048]

As described above, according to the present invention,
In an information processing apparatus that increases the reliability of the entire processing apparatus by causing two or more processing apparatuses to execute the same processing at the same time, a common apparatus number is assigned to all the processing apparatuses that are operating at the same time, and individual processing apparatuses are assigned. By assigning a unique device number to each, it is possible to easily identify the processing device that has failed.

Further, since communication can be performed with a processing device that is disconnected from the bus, the processing device that is currently operating simultaneously with the processing device that is trying to connect instead of the failed processing device. Notifying information, setting the connected processing unit to the same state as the currently operating processing unit, restarting the fault detection operation by the entire processing unit without stopping the entire information processing unit, and improving fault tolerance Will be able to.

Further, by referring to the device number unique to each processing device and intentionally shifting the operations of the processing devices that are simultaneously performing the same processing, the failure detection test of the processing device can be easily performed. Like

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration example of the present invention.

FIG. 2 is a diagram showing a configuration of a bus and an example of a packet in the embodiment of the present invention.

FIG. 3 is a diagram showing a detailed configuration of a processing device according to an embodiment of the present invention.

FIG. 4 is an explanatory diagram of bus connection / disconnection according to the embodiment of the present invention.

FIG. 5 is a diagram showing a communication processing flow when a processing device is newly added to a processing device that is performing simultaneous operations.

FIG. 6 is an explanatory diagram of a failure test according to the embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a conventional highly reliable information processing apparatus.

[Explanation of symbols]

 10 Multiplexing Units 10-1 to 10-n Processing Device 11 Unique Device Number 12 Common Device Number 13 Comparison Circuit 14 Comparison Circuit 20 Various Processing Circuits 21 Bus Connection / Disconnection Means 22 Decoder 30 Bus Connection Register 31 Bus Status Register 32 Handshake Register 33 Data communication register 40 Bus

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Shinya Kato 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Fujitsu Limited (72) Inventor, Koji Ishizuka 4-chome, Ueodaanaka, Nakahara-ku, Kanagawa Prefecture No. 1 in Fujitsu Limited (72) Inventor Fumitake Sugano 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Kanagawa Prefecture (72) Inventor Seiji Goto 3-22, Hakataekimae, Hakata-ku, Fukuoka, Fukuoka No. 8 Fujitsu Kyushu Digital Technology Co., Ltd. Inside the company

Claims (7)

[Claims] 1. An information processing apparatus comprising at least two processing devices connected via a bus, having the function of causing these processing devices to execute the same processing and comparing the results, wherein each processing device comprises: A means for holding a different unique device identifier for each processing device, and a common device identifier that is given to each processing device and is effective when the same process is executed simultaneously with other processing devices. Means,
Means for comparing whether the unique device identifier or the common device identifier matches a request specifying a device identifier, and only when either the unique device identifier or the common device identifier matches An information processing apparatus comprising means for responding to the request. 2. The information processing apparatus according to claim 1, wherein
The processing device includes means for logically disconnecting the processing device from the bus, and the processing device that holds a unique device identifier that matches the specified unique device identifier in response to a request specifying the unique device identifier An information processing apparatus comprising means for responding even when disconnected from the bus. 3. The information processing apparatus according to claim 2,
The information processing apparatus, wherein the request specifying the unique apparatus identifier is a request to refer to a specific register included in the processing apparatus. 4. The information processing apparatus according to claim 3, wherein
The processing device is provided with a means for connecting a processing device separated from the bus or a new processing device to the bus without stopping the operation of the information processing device, and the processing device transmits information to other processing devices. An information processing apparatus comprising the register of. 5. The information processing apparatus according to claim 3,
When a processing device separated from the bus or a new processing device is connected to the bus without stopping the operation of the information processing device, and the processing device has its own device newly connected to the bus In addition, by writing a value to a specific register of the own device, a value is reflected in a register of another operating processing device, and means for notifying the other processing device that the own device has been added is provided. An information processing device characterized by: 6. The information processing apparatus according to claim 3,
The processing device is provided with means for connecting a processing device separated from the bus or a new processing device to the bus without stopping the operation of the information processing device, and the processing device initializes when its own device is newly connected to the bus. When processing is completed,
An information processing apparatus, comprising means for notifying a processing device that is operating to notify that the initialization processing of the own device is completed by writing a value to a specific register of the own device. 7. The information processing apparatus according to claim 1, wherein
Means for referring to the processing device by designating the unique device identifier while the processing devices are simultaneously performing the same processing operation, and holding a unique device identifier that matches the unique device identifier designated for the reference Only the processing device responds, so that only the responding processing device performs a different operation from another processing device from a state in which the processing device simultaneously performs the same processing operation, and the processing device performs a different operation. An information processing apparatus comprising: means for disconnecting the processing device from the bus by performing the above.