JPH09311742A - Information processor and its hot-line inserting and extracting method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent defective access resulting from the insertion or extraction of a printed board by starting a timer from the start of access and latching an address signal and a data signal when an R/W signal is a write signal, and trying a dummy write access unless an ACK signal is received within a specified time. SOLUTION: When the R/W12 is write(W) and AS11 is L, the address and data of the write access cycle are latched and the timer is started. When the printed board 2 is removed from a system bus 10 before ACK becomes L, the AS11, R/W12, address 21, and data 22 are ceased on the system bus 10, so the printed board 2 considers that the access cycle has ended and ACK13 is not outputted. Consequently, when a time-out state is entered, dummy AS11 and R/W12 and then the latched address 21 and data 22 are outputted from the printed board 2 to the system bus 10 to make a dummy retrial.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a programmable controller, and more particularly to a hot-swapping method for a printed board.

[0002]

2. Description of the Related Art A conventional hot-swapping method for a printed circuit board is disclosed in JP-A-5-204507 and JP-A-6-168059, in which the length of a pin of a connector for connecting a printed board and a system bus is long. Is changed to detect the insertion / removal period. When the insertion / removal period is detected, the operation signal on the system bus is invalidated, the clock signal is switched or stopped, and the switch circuit is operated to control the operation signal on the system bus to realize hot-swap. Was.

[0003]

The above-described conventional hot-plugging / unplugging method is expensive because of the special connector structure. Also, since the printed circuit board to be inserted / removed is softly separated before insertion / removal, hot-line insertion / removal is performed, so if you accidentally insert / remove another printed circuit board, the access cycle will be interrupted and the system It may cause malfunction.

An object of the present invention is to provide a hot-swap method for detecting and backing up a defective access at the time of insertion and removal without using a special connector structure, and an information processing apparatus to which the method is applied.

[0005]

SUMMARY OF THE INVENTION The above-described object is to provide an information processing apparatus for connecting a plurality of printed boards equipped with electronic circuits such as processing means and storage means by a system bus and performing read / write access between the boards. In the hot-swap method of inserting and removing one of the printed boards being accessed, when the R / W signal is write (W), the timer is started from the access start, and the address signal and the data signal on the system bus are exchanged. This is achieved by performing a dummy retry of the write access when the ACK signal indicating the normal end of the access cycle is not received within a predetermined time from the start of access.

In the dummy retry, the address signal latched with the R / W signal is output onto the system bus at a first timing based on a time-out signal, and then latched at a second timing thereafter. An AS signal indicating the validity of the data signal and the address is output to the system bus.

An information processing apparatus to which the hot-swap method of the present invention is applied includes an unauthorized access detection circuit for monitoring access to another printed board on a predetermined printed board, and a dummy for retrying the access cycle when the unauthorized access is detected. It is realized by providing a hot-swap backup means which is a retry circuit.

The illegal access detection circuit takes in the R / W signal at the fall (valid) of the AS signal on the system bus, and if the R / W signal is read (R), it outputs the clear signal (from the Q-output). L) is output, and if it is a write (W), the clear signal is released (H), and a latchable signal (L) is output from the Q output.
It comprises a flip-flop that inverts the states of the Q and Q-outputs upon receiving a CK signal, and a timer that starts counting when the clear signal is released and outputs a time-out signal when a preset predetermined time elapses.

The dummy retry circuit latches an address signal or a data signal on the system bus by the latchable signal, and latches an address signal latched by a first timing signal by a second timing signal. An address latch circuit for outputting a data signal on the system bus and a data latch circuit, and a dummy R / W signal by receiving the time-out signal and generating the first timing signal.
Then, the second timing signal is generated to generate the dummy A
A timing generator is provided for outputting each S signal onto the system bus.

The hot-plugging / unplugging backup means is provided on a common board of the system, for example, on a printed board on which a CPU is mounted. Of course, a dedicated printed board may be provided.

When the printed board is inserted, the output end of the signal output on the system bus has a high impedance to prevent noise from being generated in the access cycle between other printed boards. .

According to the configuration of the present invention, the control signals (R / W, AS, ACK) on the system bus of the computer device or the like are monitored, and in particular, the printed board during the write access is removed, resulting in a defective access. To monitor. Further, the address and data at the time of write access are latched, and when the above defective access is detected, rewriting is performed to back up.

As a result, there is no possibility that wrong data will be written even if the access operation is halfway, and the malfunction of the system can be avoided. It should be noted that if the printed board is removed during the read access, the illegal data will not be accumulated, so the access is suspended.

Further, since it is not necessary to use a special connector, the cost of the hot-pluggable printed board can be reduced.

[0015]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a configuration diagram of a computer system to which the hot-swap method of the present invention is applied. The printed boards 1, 2, 3 are connected by a system bus 10. The printed board 1 includes a CPU (not shown) to control a common part of the system, and includes an unauthorized access detection circuit 101 and a dummy retry circuit 102 which realize the hot-swap backup means of the present invention.
The printed board 2 includes a DMA circuit 103, and the printed board 3 includes a memory 104. In the following, the printed board 2 is D
An example of performing read access or write access from the MA circuit 103 to the memory 104 of the printed board 3 will be described.

Access control signals AS11, R / W12
And ACK 13 are transmitted and received via the system bus 10. AS11 is a signal that is valid when L (low) and indicates that the printed board 2 is accessing the printed board 3 during an access cycle. R / W12 is H (high) for read access,
It is a signal indicating write access with L. ACK13 is a signal indicating that the read or write access cycle is normally completed, and is output when AS11 is L.

An address 21 indicates an address for accessing the printed board 3 from the printed board 2 and is effective when AS11 is L. The data 22 is read data of the memory 104 output from the printed board 3 during the read cycle, and write data to the memory 104 output from the printed board 2 during the write cycle.

FIG. 2 shows the detailed configurations of the unauthorized access detection circuit and the dummy retry circuit. The unauthorized access detection circuit 101 provided on the printed board 1 includes a flip-flop 5 that takes in the R / W 12 at the fall of AS11.
1, when AS11 = L is activated, the time-out circuit 5
A timer 52 which is cleared when the flip-flop 51ACK13 is activated and its output becomes Q- = L.
have.

The dummy retry circuit 102 has an R / W 12
Is a write cycle, the clear is canceled by the latch circuits 54 and 55 that latch the address 21 and the data 22 output on the system bus 10 when AS11 = L, and the timeout signal from the timer 52, and the dummy write is performed. It has a timing generator 53 that creates timing and outputs AS11 and R / W12 to the system bus 10 and outputs enable signals to the tristate gates 56 and 57 of the latch circuits 54 and 55.

The operation of this system will be described below with the printed board 2 as a hot-swap target. First, the printed board 2
From the printed board 2 during read access from the printed board 3
An example of hot-line removal will be described. The printed board 2 outputs the R / W 12 (= H) and the address 21 indicating the memory 104 of the printed board 3 onto the system bus 10. Next, AS1
1 (= L) is output to the system bus 10 and printed board 3
It waits for the data 22 and ACK13 output from the device.

At that time, the flip-flop 51 of the printed board 1 takes in the R / W signal 12 output from the printed board 2 at the fall of AS11. Since R / W12 = H (read), the output of the flip-flop 51 becomes Q- = L, and the clear signal is output to the timer 52, so that the timeout signal is not output. That is, the unauthorized access detection circuit 101 does not operate.

If the printed board 2 is removed from the system bus 10 during the read access, AS11, R / W1
2. The control signals of the address 21 disappear from the system bus 10 and the system bus 10 is not used. When the AS 11 disappears, the printed board 3 considers that the read cycle has ended, and interrupts the output of the data 22. At this time, since the ACK 13 is not output, the read cycle is aborted midway, but there is no problem because the printed board 2 which is the recipient of the read data is removed from the system bus 10.

Next, an example in which the printed board 2 is hot-plugged while the printed board 3 is write-accessed from the printed board 2 will be described. The printed board 2 is an R / W 12 on the system bus 10.
(= L), the address 21 indicating the memory 104 of the printed board 3, and the write data data 22 to the memory 104 are output. Then, AS11 (= L) is output onto the system bus 10 and the ACK 13 output from the printed board 3 is awaited.

The hot-swap backup means of the printed board 1 processes according to the flow shown in FIG. That is, when the R / W 12 is write (W) and the AS 11 is L, the address and data of the write access cycle are latched and the timer is started. After that, it is monitored whether ACK = L or time out. When ACK = L, the access cycle has ended normally, so the timer is reset and the operation of detecting unauthorized access is ended.

However, if the printed board 2 is removed from the system bus 10 before ACK = L, the AS 11, the R / W 12, the address 21 and the data 22 are lost from the system bus 10, so the printed board 3 is accessed. The cycle is considered to have ended, and ACK13 is not output. Therefore, when a time-out occurs, the dummy AS 11, R / W 12, and then the latched address 21 and data 22 are output from the printed board 1 to the system bus 10 and a dummy retry is performed.

Next, the operations of the unauthorized access detection circuit 101 and the dummy retry circuit 102 will be described in detail with reference to the time chart of FIG.

At the start of the write cycle, the flip-flop 51 in the illegal access detection circuit 101 takes in the R / W 12 output from the printed board 2 at the fall of AS11. Since R / W12 = L, the output Q− of the flip-flop 51 becomes H−, and the clear signal of the timer 52 is released to start counting. Further, since the output Q of the flip-flop 51 becomes L, the printed board 2 is connected to the system bus 10 in the latches 54 and 55 in the dummy retry circuit 102.
The address 21 and the data 22 output above are latched.

If the printed board 2 is removed from the system bus 10 before the ACK 13 is output from the printed board 3, there is no guarantee that the data written in the memory 104 of the printed board 3 is normal. At this time, since the flip-flop 51 in the unauthorized access detection circuit 101 is not reset, the timer 52 continues counting and outputs the timeout 31 (= H) after a fixed time.

When the time-out 31 is received, the timing generator 53 in the dummy retry circuit 102 is released from clearing, generates dummy write timing (enables 56 and 57), and outputs AS11 and R / W12 to the system bus 10. . Further, at the timing of the enable 56, the address 21 of the latch 54 and the enable 57
The data 22 of the latch 55 is output to the system bus 10 at the timing.

As a result, the data 22 is written in the address 21 of the memory 104 of the printed board 3. afterwards,
ACK13 indicating normal end of access from the printed board 3
Is returned, the unauthorized access detection circuit 101 and the dummy retry circuit 102 are reset and the operation ends.

According to the present embodiment, when the printed board 2 is being read-accessed from the printed board 3, the removal of the printed board 2 causes no problem because the access is interrupted. On the other hand, if the printed board 2 is removed during the write access from the printed board 2 to the printed board 3, illegal data may be stored in the printed board 3, but the write cycle is performed by the hot-swap backup means of the printed board 1. Since it acts on behalf of the user, illegal data is not stored in the printed board 3.

Further, when the printed board 2 is inserted, if the signal output on the system bus 10 is set to high impedance, noise due to the printed board 2 insertion may occur even during a read or write cycle between other printed boards. There is no effect.

FIG. 5 shows the configuration of a computer system according to another embodiment of the present invention. The difference from the configuration of FIG. 1 is that the printed board 1 is a dedicated board for hot-swap backup means,
The printed board 2 has a CPU 105. The operation of this system is such that the access of the DMA circuit 103 in FIG.
Detecting unauthorized access due to removal of the printed board 2 during write access, instead of access to the PU 105,
The dummy retry is performed similarly.

[0034]

According to the present invention, even if the printed board is inserted or removed during access, erroneous data is not written, and malfunction of the system can be avoided. Further, since it is not necessary to use a special connector, the cost of the hot-pluggable printed board can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a computer system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an unauthorized access detection circuit and a dummy retry circuit of hot-swap backup means.

FIG. 3 is a flowchart showing a processing procedure of hot-swap backup means.

FIG. 4 is a time chart showing the operation of hot-swap backup means.

FIG. 5 is a configuration diagram of a computer system according to another embodiment of the present invention.

[Explanation of symbols]

1, 2, 3 ... Printed board, 10 ... System bus, 11 ...
AS, 12 ... R / W, 13 ... ACK, 21 ... Address,
22 ... Data, 31 ... Timeout, 51 ... Flip-flop, 52 ... Timer, 53 ... Timing generator, 54, 55 ... Latch, 56, 57 ... Tristate gate, 101 ... Unauthorized access detection circuit, 102 ... Dummy retry circuit, 103 ... DMA circuit, 104 ... Memory, 105 ... CPU.

Claims (6)

[Claims] 1. An information processing apparatus for connecting a plurality of printed boards equipped with electronic circuits such as processing means and storage means via a system bus, and performing read / write access between the boards. In the hot-swap method of inserting and removing the board, when the R / W signal is write (W), the timer is started from the access start, and the address signal and the data signal on the system bus are latched for a predetermined time from the access start. A hot-swap method, wherein a dummy retry of the write access is performed when an ACK signal indicating the normal end of the access cycle cannot be received. 2. The dummy retry according to claim 1, wherein the dummy retry is based on a time-out signal.
The R / W signal and the latched address signal are output onto the system bus at the timing of, and the latched data signal and the AS signal indicating the validity of the address at the second timing thereafter are transmitted to the system. A hot-plug method that outputs on the bus. 3. An information processing apparatus for connecting a plurality of printed boards equipped with electronic circuits such as a processing means and a storage means by a system bus to perform read / write access between the boards. An information processing apparatus comprising: a hot-swap backup means including an unauthorized access detection circuit for monitoring access to a printed board and a dummy retry circuit for retrying the access cycle when an unauthorized access is detected. 4. The unauthorized access detection circuit according to claim 3, wherein the unauthorized access detection circuit is A on the system bus.
R / W signal is taken in at the falling edge (valid) of S signal and R
If the / W signal is a read (R), the clear signal (L) is output from the Q- output, and if the / W signal is a write (W), the clear signal is released (H) and the latchable signal (L) is output from the Q output. , And a flip-flop that inverts the states of the Q and Q-outputs upon reception of an ACK signal on the system bus, and counting is started by releasing the clear signal, and a timeout occurs when a preset predetermined time elapses. The dummy retry circuit latches an address signal or a data signal on the system bus according to the latchable signal and a latching address signal according to a second timing signal. Address latch circuit and data for outputting the data signal latched by the timing signal of the above to the system bus A latch circuit required, and the time-out signal is received to generate the first timing signal to generate a dummy R / W signal, and then the second timing signal is generated to generate a dummy AS signal, respectively. An information processing apparatus having a timing generator for outputting on a bus. 5. The information processing device according to claim 3, wherein the hot-swap backup means is provided on a printed board that is a common part of the system. 6. The information processing apparatus according to claim 3, 4 or 5, wherein the printed board is configured such that, when the printed board is inserted, an output end of a signal output onto the system bus has a high impedance.