JPH09311666A - Gradation voltage generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accomplish a simple-structured gradation voltage generating circuit by means of a small number of parts. SOLUTION: The gradation voltage generating circuit is provided with the first - the (n)th resistance elements 41-44, whose one ends are connected to the first electric potential, and the first - the (n)th switch elements 45-48 connecting the other ends of the first - the (n)th resistance elements 41-44 to one end of the (n+1)th element 49. Weighting of respective values in the (n+1)th resistance element 49 is carried out, while the other end of the (n+1)th resistance element 49 is connected to the second electric potential, and an output voltage is taken out from one end of the (n+1)th resistance element 49. According to a combination of turning on/off of the first - the (n)th switch elements 45-48, a resistance dividing ratio between the first - the (n)th resistance elements 41-44 and the (n+1)th resistance element 49 is varied, so that a gradient voltage, in which a voltage difference between the first electric potential and the second electric potential is divided by the resistance dividing ratio, can be provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a grayscale voltage generation circuit, and more particularly to a grayscale voltage generation circuit of a liquid crystal display device for displaying bright and dark grayscales according to a digital input signal, and more particularly to reduction of the number of parts. And a gradation voltage generating circuit intended to simplify the configuration. In general, a liquid crystal display in which a voltage (hereinafter referred to as “liquid crystal voltage”) is applied to a liquid crystal sandwiched between two glass substrates to change the alignment (light transmittance) of the liquid crystal to obtain a desired display gradation. The device uses an "analog method" in which an analog input signal is directly amplified and used for liquid crystal voltage, and a digital input signal is decoded, and the grayscale voltage generated inside the device is selectively selected according to the decoding result. It is roughly classified into the "digital system" to be used, and in particular, the latter digital system occupies the mainstream of applications requiring high image quality.

Here, when the number of bits of the digital input signal is "n", the number of gray scales that can be displayed is 2 ⁿ , and for example, with 4 bits, 2 ⁴ = 16 gray scales. Similarly, the gray scale voltage is 2 ^{n because} it is necessary for each gray scale. However, the number (type) of gray scale voltages and the scale of the gray scale voltage generation circuit are in a proportional relationship, and as the circuit scale increases, the cost and the yield decrease, so that further multi-gradation display is realized. In addition, there is a demand for a grayscale voltage generation circuit having a small number of components and a simple structure.

[0003]

2. Description of the Related Art FIG. 10 shows 16 types (types are convenience examples).
Gradation voltage V₁ ~ V₁₆Conventional grayscale voltage generation circuit for generating
It is a block diagram of. This circuit has a 4-bit digital input.
Force signal B₁ ~ B_Four 16 according to the combination of logic
Output D₁ ~ D₁₆1 to activate one of the
And the active output of this decoder 1
16 switch elements 2 to 17 that are turned on and the high potential side
Connect in series between the power supply VDD and the low potential power supply VSS.
VDD-V provided with 17 resistance elements 18 to 34
The potential difference between SS is divided by 17 resistance elements 18-34.
16 gradation voltages V₁ ~ V₁₆To generate
One voltage of the digital input signal B₁ ~ B _Four The logic of
Select according to the combination, liquid crystal voltage V_OUT As a figure
Output to the data bus line of the LCD panel not shown.
You.

It should be noted that the number of the resistance elements 18 to 34 is decreased by _{one by 16} if V ₁ = VDD or VSS = V ₁₆ , or V ₁ = VDD and V ₁₆ = VS.
If it is S, it will be 15 less by 2 less.

[0005]

However, in such a conventional gradation voltage generating circuit, at least 2 ⁿ -1 is required.
Resistance elements 18 to 34 and 2 ⁿ switch elements 2 to
Since 17 and one decoder 1 are required, even if the number of bits of the digital input signal is increased by 1 bit at most, the number of components is almost doubled. It is insufficient in terms of realizing the generation circuit, and there is a technical problem to be solved here.

Therefore, an object of the present invention is to provide a useful technique for realizing a simple gray scale voltage generating circuit with a small number of parts, thereby contributing to a higher gray scale.

[0007]

[Means for Solving the Problems]

(Structure) The invention according to claim 1 is characterized in that the first to nth resistance elements having one ends connected to the first potential and the first to nth selection patterns are selected in accordance with a combination of logics of digital input signals. A first to an n-th switch element connecting between the other end of the resistance element and one end of the (n + 1) th resistance element, and weighting the respective values of the (n + 1) th resistance element, The other end of the resistance element is connected to the second potential, and the output voltage is taken out from one end of the (n + 1) th resistance element.

According to a second aspect of the invention, the first to nth MOs are provided.
One of two electrodes, excluding the gate electrode, of the source electrode, the drain electrode, and the gate electrode of the S transistor is connected to a first potential, and each bit of the digital input signal is applied to each gate electrode, and the first electrode is connected to the first electrode. ~ The nth M
Each L / W of the OS transistor is weighted, the other of the two electrodes is connected to the second potential via a resistance element, and the output voltage is taken out from the other of the two electrodes.

According to a third aspect of the invention, the first to nth MOs are provided.
Of the source electrode, the drain electrode, and the gate electrode of the S transistor group, one of two electrodes excluding the gate electrode is first
Of the digital input signal to each of the gate electrodes, weighting the number of each MOS transistor forming the first to n-th MOS transistor groups, the other of the two electrodes. Is connected to a second potential via a resistance element, and the output voltage is taken out from the other of the two electrodes.

According to a fourth aspect of the invention, in the third aspect of the invention, the resistance element is constituted by a MOS transistor, and a gate voltage varying means for varying the gate voltage of the MOS transistor is provided. To do. Claim 5
According to the invention described in claim 1, 2, 3 or 4, a switch element is inserted in series with the (n + 1) th resistance element or the resistance element. (Operation) In the invention according to claim 1, the resistance voltage dividing ratios of the first to nth resistance elements and the (n + 1) th resistance element change in accordance with the on / off combinations of the first to nth switch elements, An output voltage (gradation voltage) is obtained by dividing the potential difference between the first potential and the second potential by this voltage division ratio.

According to a second aspect of the invention, the first to nth M's
The resistance voltage division ratio between the channel on-resistances of the first to n-th MOS transistors and the resistance element changes according to the combination of ON / OFF of the OS transistor, and the potential difference between the first potential and the second potential is calculated by the voltage division ratio. An output voltage (gradation voltage) divided by is obtained. In the invention of claim 3, the first to nth
The resistance division ratio between the channel on resistance and the resistance element of the first to n-th MOS transistor groups changes according to the combination of ON and OFF of the MOS transistor group of, and the potential difference between the first potential and the second potential is An output voltage (gradation voltage) divided by this division ratio is obtained.

According to the fourth aspect of the present invention, the resistance voltage dividing ratio can be finely adjusted by changing the gate voltage of the MOS transistor functioning as a resistance element. In the invention according to claim 5, by turning off the switch element, a through current flowing between the first potential and the second potential is blocked, and power consumption is suppressed.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are diagrams showing a first embodiment of a gradation voltage generating circuit according to the present invention. In each of the following examples including this example, an example of application to a liquid crystal display device with 16 gradations is shown, but this is for convenience of description and is not limited to this number of gradations. .

First, the structure will be described. In FIG. 1, V
DD is a power source on the high potential side. First value with different value for VDD
~ Each one end of the fourth resistance elements 41 to 44 is connected, and each other end of the first to fourth resistance elements 41 to 44 is connected to one end of each of the first to fourth switch elements 45 to 48. It is connected. The first to fourth switch elements 45 to 48 are
It corresponds to each bit B _{1 to} B ₄ of the 4-bit digital input signal, is turned on when the corresponding bit has a predetermined logic (for example, “1” logic), and is connected to one end side of a resistance element (for example, In the case of the first switch element 45, the first resistance element 41) is connected to the low potential power supply VSS via the fifth resistance element 49. The VD in this specification
D and VSS are not necessarily limited to the power supply voltage. It is only necessary to have two stable potentials.

Here, the first to fourth resistance elements 41 to 44 are provided.
For the sake of convenience, each resistance value of
4), the following relationships are given between these resistance values 41 to 44. 41 <42 41 + 42 <43 41 + 42 + 43 <44 To satisfy this relationship, for example, the following weighted values can be given.

41 = 1R 42 = 2R 43 = 4R 44 = 8R However, R is an arbitrary resistance value. In such a configuration, the combination of the logic of the 4-bit digital input signals B _{1 to} B ₄ and the switch element 45.
The relationship between ON and OFF of 48 is summarized as in Table 1 below. (Below margin)

[0017] However, ● indicates on and ○ indicates off.

Here, how the value of the liquid crystal voltage V _OUT taken out from both ends of the fifth resistance element 49 changes by turning on / off each of the switch elements 45 to 48 will be verified. However, VSS is 0V, and the resistance value of the fifth resistance element 49 is “1R”. First, when all of B _{1 to} B ₄ are logic “0”, all the switch elements 45 to 48 are turned off, so that the liquid crystal voltage V _OUT becomes 0 V. For example, only B ₁ is logic “1”. ", Only the first switch element 45 is turned on, and the fifth resistance element 49 having a resistance value of 1R is connected in series between VDD and VSS in the same manner as the first resistance element 41 having a resistance value of 1R. Therefore, the liquid crystal voltage V _OUT
Is the potential difference of VDD-VSS divided by the ratio of these two resistance values, and is given by VDD / 2.

Alternatively, if only B ₂ is a logic "1", only the second switch element 46 is turned on, and the second resistance element 42 having the resistance value 2R and the resistance value 1R having the resistance value 2R are connected between VDD and VSS. Since the fifth resistance element 49 is connected in series, the liquid crystal voltage V _OUT is given by VDD / 3. Alternatively, if only B ₃ is a logic “1”, only the third switch element 47 is turned on, and the third resistance element 43 having the resistance value 4R and the fifth resistance element 1R having the resistance value 4R are provided between VDD and VSS. Since the resistance element 49 is connected in series, the liquid crystal voltage V _OUT is given by VDD / 5.

Alternatively, if only B ₄ is a logic "1", only the fourth switch element 48 is turned on, and between the fourth resistance element 44 having a resistance value 8R and the resistance value 1R between VDD and VSS. Since the fifth resistance element 49 is connected in series, the liquid crystal voltage V _OUT is given by VDD / 9. That is, when only one bit has a predetermined logic, "VDD / 2", "VDD / 3", "VDD /" depending on the bit position.
Four types of liquid crystal voltage V _{OUT of} “5” or “VDD / 9” will be generated.

On the other hand, when a plurality of bits have a predetermined logic, the same number of switch elements corresponding to the bit positions are turned on, and the "parallel combination of the first to fourth resistance elements 41 to 44 is selectively performed. "Value" is obtained, and the value of the liquid crystal voltage V _OUT is determined by the resistance voltage division between the parallel combined value and the resistance value (1R) of the fifth resistance element 49. The parallel combined values are as follows. First, when both B ₁ and B ₂ are logic “1”, two of the first switch element 45 and the second switch element 46 are turned on, and the resistance value 1R of the first resistance element 41 and the second resistance element 41 The parallel combined value (* R ₁ ) of the resistance values 2R of the element 42 is obtained.

* R ₁ = 1 / [(1 / 1R) + (1/2
R)] ≈0.666R or when B ₁ and B ₃ are logic “1”, two of the first switch element 45 and the third switch element 47 are turned on,
The resistance value 1R of the first resistance element 41 and the third resistance element 43
The parallel combined value (* R ₂ ) of the resistance values 4R of 4 is obtained. * R ₂ = 1 / [(1 / 1R) + (1 / 4R)] = 0.8
When R ₂ or B ₂ and B ₃ become logic "1", two of the second switch element 46 and the third switch element 47 are turned on,
The resistance value 2R of the second resistance element 42 and the third resistance element 43
The parallel combined value (* R ₃ ) of the resistance values 4R of 4 is obtained.

* R ₃ = 1 / [(1 / 2R) + (1/4
R)] ≈1.333R or when B ₁ , B ₂ and B ₃ become a logical “1”, _three of the first switch element 45, the second switch element 46 and the third switch element 47 are turned on. , The resistance value 1R of the first resistance element 41, the resistance value 2R of the second resistance element 42, and the resistance value 4R of the third resistance element 43 are obtained in parallel (* R ₄ ).

* R ₄ = 1 / [(1 / 1R) + (1/2
R) + (1 / 4R)] ≈0.571R or when B ₁ and B ₄ are logic “1”, two of the first switch element 45 and the fourth switch element 48 are turned on,
The resistance value 1R of the first resistance element 41 and the fourth resistance element 44
A parallel composite value (* R ₅ ) of the resistance value 8R of is obtained.

* R ₅ = 1 / [(1 / 1R) + (1/8
R)] ≈0.888R or when B ₂ and B ₄ are logic “1”, two of the second switch element 46 and the fourth switch element 48 are turned on,
The resistance value 2R of the second resistance element 42 and the fourth resistance element 44
A parallel composite value (* R ₆ ) of the resistance value 8R of is obtained. * R ₆ = 1 / [(1 / 2R) + (1 / 8R)] = 1.6
When R ₁ or B ₁ , B ₂ and B ₄ becomes logic “1”, three of the first switch element 45, the second switch element 46 and the fourth switch element 48 are turned on, and the first resistance element A parallel combined value (* R ₇ ) of the resistance value 1R of 41, the resistance value 2R of the second resistance element 42, and the resistance value 8R of the fourth resistance element 44 is obtained.

* R ₇ = 1 / [(1 / 1R) + (1/2
R) + (1 / 8R)] ≈0.615R or when B ₃ and B ₄ are logic “1”, two of the third switch element 47 and the fourth switch element 48 are turned on,
The resistance value 4R of the third resistance element 43 and the fourth resistance element 44
A parallel combined value (* R ₈ ) of the resistance value 8R of is obtained.

* R ₈ = 1 / [(1 / 4R) + (1/8
R)] ≈2.666R or when B ₁ , B ₃ and B ₄ become logic “1”, three of the first switch element 45, the third switch element 47 and the fourth switch element 48 are turned on. , A parallel combined value (* R ₉ ) of the resistance value 1R of the first resistance element 41, the resistance value 4R of the third resistance element 43, and the resistance value 8R of the fourth resistance element 44 is obtained.

* R ₉ = 1 / [(1 / 1R) + (1/4
R) + (1 / 8R)] ≈0.727R or when B ₂ and B ₃ and B ₄ are logic “1”, the second switch element 46, the third switch element 47, and the fourth switch element Three of 48 are turned on, and a parallel combined value (* R ₁₀ ) of the resistance value 2R of the second resistance element 42, the resistance value 4R of the third resistance element 43 and the resistance value 8R of the fourth resistance element 44 is obtained. To be

* R ₁₀ = 1 / [(1 / 2R) + (1/4
R) + (1 / 8R)] ≈1.143R or when all bits (B _{1 to} B ₄ ) become logic “1”, all of the first to fourth switch elements 45 to 48 are turned on, The parallel combined value of the resistance value 1R of the first resistance element 41, the resistance value 2R of the second resistance element 42, the resistance value 4R of the third resistance element 43, and the resistance value 8R of the fourth resistance element 44 (*
R ₁₁ ) is obtained.

* R ₁₁ = 1 / [(1 / 1R) + (1/2
R) + (1 / 4R) + (1 / 8R)] ≈0.533R Here, each resistance value (1R to 8R) of each of the first to fourth resistance elements 41 to 44 and each combined resistance value ( * R ₁ ~ *
When the magnitude relationship of R ₁₁ ) is shown in ascending order, the order is shown in Table 2 below. (Below margin)

[0031] Rearranging Table 1 in this order gives Table 3 below. (Below margin)

[0032]In Table 3, the weight of each bit is B_Four = 2¹ , B_Three =
2^Two , B_Two = 2^Three , B ₁ = 2^Four It is. For example, B_Four ~
B₁ Is an all-logical "1" (15 in decimal notation_{(1 0)})
Then, the resistance value becomes the minimum and the maximum liquid crystal voltage V_OUT (=
V_Fifteen) Can be taken out. Or B_Four ~ B₁ The
Logic “0” (0 in decimal notation_(Ten)), The maximum
The minimum liquid crystal voltage V_OUT (= V₀ )
You can get out. Then, the area (0
_(Ten)Beyond and 15_(Ten)Area less than)_Four ~ B₁ 
1 according to the combination pattern of_(Ten)~ 14_(Ten)Liquid
Crystal voltage V_OUT (= V₁ ~ V₁₄) Can be taken out
So, after all, 0_(Ten)~ 15_{(1 0)}Up to 16 types of LCD
Pressure V_OUT (= V₀ ~ V_Fifteen) Can be generated
One of the voltages is the digital input signal B_Four ~ B₁ In response
Can be selected.

Therefore, according to the configuration of FIG. 1, only a very simple circuit configuration including five resistance elements 41, 42, 43, 44 and 49 and four switch elements 45, 46, 47 and 48 is provided. Can generate 16 types of gradation voltages (V _{0 to} V ₁₅ ), and one of the voltages can be selected in accordance with a 4-bit digital input signal, so that the number of parts can be reduced and the configuration can be reduced. It is possible to achieve simplification, and it is possible to obtain a particularly advantageous effect that it is possible to deal with multiple gradations without inviting an increase in cost and a decrease in yield.

FIG. 2 is an overall configuration diagram of a preferred liquid crystal display device to which the above embodiment is applied. In particular, a type in which peripheral circuits such as a data driver 50 and a gate driver 51 are integrated with a liquid crystal display panel 52. LCD device (common name:
It is a figure which shows a peripheral circuit integrated type panel. In this figure, the control circuit 53 for controlling the peripheral circuits is provided outside the panel 54, but the control circuit 53 may be integrated.

The configuration of the above embodiment is based on the data driver 5
Applies to 0. Specifically, it is applied to the voltage selectors 55 ₁ , 55 ₂ , ... Which are provided inside the data driver 50. In FIG. 3, the data driver 50 is
During one horizontal scanning period, 4-bit digital display signals D _{1 to} D are synchronized with the pixel clocks φ ₁ and φ _2.
4 latches and latches 56 composed of a large number of flip-flops that output the latched data at the timing of the signal L generated slightly later than the horizontal scanning signal, and the digital data B ₁ to One of 16 kinds of gradation voltages is selected according to B _4, and the data bus lines 56 ₁ , 56 ₂ , ... of the liquid crystal display panel 52 are selected.
Voltage selectors to be applied to the voltage selectors 55 ₁ , 55 ₂ ,
By applying the above-described embodiment, it is possible to achieve “reduction of the number of parts” and “simplification of the configuration” of the voltage selectors 55 ₁ , 55 ₂ ,. The ripple effect that the yield of the integrated panel can be improved can be obtained. That is, in the type in which the peripheral circuit and the liquid crystal panel are not integrated, since the driver IC is incorporated separately, if the voltage selector is defective, only the driver IC needs to be replaced, which does not affect the yield of the liquid crystal panel. This is because in the peripheral circuit integrated type, if a defect occurs in the voltage selector, the entire liquid crystal panel must be discarded.

Therefore, as shown in FIG.
According to the liquid crystal display device of FIG. 3, the voltage selector few simple configuration of parts 55 _1, 55 _2, because it is possible to ........., voltage selectors 55 _1, 55 _2, the defective ......... It is possible to obtain the advantageous effect that it can be reduced and the yield of the peripheral circuit integrated type panel can be significantly improved.

Next, the gradation voltage output characteristic of the above embodiment will be described. FIG. 5 shows the first to fourth switch elements 45 to
Each of the resistance values obtained with a combination of 48 on-off (1R, 2R, 4R, 8R , * R 1 ~ * R 11) is a graph plotting. The vertical axis represents the resistance value and the horizontal axis represents the order (see Table 2). According to this graph, the minimum resistance value (*
A characteristic line 57 of resistance value which changes "non-linearly" from R ₁₁ ) to the maximum resistance value (8R) is observed.

As described above, 16 kinds of gradation voltages V ₀
~ V ₁₅ are those resistance values (1R, 2R, 4R, 8R,
* R ₁ to * R ₁₁ ) and the resistance value of the fifth resistance element 49. Assuming that the resistance value of the fifth resistance element 49 is “1R” as in the above assumption, the characteristic line 58 of the gradation voltages V _{0 to} V ₁₅ is the characteristic line 5 in the graph.
The shape of 7 is inverted. That is, when the minimum resistance value (* R ₁₁ ) is the maximum gradation voltage (V ₁₅ ), the maximum resistance value (8R in the figure) is the minimum gradation voltage (V _{1 in the} figure), and in between. A large number of gradation voltages that change non-linearly can be obtained.

The gradation voltages V _{0 to} V ₁₅ of this embodiment having such non-linear characteristics are advantageous in that the display characteristics of the liquid crystal panel can be corrected (so-called gamma: γ correction) without providing a special circuit. Is. FIG. 4 is a diagram showing a display characteristic (TV characteristic) of the liquid crystal panel. The vertical axis represents the liquid crystal transmittance (T), and the horizontal axis represents the liquid crystal voltage (V). The display characteristics of the liquid crystal panel are non-linear unlike the cathode ray tube type display device, and its use area is T = A · V ^* (A is a constant, * is γ
It is the range where the relationship of (value) is established.

According to this TV characteristic, the liquid crystal voltage (V)
The change in the transmittance (T) is small in the area A where the liquid crystal voltage (V) is low, and the change in the transmittance (T) is large in the area B where the liquid crystal voltage (V) is high. It has the undesired characteristic of being difficult to display. In order to eliminate such a defect, it is effective to increase the change of the gradation voltage (V) in the area A. That is, the slope on the V ₀ side may be made steep as indicated by the characteristic line 58 in FIG. In this case, for example, the potential difference between V ₁ and V ₂ becomes larger than the potential difference between V ₁₅ and V ₁₄ , so that the change in the gradation voltage (A) in the area A is increased to the same value. An advantageous effect that a subtle gradation difference in the area A can be displayed is obtained. Moreover, since such a correction operation can be achieved without providing a special circuit, it does not hinder the subject of the present invention of simplifying the circuit configuration.

The scope of the present invention is disclosed in the above embodiment.
It is not limited to what was done. For example, as shown in FIG.
First to fourth resistance elements and first to fourth switch elements are first
~ Realization with fourth MOS transistors 60-63
Can be. That is, the first to the fourth with different L / W
Connect the drains of MOS transistors 60-63 to VDD
4 bit digital input signal B to each gate₁ ~
B _Four And each source with a resistive element 64
It may be configured to be connected to VSS via.

Here, W is the channel width of the MOS transistor, and L is the channel length. W of the first MOS transistor 60 is “W ₆₀ ”, L is “L ₆₀ ”, and W of the second MOS transistor 61. “W ₆₁ ”, L is “L ₆₁ ”, W of the third MOS transistor 62 is “W ₆₂ ”, L is “L ₆₂ ”, W of the fourth MOS transistor 63 is “W ₆₃ ”, L is Given that “L ₆₃ ”, the following relationships are given to these parameters.

L ₆₀ / W ₆₀ <L ₆₁ / W ₆₁ L ₆₀ / W ₆₀ + L ₆₁ / W ₆₁ <L ₆₂ / W ₆₂ L ₆₀ / W ₆₀ + L ₆₁ / W ₆₁ + L ₆₂ / W ₆₂ <L ₆₃ / W
₆₃ To satisfy this relationship, for example, the following weighted values can be given: L ₆₀ / W ₆₀ = 1R L ₆₁ / W ₆₁ = 2R L ₆₂ / W ₆₂ = 4R L ₆₃ / W ₆₃ = 8R Since this weighting is the same as that in the above-mentioned embodiment, the same effect can be obtained, and further, in this example,
Since the functions of the resistance element and the switch element can be realized by the MOS transistor, there is an advantageous effect that the number of parts can be further reduced and the configuration can be simplified.
In addition, in FIG. 6, the fifth resistance element 64 may of course be formed of a MOS transistor.

Alternatively, as shown in FIG. 7, a large number of MOS transistors 70 to 84 having the same L / W can be used. That is, one MOS transistor 70 constitutes a first MOS transistor group 71, and two MOS transistors 70
The transistors 72 and 73 form a second MOS transistor group 74, the four MOS transistors 75 to 78 form a third MOS transistor group 79, and
The fourth MOS transistor group 88 may be composed of the individual MOS transistors 80 to 87. Reference numeral 89 is a MOS transistor as a fifth resistance element.

In such a configuration, the resistance value of the first MOS transistor group 71 is given by the channel ON resistance (R ₇₀ ) of one MOS transistor 70, and the resistance value of the second M transistor 70 is given.
The resistance value of the OS transistor group 74 is given by the channel on resistance (R ₇₂ + R ₇₃ ) of the two MOS transistors 72 and 73, and the resistance value of the third MOS transistor group 79 is that of the four MOS transistors 75 to 78. Channel ON resistance (R ₇₅ + R ₇₆ + R ₇₇ + R ₇₈ ), and the resistance value of the fourth MOS transistor group 88 is 8 MOS.
Channel on resistance of transistors 80-87 (R ₈₀ + R
₈₁ + R ₈₂ + ... ...... R ₈₆ + R ₈₇ ), and the channel on-resistances of all MOS transistors are equal (R ₇₀ = R ₇₂ = R ₇₃ = ... ...... R ₈₆ = R ₈₇ ). R ₇₀ = 1R R ₇₂ + R ₇₃ = 2R R ₇₅ + R ₇₆ + R ₇₇ + R ₇₈ = 4R R ₈₀ + R ₈₁ + R ₈₂ + ... R ₈₆ + R ₈₇ = 8R can be satisfied.

Note that FIG. 7 may be modified as shown in FIG. That is, the gate voltage varying means 90 (typically a variable resistor) for varying the gate voltage V _REF of the MOS transistor 89 as the fifth resistance element may be provided. By doing so, a combination (or single) of the first to fourth MOS transistor groups 71, 74, 79, 88
And the resistance division ratio with the fifth resistance element (MOS transistor 89) can be finely adjusted, and the output characteristic of the gradation voltage can be changed to some extent, which is preferable.
The following formula is a formula of the drain current I _D which is closely related to the channel on resistance (R _ON ) of the MOS transistor.

[0047] _{I D = β {(V GS} -V T) V DS - (V DS 2/2)} where, beta: As can be understood from the transistor gain factor This equation, closely related to the channel on-resistance A certain drain current I _D is affected by the gate-source voltage V _GS and the drain-source voltage V _DS of the MOS transistor, but the effects of both are not the same. FIG.
At V _REF , the fifth resistance element (M
Channel on-resistance of OS transistor 89) "changes"
However, in accordance with this change, the voltages across the first to fourth MOS transistor groups 71 to 88 (that is, V _DS ) also “change”.
I do. Assuming that the effects of V _GS and V _DS on I _D are the same, the two changes are exactly the same and the resistance voltage dividing ratio does not change at all, but from the above equation, the effects of V _GS and V _DS on I _D are Since they are unequal, there is a subtle difference between the two changes, and this difference allows the resistance division ratio to be finely adjusted.

This will be specifically verified. First, the fifth
The drain current of the resistance element (MOS transistor 89) of I _D1 , the first to fourth MOS transistor groups 71 to 88
If the drain current of each is I _D2 , these drain currents I _D1 and I _D2 are expressed by the following equations. However, V _REF is the gate voltage of the fifth resistance element (MOS transistor 89), V
_DA is the gate voltage of the first to fourth MOS transistor groups 71 to 88, and V _T is the threshold voltage of the MOS transistors.

[0049] _{I D1 = β {(nV REF} -V T) V OUT - (V OUT 2/2)} I D2 = β {(V DA -V OUT -V T) · (VDD-V OUT)
- when the potential of the ^{_{[(VDD-V OUT) 2/}} 2 ]} V _OUT is stable (that is, when the charging of the load capacitor has been completed), from becomes I _D1 = I _D2, the above two equations, It can be solved as follows. In the following, for simplification of calculation, the first
The number of transistors in the fourth MOS transistor groups 71 to 88 is one.

Β {(nV _REF −V _T ) V _OUT − (V _OUT
^{2/2) = β {(} V DA -V OUT -V T) · (VDD-
V _OUT) - ^{_{[(VDD-V OUT) 2/}} 2 _{]} (nV REF -V T) V} OUT - (1/2) V OUT 2 = V DA
VDD-VDD V _OUT -V _T VDD-V _DA V _OUT + V _OUT ²
+ V _T V _OUT − (1/2) VDD ² + VDDV _OUT − (1 /
2) V _OUT ² V _OUT ² + (V _T + VDD−V _DA −VDD + V _T −nV
_REF ) ・ V _OUT + {V _DA VDD−V _T VDD− (1/2)
VDD ² } V _OUT ² + (2V _T −V _DA −nV _REF ) V _OUT + V _DA V
DD-V _T VDD- (1/2) VDD ² V _OUT = {-(2V _T -V _DA -nV _REF ) ± √X} /
2 However, X = (2V _T −V _DA −nV _REF ) ² −4 (V _DA VD
D−V _T VDD− (1/2) VDD ² ) That is, from the expressions (1) to ( ⁵ ), since V _OUT changes according to the multiple n of V _REF , the gate voltage V _{REF of} the fifth resistance element (MOS transistor 89) By adjusting, the resistance voltage dividing ratio can be finely adjusted.

Alternatively, as shown in FIG. 9, a fifth switch element 92 may be inserted in series with the fifth resistance element, or further,
The gradation voltage V _OUT may be taken out via the sixth switch element 93. By doing so, the fifth and sixth switch elements 92, 93 can be turned off in synchronization with the predetermined timing signals Sa, Sb, and a shoot-through current flowing from VDD to VSS or a load (mainly from VDD). It is preferable because a through current flowing to the parasitic capacitance of the data bus line) can be blocked and power consumption can be suppressed.

The fifth switch element 92 may also be used as the fifth resistance element (MOS transistor 89), or only one of the fifth switch element 92 and the sixth switch element 93 is provided. You may do it.

[0053]

According to the first aspect of the present invention, 2 ⁿ kinds of gray scale voltages can be generated with an extremely simple structure of only n switch elements and n + 1 resistance elements. According to the second aspect of the present invention, 2 ⁿ kinds of gray scale voltages can be generated with a very simple configuration including only n MOS transistors and one resistance element.

According to the invention described in claim 3, more MOS transistors are required than in the invention described in claim 2, but the MOS transistors of the same size are sufficient.
The design and manufacturing process can be facilitated. According to the invention described in claim 4, the output characteristics of 2 ⁿ kinds of gradation voltages can be finely adjusted.

According to the fifth aspect of the invention, it is possible to prevent a through current between the first potential and the second potential and suppress power consumption.

[Brief description of drawings]

FIG. 1 is a configuration diagram of one embodiment.

FIG. 2 is a schematic configuration diagram of a preferable peripheral circuit integrated panel to which an embodiment is applied.

FIG. 3 is a main part configuration diagram of a data driver of a peripheral circuit integrated type panel.

FIG. 4 is a TV characteristic diagram of a liquid crystal panel.

FIG. 5 is a resistance value characteristic and an output voltage characteristic diagram of an example.

FIG. 6 is a modified configuration diagram (1) of the embodiment.

FIG. 7 is a modified configuration diagram (2) of the embodiment.

FIG. 8 is a modified configuration diagram (3) of the embodiment.

FIG. 9 is a modified configuration diagram (4) of the embodiment.

FIG. 10 is a configuration diagram of a conventional example.

[Explanation of symbols]

B _{1 to} B ₄ : Digital input signal VDD: First potential VSS: Second potential V _OUT : Output voltage 41 to 44: First to fourth resistance elements (first to nth resistance elements) 45 to 48: 1st-4th switch element (1st-nth switch element) 49: 5th resistance element (n + 1th resistance element) 60-63: 1st-4th MOS transistor (1st-first)
Nth MOS transistor) 64: resistance element 71: first MOS transistor group (first MOS transistor group) 74: second resistance element (second MOS transistor group) 79: third resistance element (third resistance element) No. 3 MOS transistor group) 88: Fourth resistance element (nth MOS transistor group) 89: MOS transistor (resistance element) 90: Gate voltage varying means 92: MOS transistor (switch element)

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Akira Yamamoto 4-1-1 Uedanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Mitsuharu Nakazawa 4-1-1 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 Inside Fujitsu Limited

Claims (5)

[Claims] 1. A first to nth resistance element whose one end is connected to a first potential, and the other end of each of the first to nth resistance elements in a selection pattern according to a combination of logics of digital input signals. And n + 1
A first to n-th switch element connected to one end of the resistance element of the first resistance element, weighting respective values of the n + 1th resistance element, and a second end of the n + 1th resistance element to the second end. A gray-scale voltage generating circuit, which is connected to the electric potential of the output terminal and outputs an output voltage from one end of the n + 1th resistance element. 2. One of two source electrodes, drain electrodes and gate electrodes of the first to nth MOS transistors except the gate electrode is connected to a first potential, and a digital input signal is applied to each gate electrode. Of each of the first to n-th MOS transistors.
A gray scale voltage generation circuit, wherein W is weighted, the other of the two electrodes is connected to a second potential via a resistance element, and an output voltage is taken out from the other of the two electrodes. 3. A source electrode, a drain electrode, and a gate electrode of the first to n-th MOS transistor groups, one of two electrodes excluding the gate electrode is connected to a first potential, and a digital input is made to each gate electrode. Each bit of the signal is applied, the number of each MOS transistor forming the first to nth MOS transistor groups is weighted, and the other of the two electrodes is connected to the second potential via a resistance element. A gradation voltage generating circuit, wherein an output voltage is taken out from the other of the two electrodes. 4. The gradation voltage generating circuit according to claim 3, wherein the resistance element is composed of a MOS transistor, and a gate voltage varying means for varying the gate voltage of the MOS transistor is provided. 5. The gradation voltage generating circuit according to claim 1, wherein a switch element is inserted in series with the (n + 1) th resistance element or the resistance element.