JPH09307759A - Error storage control method for image processing unit and error storage controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make the memory size of an error signal storage means small and to reduce the cost of the means. SOLUTION: An image signal correction section 11 adds an image correction signal Ec to an input image signal Din to obtain a corrected image signal, it is compared with a threshold level Th at a binarization circuit 12, and converted to a binarized image signal Dout. Furthermore, an error calculation section 13 calculates the difference between the corrected image signal and the binarized image signal to provide an output of an error signal Er, a weighted error calculation section 14 multiplies a weighting coefficient from a weighting coefficient storage section 15 with the error signal to obtain a weighted error signal Erh and the weighted error signal is accumulated in an error storage section 17 storing the signal corresponding to one line of N-pixels via an error storage control section 16. In the case of binarizing a multilevel image signal with M-pixels in one line, M being larger than N, the N-pixels in the error storage section is arranged to optional pixels in the M-pixels in advance, the error storage control section 16 allocates the weighted errors at corresponding positions of the error storage section 17 with respect to the positions at which the N-pixels are arranged and allocates the weighted errors to the positions adjacent to the corresponding positions of the error storage section 17 with respect to other positions.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error storage of an image processing apparatus for converting a multi-valued image signal obtained by raster scanning into a binarized image signal or a multi-valued image signal using an error diffusion method. The present invention relates to a control method and an error storage control device.

[0002]

2. Description of the Related Art Generally, in document image processing capable of handling image information, image information read by a reading means such as a scanner is simply binarized by a fixed threshold for image information such as characters and line drawings, and photographs are taken. The image information having the gradation is binarized by a pseudo gradation means such as a dither method or an error diffusion method. This is because when the read image information is subjected to a simple binarization process with a fixed threshold value, the resolution of the character and line drawing areas is preserved, so that the image quality is not deteriorated.
There is a problem that the image quality is deteriorated because the gradation is not preserved in the area of the photographic image, and when the read image information is subjected to pseudo gradation processing such as the systematic dither method, the area of the photographic image becomes gradation. This is because the image quality is not deteriorated because the image quality is preserved, but there is a problem that the image quality is deteriorated because the resolution is deteriorated in the character and line drawing areas.

However, if such a single binarization process is performed on the read image, the image quality of each region having different characteristics cannot be satisfied. Therefore, the error diffusion method is known as a method that satisfies the gradation of the area of the photographic image and is excellent in the resolution of the area of the character and the line drawing as compared with the systematic dither method. The error diffusion method is described in, for example, the literature (An Adaptive Algori
thm for Spatial Grayscaleby RW Floyd and L. Stein
berg, Proceeding of the SID Vol.17-2, pp.75-77
), The density of the pixel of interest is multiplied by an appropriate weighting coefficient, which is the binarization error of the already binarized peripheral pixels, and binarized with a fixed threshold value. .

FIG. 10 shows an example of an image processing apparatus for carrying out a binarization process using an error diffusion method, which is a multi-valued input image signal D.
Input in to the image signal correction unit 1
At, the image correction signal Ec is added to the input image signal Din to obtain the corrected image signal Dinc. This corrected image signal Dinc is set to 2
The binarization circuit 2 compares the binarization threshold Th with the binarization circuit 2 and outputs the binarized image signal Dout. Binarization threshold T
h is 2 if the input image signal Din is 8 bits, for example.
It is set to 128, which is half of 56. The binarization circuit 2 outputs "1", that is, a black pixel signal as the binarized image signal Dout when the corrected image signal Dinc is equal to or greater than the binarized threshold Th, and outputs 2 when the corrected image signal Dinc is smaller than the binarized threshold Th. As the binarized image signal Dout, "0", that is, a signal of a white pixel is output.

Further, the corrected image signal Dinc and the binarized image signal Dout are supplied to the binarized error calculation unit 3, and the binarized error calculation unit 3 supplies the corrected image signal Dinc and the binarized image signal D.
The difference from out is calculated, the binarized error signal Er is output, and this binarized error signal Er is supplied to the weight error calculation unit 4.
The binarized image signal Dout in this case is "0" when it is "0" and "255" when it is "1", and the binarization error is calculated. Reference numeral 5 denotes a weight coefficient storage unit that stores the weight coefficient of the error filter for calculating the weight error. From the weight coefficient storage unit 5 to the weight error calculation unit 4, the weight coefficients A, B, and C and D are read and supplied.
The weighting error calculation unit 4 multiplies the binarization error signal Er by the weighting factors A, B, C and D, and outputs the weighting error signal Erh for the surrounding pixel positions. The weighting factors A, B,
C and D are, for example, A = 7/16, B = 1/16, C =
The sum is set to 1 such as 5/16 and D = 3/16.

The weight error signal Erh from the weight error calculation unit 4
Is accumulated in the relevant pixel position of the error storage unit 6. That is,
The weighting errors of four pixels around the pixel of interest * are accumulated at corresponding pixel positions to obtain accumulated values EA, EB, EC and ED. Then, the error storage unit 6 outputs the cumulative value of the weighting error of the pixel of interest * to the image signal correction unit 1 as an image correction signal Ec. In the image processing apparatus having such a configuration, the input image signal Din is input to the image signal correction unit 1 by the image signal correction unit 1 pixel by pixel.
After c is added and corrected, it is binarized by the binarization circuit 2, and this is repeated for one line to perform binarization processing for one line. Then, the binarization process for each input line is completed by repeating the binarization process for each line for the total number of lines of the input image signal Din.

Further, in Japanese Patent Laid-Open No. 63-155952, a distribution coefficient for distributing a binarization error to unprocessed pixels around a pixel of interest in an image processing device for binarizing using an error diffusion method. A distribution coefficient generating means is provided for generating (weighting coefficient) in accordance with random number generation arbitrarily set for each arbitrary sub-scanning line from a plurality of distribution coefficient sets at a predetermined change cycle, and the distribution coefficient is sub-scanned. Textures are prevented by changing each line.

[0008]

An image processing apparatus which performs a binarization process using such an error diffusion method is a system for correcting an error between an input image signal and an output image signal.
A storage capacity for one line is required as an error storage unit that accumulates the calculated weighting error pixel by pixel. On the other hand, as image information to be handled, large size information such as A4 size to B4 and A3 is increasing, and the resolution is also increasing. Therefore, there is a problem that an error storage unit having a storage capacity capable of coping with a large size and a large resolution is required, the memory size of the storage unit becomes large, and the cost increases.

Therefore, the invention described in claim 1 is a binarization or multi-value conversion based on an error diffusion method of an input image signal having a large size and a large resolution without increasing the storage capacity of the error storage means to be used. There is provided an error storage control method for an image processing apparatus which can deal with the problem and can reduce the memory size and the cost.

According to the second aspect of the present invention, the binarization or multi-valued conversion based on the error diffusion method of the input image signal having a large size or a large resolution can be performed without increasing the storage capacity of the error storage means used. Provided is an error storage control device of an image processing device which can cope with the problem and can reduce the memory size and the cost.

According to the third aspect of the present invention, the binarization or multi-valued conversion based on the error diffusion method of an input image signal having a large size or a large resolution can be performed without increasing the storage capacity of the error storage means to be used. This makes it possible to reduce the size of the memory and reduce the cost. Further, for an input image signal having a small size or a small resolution, the error correction accuracy is increased to perform binarization based on the error diffusion method or Provided is an error storage control method of an image processing device capable of multi-value conversion.

Further, the invention according to claim 4 is a binarization or multi-value conversion based on an error diffusion method of an input image signal having a large size and a large resolution without increasing the storage capacity of the error storage means to be used. This makes it possible to reduce the size of the memory and reduce the cost. Further, for an input image signal having a small size or a small resolution, the error correction accuracy is increased to perform binarization based on the error diffusion method or An error storage control device of an image processing device capable of multi-value conversion.

[0013]

According to the first aspect of the present invention,
After correcting the multi-valued image signal with the image correction signal to form a corrected image signal, the corrected image signal is converted into a binarized image signal or a multi-valued image signal and output, while the corrected image signal and the binary image signal are output. Calculate the error with the digitized image signal or multi-valued image signal,
By multiplying this error by the weighting coefficient set in advance to the peripheral pixels of the target pixel, the weighting error with respect to the peripheral pixels of the target pixel is obtained,
In an image processing apparatus for accumulating the weighting error at the corresponding pixel position of the error storing means for storing N pixels of one line and generating an image correction signal by using the accumulated error of the error storing means, one line has more than N pixels. When converting a large M-valued multi-valued image signal into a binarized image signal or a multi-valued image signal, N pixels of the error storage means are arranged in advance in arbitrary M pixels and the weighting error is set to N pixels. The arbitrary position of the arranged M pixels is accumulated at the corresponding pixel position of the error storage means, and the other positions are distributed to the adjacent pixel positions of the error storage means and accumulated.

According to a second aspect of the present invention, the multi-valued image signal is corrected by the image correction signal to be a corrected image signal, and the corrected image signal is converted into a binarized image signal or a multi-valued image signal. On the other hand, on the other hand, the error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by the weighting coefficient set in advance to the peripheral pixels of the pixel of interest, and the peripheral pixel of the pixel of interest is calculated. Obtain the weight error, and set this weight error to 1
In an image processing apparatus for accumulating at a corresponding pixel position of an error storage means for storing N pixels of a line and generating an image correction signal by using the accumulated error of this error storage means, the N pixels of the error storage means are preliminarily changed to M pixels. Arrangement is performed at an arbitrary pixel, and control is performed to accumulate a weighting error at an appropriate position of the M pixel where N pixels are arranged at a corresponding pixel position of the error storage unit, and an arbitrary weighting error is determined for the M pixels where N pixels are arranged. With respect to positions other than the position, the cumulative control means for performing control by distributing and accumulating to adjacent pixel positions of the error storage means, and the cumulative control of this cumulative control means, the position where the weighting error is accumulated is arranged by N pixels. M
A switching means for switching between arbitrary positions of pixels or positions other than arbitrary positions is provided.

According to a third aspect of the present invention, the multi-valued image signal is corrected by the image correction signal to form a corrected image signal, and the corrected image signal is converted into a binarized image signal or a multi-valued image signal. On the other hand, on the other hand, the error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by the weighting coefficient set in advance to the peripheral pixels of the pixel of interest, and the peripheral pixel of the pixel of interest is calculated. Obtain the weight error, and set this weight error to 1
In an image processing apparatus that accumulates at a corresponding pixel position of an error storage unit that stores N pixels of a line and generates an image correction signal using the accumulated error of the error storage unit, one line has N lines.
When converting a multi-valued image signal of M pixels larger than a pixel into a binarized image signal or a multi-valued image signal, N pixels of the error storage means are arranged in advance in arbitrary pixels of M pixels, and the weight error is N. For any position of the M pixels in which the pixels are arranged, it is accumulated at the corresponding pixel position of the error storage means, and for other positions, it is distributed to the adjacent pixel positions of the error storage means and accumulated, and one line 2 multi-valued image signals of M pixels with N pixels or less
When converting to a binarized image signal or a multi-valued image signal, M
All the pixels are arranged in the error storage means, and the weighting error is accumulated at the corresponding pixel position in the error storage means.

According to a fourth aspect of the invention, the multi-valued image signal is corrected by the image correction signal to form a corrected image signal, and the corrected image signal is converted into a binarized image signal or a multi-valued image signal. On the other hand, on the other hand, the error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by the weighting coefficient set in advance to the peripheral pixels of the pixel of interest, and the peripheral pixel of the pixel of interest is calculated. Obtain the weight error, and set this weight error to 1
In an image processing apparatus that accumulates at a corresponding pixel position of an error storage unit that stores N pixels of a line and generates an image correction signal using the accumulated error of the error storage unit, one line has N lines.
When converting a multi-valued image signal of M pixels larger than pixels into a binarized image signal or a multi-valued image signal, N pixels of the error storage means are arranged in advance in arbitrary pixels of M pixels and the weight error is N. The control for accumulating the arbitrary position of the M pixel where the pixel is arranged at the corresponding pixel position of the error storage means is performed, and the weight storage error is performed for the position other than the arbitrary position of the M pixel where the N pixel is arranged. When the multi-valued image signal of M pixels in which one line is N pixels or less is converted into a binarized image signal or a multi-valued image signal by performing control for distributing and accumulating to adjacent pixel positions of A cumulative control unit for arranging all of them in the error storage unit and performing control for accumulating the weighting error at the corresponding pixel position of the error storage unit, and a multi-valued image signal of M pixels in which one line is larger than N pixels is a binarized image signal. Or when converting to a multi-valued image signal Position to accumulate weighted error accumulation control of the cumulative control means switched by one position other than the arbitrary position or any position M pixels arranged N pixels, one line N
When converting a multi-valued image signal of M pixels less than the pixel into a binarized image signal or a multi-valued image signal, the cumulative control of the cumulative control means is only the control of accumulating the weight error at the corresponding pixel position of the error storage means. The switching means for switching to is provided.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, a case where a multi-valued input image signal is converted into a binarized image signal will be described. (First Embodiment) This embodiment is an embodiment corresponding to claims 1 and 2, and as shown in FIG. 1, for example, an 8-bit input image signal read by an input device such as a scanner. Din is input to the image signal correction unit 11, and this image signal correction unit 11 converts the input image signal Din into the image correction signal E.
The corrected image signal Dinc is obtained by adding c. And
The binarized circuit 12 compares the corrected image signal Dinc with the binarized threshold value Th, and the binarized circuit 12 outputs the binarized image signal Dout. The binarization threshold Th is the input image signal D
Since in is 8 bits, set it to 128, which is half of 256.
The binarization circuit 12 outputs "1", that is, a black pixel signal as the binarized image signal Dout when the corrected image signal Dinc is equal to or greater than the binarized threshold Th, and outputs the binarized threshold T.
When it is smaller than h, "0", that is, a white pixel signal is output as the binarized image signal Dout.

Further, the corrected image signal Dinc and the binarized image signal Dout are supplied to the binarized error calculation unit 13, and the binarized error calculation unit 13 generates the corrected image signal Dinc and the binarized image signal Dout. The difference is calculated, the binarized error signal Er is output, and this binarized error signal Er is supplied to the weight error calculation unit 14. The binarized image signal Dout in this case is
The binarization error is calculated as "0" when it is "0" and "255" when it is "1".

Reference numeral 15 is a weighting coefficient storage unit for storing the weighting coefficient of the error filter for calculating the weighting error. From the weighting coefficient storage unit 15 to the weighting error calculation unit 14, the weighting coefficient of the peripheral pixel of the pixel of interest * is stored. A, B, C, D are read and supplied. The weighting error calculating section 14 multiplies the binarization error signal Er by the weighting factors A, B, C and D and outputs the weighting error signal Erh for the surrounding pixel positions. In addition,
The weighting factors A, B, C, D are, for example, A = 7/16, B
= 1/16, C = 5/16, D = 3/16, etc., so that the total sum is 1.

The weighting error signal Erh from the weighting error calculating unit 14 is accumulated in the corresponding pixel position of the error storing unit 17 forming the error storing unit via the error storing control unit 16 forming the accumulation controlling unit. Has become. The error storage unit 17 has a memory size capable of accumulating the weight error signal Erh of N pixels per line.

The weight error calculation unit 14 and the error storage control unit 16 have the configuration shown in FIG. That is, the weight error calculator 14 includes four multipliers 14A, 14B, 1
4C and 14D, the weight coefficient A from the weight coefficient storage unit 15 is supplied to the multiplier 14A, the weight coefficient B is supplied to the multiplier 14B, and the weight coefficient C is supplied to the multiplier 14.
C and the weighting coefficient D are supplied to the multiplier 14D. Also, each of the multipliers 14A, 14B, 14C, 1
The binarization error signal Er from the binarization error calculator 13 is supplied to 4D. Each of the multipliers 14A, 1
4B, 14C and 14D are weighted error signals Erh obtained by multiplying the binarized error signal Er by the weighting factors A, B, C and D, respectively.
A, ErhB, ErhC, ErhD are stored in the error memory control unit 16
To supply.

The error storage control unit 16 includes four selectors 21A, 21B, 21C, 21D and four adders 22.
A, 22B, 22C, 22D and three registers 23
B, 23C, and 23D, the weight error signal ErhA from the multiplier 14A is input to the A input terminal of the selector 21A and the adder 22A, and the weight error signal ErhB from the multiplier 14B is input to the adder 22A. Adder 22
B is input to the weighting error signal Erh from the multiplier 14C.
C is input to the adder 22C, the weight error signal ErhD from the multiplier 14D is input to the A input terminal of the selector 21D, and is also input to the adder 22D.

The adder 22A also receives the cumulative error EA of the corresponding pixel position read from the error storage unit 17, and adds the weighted error signal ErhA to the cumulative error EA to obtain the value of B of the selector 21A. Inputting to the input terminal. The adder 22B also inputs the output of the selector 21B, and inputs the value obtained by adding the weight error signal ErhB to the output to the register 23B. The adder 22C also receives the output of the selector 21C,
A value obtained by adding the weight error signal ErhC to this output is input to the register 23C. The adder 22D also inputs the data of the register 23D, and adds the weight error signal ErhD to this data to obtain the value of the selector 21D.
It is input to the B input terminal of D.

The selector 21B includes the register 23.
Input the data of C to the A input terminal,
Data is input to the B input terminal. The selector 2
1C inputs the data of the register 23D into the A input terminal and the data of the register 23C into the B input terminal. Each of the selectors 21A, 21B, 21C, 2
1D is a D-type flip-flop 24 that constitutes switching means.
The selection operation is performed according to the switching timing signal output from the Q output terminal. That is, the D
As shown in FIG. 5, the flip-flop 24 inputs a pixel clock CL, which takes a timing of converting the input image signal Din into a binarized image signal Dout for each pixel, to a CK input terminal, and inputs the pixel clock CL to this pixel clock CL. The switching timing signal output from the Q output terminal in synchronization with the H (high) level,
It is changed to L (low) level. When the switching timing signal is at H level, each selector 21A,
21B, 21C, and 21D select and output a signal input to the A input terminal, and when the switching timing signal is at L level, each selector 21A, 21B, 21C, and 21D outputs B.
The signal input to the input terminal is selected and output.

In such a structure, for example, the error storage unit 1 capable of accumulating the weighting error signal Erh of N pixels in one line.
On the other hand, in the case of converting the input image signal Din in which one line has M pixels (M = 2N) into the binarized image signal Dout, the N pixels in the error storage unit 17 are even pixels of the M pixels in the input image signal Din. It is arranged corresponding to. Attention pixel * (= 2n)
Is at the pixel position shown in Fig. 3 (a), which is shown in Fig. 3 (b).
Suppose that the pixel of interest * (= 2n) is at an even pixel position as shown in FIG. 2, the image correction signal Ec is added to the pixel of interest * (= 2n) to perform error correction. The binarizing circuit 12 binarizes and outputs a binarized image signal Dout. In FIG. 3 (b), the shaded portion indicates the even pixel position where N pixels of the error storage unit 17 are arranged, and the blank portion indicates the odd pixel position where N pixel of the error storage unit 17 is not arranged. .

The binarization error calculation unit 13 calculates the corrected image signal Din.
The difference between c and the binarized image signal Dout is calculated to output a binarized error signal Er (= E2n), and the weighting error calculation unit 14 uses the binarized error signal Er (= E2n) as the pixel of interest *. The weighting error is calculated by multiplying the weighting factors A, B, C, and D of the surrounding pixels. This weight error is distributed as shown in FIG. That is, the weighting error A x obtained by multiplying the weighting factor A
E2n is obtained by multiplying the error of the next pixel (2n + 1) by the weighting coefficient B, and E × 2n is obtained by multiplying the error of the even pixel 2 (n−1) of the next line by the weighting coefficient C. The weighting error C × E2n obtained by multiplying the error of the even pixel 2n on the next line by the weighting coefficient D is distributed to the error of the even pixel 2 (n + 1) on the next line. It In this case, the even pixel 2 (n-
1), 2n, and 2 (n + 1) correspond to N pixels in the error storage unit 17.

When the target pixel * shifts to the next pixel (2n + 1) as shown in FIG. 3C, this target pixel * (= 2
n + 1) is an image correction signal E corresponding to the error of the next pixel (2n + 1) obtained by the image signal correction unit 11 in the previous error processing.
Error correction is performed by adding c, and the pixel of interest (2n + 1) corrected for error is binarized by the binarization circuit 12 and the binarized image signal Dout is output. In FIG. 3 (c), the shaded area shows the even pixel positions where N pixels of the error storage unit 17 are arranged, and the blank areas show the odd pixel positions where N pixels of the error storage unit 17 are not arranged. .

The binarization error calculation unit 13 calculates the corrected image signal Din.
The difference between c and the binarized image signal Dout is calculated to output the binarized error signal Er (= E2n + 1), and the weighting error calculation unit 1
Reference numeral 4 multiplies the binarized error signal Er (= E2n + 1) by the weighting factors A, B, C and D of the pixels surrounding the pixel of interest * to calculate the weighting error. This weight error is distributed as shown in FIG. 4 (b). That is, the weight error A × E (2n + 1) obtained by multiplying the weight coefficient A is the weight error B × E (2n +) obtained by multiplying the error of the next pixel 2 (n + 1) by the weight coefficient B.
1) is the error of the even pixel 2 (n-1) of the next line,
Weighting error C × E (2n + 1) obtained by multiplying the weighting coefficient C
Is a weighting error D × E (2n + 1) obtained by multiplying the error of the even pixel 2n on the next line by the weighting coefficient D is distributed to the error of the even pixel 2 (n + 1) on the next line.
Thus, when the pixel of interest * is an odd number, it is distributed to even pixels 2 (n−1), 2n, 2 (n + 1) of adjacent pixel positions of the next line existing as N pixels of the error storage unit 17, respectively. Will be. The result of accumulating the weighted error signals calculated by such a procedure is used as the error storage control unit 16
Will be stored in the corresponding pixel position of the error storage unit 17.

That is, when the pixel of interest * is an even pixel 2n, the D-type flip-flop 24 outputs the switching timing signal of H level, and the selectors 21A, 21B, 21C and 21D of the error storage controller 16 have A input terminals. Select. At this time, the binary error signal E is stored in the register 23D.
The value D of the weight error signal ErhD obtained by multiplying 2n by the weight error D ×
E2n is input via the selector 21D.

In addition, the value obtained by adding the value C × E2n of the weight error signal ErhC obtained by multiplying the binarization error signal E2n by the weight error C and the value of the register 23D by the adder 22C is input to the register 23C. . In addition, the register 23B has 2
A value obtained by adding the value B × E2n of the weight error signal ErhB obtained by multiplying the value error signal E2n by the weight error B and the value of the register 23C by the adder 22B is input. At this time, the value previously input to the register 23D is the pixel 2n which is the previous pixel.
−1 and the pixel 2 (n−1) are processed, and the error is a value obtained by multiplying the weight coefficient D.

The value previously input to the register 23C is a value obtained by multiplying an error generated when the pixels 2n-1 and 2 (n-1), which are the previous pixels, by the weighting coefficient C, and The previous pixel, pixel 2n-3 and pixel 2 (n-
This is a value obtained by adding the error generated when processing 2) is multiplied by the weighting coefficient D. Further, the output of the selector 21A, that is, the value A × E2n of the weight error signal ErhA is directly supplied to the image signal correction unit 11 as the image correction signal Ec and used for the error correction of the next pixel 2n + 1.

When the next pixel 2n + 1 is binarized, that is, when the target pixel * is an odd pixel 2n + 1,
The D-type flip-flop 24 outputs an L-level switching timing signal, and each selector 21 of the error storage controller 16
A, 21B, 21C and 21D select the B input terminal.
At this time, the binary error signal E2n is stored in the register 23D.
The value D of the weight error signal ErhD obtained by multiplying +1 by the weight error D ×
A value obtained by adding E2n + 1 and the value of the register 23D by the adder 22D is input via the selector 21D.

The register 23C has a weight error signal ErhC obtained by multiplying the binarized error signal E2n + 1 by the weight error C.
Value of C × E2n + 1 and the value of the register 23C are added by the adder 2
The value added in 2C is input. In addition, the register 23B
Is the value B × E2n + 1 of the weight error signal ErhB obtained by multiplying the binarization error signal E2n + 1 by the weight error B, and the register 23.
A value obtained by adding the value of B and the value of the adder 22B is input. The value A × E2n + 1 of the weight error signal ErhA obtained by multiplying the binarization error signal E2n + 1 by the weight error A and the error storage unit 17 are also included.
The value added by the adder 22A with the value read from the image signal correction unit 1 is used as the image correction signal Ec from the selector 21A.
1 and is used for error correction of the next pixel 2 (n + 1). At this time, the value of the register 23B is written into the error storage unit 17 at the same time as the reading.

When binarizing the even pixels in one line in this way, the weighting errors obtained for the four pixels surrounding the pixel of interest * are accumulated at the corresponding pixel positions in the error storage unit 17, and the odd pixels are When the binarization processing is performed, the weighting errors obtained for the four pixels around the target pixel * are accumulated at the corresponding pixel positions in the adjacent error storage unit 17 to generate the image correction signal Ec for each target pixel *. This allows
By using the error storage unit 17 in which the number of stored pixels is N pixels, the input image signal Din of M pixels in which one line is twice as many as N pixels can be binarized. That is, it is not necessary to provide an error storage unit having a storage capacity twice as large as N pixels in order to binarize the input image signal Din of M (= 2N) pixels, and the memory size can be reduced and the cost can be reduced. be able to.

In this embodiment, the error storage unit 1
The case where the N pixels of 7 are arranged corresponding to the even pixels of the M pixels of the input image signal Din has been described as an example, but the present invention is not necessarily limited to this, and the N pixels of the error storage unit 17 are set to the pixels of the input image signal Din. Even when the pixels are arranged corresponding to odd-numbered pixels of M pixels, the same effect can be obtained.

(Second Embodiment) In this embodiment,
In the embodiment corresponding to claims 3 and 4, the configuration other than the switching means for selectively controlling the sectors 21A to 21D of the error storage control unit 16 is the same as that of the first embodiment. As shown in FIG. 6, the switching means inputs the output from the Q output terminal of the D-type flip-flop 24 to one input terminal of the 2-input AND gate 25. The comparator 26 compares N pixels, which is the number of pixels stored in the error storage unit 17, with M pixels, which is the number of pixels of one line of the input image signal Din, and when N <M, a high-level output is output from the AND gate. It is input to the other input terminal of the gate 25, and when N ≧ M, a low level output is input to the other input terminal of the AND gate 25. The AND gate 25 outputs a switching timing signal.

If such a switching means is used, N <M
7A, the output from the Q output terminal of the D flip-flop 24 can be directly output as the switching timing signal as shown in FIG. 7A, and when N ≧ M, the output of FIG.
As shown in (b), the output of the AND gate 25 is set to L regardless of the output from the Q output terminal of the D flip-flop 24.
The level is set so that the L-bell switching timing signal is always output.

In such a configuration, when N <M, the switching means outputs the output from the Q output terminal of the D-type flip-flop 24 as it is as the switching timing signal, which is the same as in the first embodiment. The binarization process is performed. Therefore, in this case, the same effect as that of the first embodiment can be obtained. Further, when N ≧ M, the switching means always outputs the switching timing signal that is L level, so that each of the selectors 21A to 21D always selects only the A input terminal.

As a result, the error storage control unit 16 stores all the pixels of one line of the input image signal Din in the error storage unit 17.
All the weighting errors calculated when binarizing each pixel of one line of the input image signal Din are arranged at the corresponding pixel position of the error storage unit 17. Therefore, when the number M of pixels in one line of the input image signal Din is less than or equal to the number N of pixels stored in the error storage unit 17, there is no need to perform a process of distributing the weight error to adjacent pixel positions, and the input image signal Din On the other hand, increase the error correction accuracy to 2
Value processing is possible.

In each of the above-described embodiments, when the number M of pixels in one line of the input image signal Din is twice the number N of pixels stored in the error storage unit 17, the error storage unit 17 is irrespective of the number of lines. The N pixels of the input image signal Din are arranged in the even pixels or the odd pixels of the input image signal Din, but the present invention is not limited to this. For example, in the odd line, the N pixels of the error storage unit 17 are arranged in the odd pixels of the input image signal Din. The even-numbered line may have a configuration in which N pixels of the error storage unit 17 are arranged in even-numbered pixels of the input image signal Din.

The control in this case is, for example, the pixel of interest * (=
2n) is at the pixel position shown in FIG. 8 (a), which is shown in FIG.
As shown in (b) of FIG. 4, if it is an even-numbered pixel position on an even-numbered line, the pixel of interest * (= 2n) is subjected to error correction by adding the image correction signal Ec in the image signal correction unit 11, and this error is corrected. The corrected target pixel 2n is binarized by the binarization circuit 12 and the binarized image signal Dout is output. In FIG. 8B, the hatched portion indicates the pixel position where N pixels of the error storage unit 17 are arranged, and the blank portion indicates the error storage unit 1.
7 shows the pixel positions where N pixels are not arranged.

The binarization error calculation unit 13 calculates the corrected image signal Din.
The difference between c and the binarized image signal Dout is calculated to output a binarized error signal Er (= E2n), and the weighting error calculation unit 14 uses the binarized error signal Er (= E2n) as the pixel of interest *. The weighting error is calculated by multiplying the weighting factors A, B, C, and D of the surrounding pixels. This weight error is distributed as shown in FIG. That is, the weighting error A x obtained by multiplying the weighting factor A
E2n is a weight error B × E2n obtained by multiplying the error of the next pixel (2n + 1), which is an odd pixel, by the weight coefficient B, and the error of the odd pixel 2 (n−1) −1 of the next odd line is The weight error C × E2n obtained by multiplying the weight coefficient C is the error of the odd pixel 2n−1 of the next odd line, and the weight error D × E2n obtained by multiplying the error of the next odd line is the odd number of the next odd line. It is allocated to the error of pixel 2 (n + 1) -1. In this case, odd pixels 2 (n-1) -1, 2 of the next odd line
n−1, 2 (n + 1) −1 correspond to N pixels in the error storage unit 17.

When the target pixel * shifts to the next odd pixel (2n + 1) as shown in FIG. 8C, this target pixel *
In (= 2n + 1), the image correction signal Ec corresponding to the error of the next pixel (2n + 1) obtained in the previous error processing by the image signal correction unit 11 is added to perform the error correction, and the error-corrected target pixel 2n + 1 is set. Binarize by the binarization circuit 12 to 2
The binarized image signal Dout is output. In FIG. 8 (c), the shaded area indicates the pixel position where N pixels of the error storage unit 17 are arranged, and the blank area indicates the pixel position where N pixels of the error storage unit 17 is not arranged.

The binarization error calculation unit 13 calculates the corrected image signal Din
The difference between c and the binarized image signal Dout is calculated to output the binarized error signal Er (= E2n + 1), and the weighting error calculation unit 1
Reference numeral 4 multiplies the binarized error signal Er (= E2n + 1) by the weighting factors A, B, C and D of the pixels surrounding the pixel of interest * to calculate the weighting error. This weight error is distributed as shown in FIG. 9 (b). That is, the weight error A × E (2n + 1) obtained by multiplying the weight coefficient A is the weight error B × E (2n +) obtained by multiplying the error of the next pixel 2 (n + 1) by the weight coefficient B.
1) is a weighting error C × E (2n +) obtained by multiplying the error of the odd-numbered pixel 2 (n−1) +1 of the next line by the weighting coefficient C.
In 1), the weight error D × E (2n + 1) obtained by multiplying the error of the odd pixel 2n + 1 on the next line by the weight coefficient D is distributed to the error of the odd pixel 2 (n + 1) +1 on the next line. It Thus, when the pixel of interest * is an odd number, odd pixels 2 (n−1) +1, 2n + 1, 2 which are the adjacent pixels of the next line in which N pixels of the error storage unit 17 are arranged are arranged.
(N + 1) +1 will be allocated to each.

As described above, the odd-numbered lines are stored in the error storage unit 1
N pixels of 7 are arranged in odd pixels of the input image signal Din, and N pixels of the error storage unit 17 are arranged in the input image signal D in the even line.
Even with the configuration in which the pixels are arranged in in even-numbered pixels, the memory size of the error storage unit can be downsized and the cost can be reduced as in the above-described embodiment. The above-described embodiments have described the case where the multi-valued input image signal Din is binarized. However, the present invention is not limited to this. For example, when the number of gradations of the output device is large, 2 Use a multi-valued circuit that compares with multiple thresholds instead of the valued circuit,
A process of converting the multivalued input image signal Din into a multivalued image signal corresponding to the number of gradations of the output device may be performed.

[0046]

As described above, according to the first and second aspects of the present invention, binarization based on the error diffusion method of an input image signal having a large size and a large resolution without increasing the storage capacity of the error storage means to be used. Alternatively, multi-value conversion can be dealt with, which can reduce the memory size and cost.

According to the third and fourth aspects of the present invention, binarization or multi-value conversion based on the error diffusion method for an input image signal having a large size or a large resolution is possible without increasing the storage capacity of the error storage means used. It is possible to deal with the binarization conversion, which makes it possible to reduce the memory size and cost, and to improve the error correction accuracy for an input image signal with a small size and a small resolution, and to use the error diffusion method. Binarization or multi-value conversion can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing configurations of a weight error calculation unit and an error storage control unit according to the same embodiment.

FIG. 3 is a diagram showing a relationship between a pixel arrangement of an error storage unit and a target pixel according to the same embodiment.

FIG. 4 is a diagram showing a relationship between a pixel of interest and error distribution according to the same embodiment.

FIG. 5 is a timing chart for explaining the operation of the switching means in the same embodiment.

FIG. 6 is a circuit configuration diagram of a switching unit according to a second embodiment of the present invention.

FIG. 7 is a timing chart for explaining the operation of the switching means in the same embodiment.

FIG. 8 is a diagram showing another example of the pixel arrangement of the error storage unit.

9 is a diagram showing the relationship between the pixel of interest in FIG. 8 and error distribution.

FIG. 10 is a block diagram showing a conventional example.

[Explanation of symbols]

 11 ... Image signal correction unit 12 ... Binarization circuit 13 ... Binary error calculation unit 14 ... Weight error calculation unit 15 ... Weight coefficient storage unit 16 ... Error storage control unit 17 ... Error storage unit 24 ... D flip-flop ( Switching means)

Claims (4)

[Claims] 1. A multi-valued image signal is corrected by an image correction signal to form a corrected image signal, and then the corrected image signal is converted into a binarized image signal or a multi-valued image signal and output.
An error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by a weighting coefficient set in advance to peripheral pixels of the pixel of interest to obtain a weighting error with respect to the peripheral pixels of the pixel of interest. In the image processing apparatus for accumulating the weighting error at the corresponding pixel position of the error storing means for storing N pixels of one line and generating the image correction signal using the accumulated error of the error storing means, one line has N pixels. 2 multi-valued image signals with larger M pixels
When converting to a binarized image signal or a multi-valued image signal, N pixels of the error storage means are arranged in advance in arbitrary pixels of M pixels, and weighting errors are placed in arbitrary positions of M pixels in which N pixels are arranged. On the other hand, the error accumulation means accumulates at the corresponding pixel position,
An error storage control method for an image processing apparatus, characterized in that other positions are distributed to adjacent pixel positions of the error storage means and accumulated. 2. A multi-valued image signal is corrected by an image correction signal to form a corrected image signal, and the corrected image signal is converted into a binarized image signal or a multi-valued image signal and output.
An error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by a weighting coefficient set in advance to peripheral pixels of the pixel of interest to obtain a weighting error with respect to the peripheral pixels of the pixel of interest. In the image processing apparatus for accumulating the weighting error at the corresponding pixel position of the error storing means for storing N pixels of one line and generating the image correction signal by using the accumulated error of the error storing means, The N pixels are arranged in advance in arbitrary pixels of M pixels, and the weight error is controlled to accumulate in the corresponding pixel position of the error storage means with respect to the arbitrary position of M pixels in which the N pixels are arranged. Accumulation control means for performing control of distributing and accumulating to adjacent pixel positions of the error storage means with respect to positions other than arbitrary positions of M pixels in which the pixels are arranged, and weighting error of the accumulation control of the accumulation control means. Cumulative An error storage control device for an image processing apparatus, characterized in that a switching means is provided for switching between a position to be stacked and an arbitrary position of M pixels in which N pixels are arranged or a position other than the arbitrary position. 3. A multi-valued image signal is corrected by an image correction signal to form a corrected image signal, and the corrected image signal is converted into a binarized image signal or a multi-valued image signal and output,
An error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by a weighting coefficient set in advance to peripheral pixels of the pixel of interest to obtain a weighting error with respect to the peripheral pixels of the pixel of interest. In the image processing apparatus for accumulating the weighting error at the corresponding pixel position of the error storing means for storing N pixels of one line and generating the image correction signal using the accumulated error of the error storing means, one line has N pixels. 2 multi-valued image signals with larger M pixels
When converting to a binarized image signal or a multi-valued image signal, N pixels of the error storage means are arranged in advance in arbitrary pixels of M pixels, and weighting errors are placed in arbitrary positions of M pixels in which N pixels are arranged. On the other hand, the error accumulation means accumulates at the corresponding pixel position,
For other positions, it is distributed to adjacent pixel positions of the error storage means and accumulated, and a multi-valued image signal of M pixels in which one line is N pixels or less is binarized image signal or multi-valued image signal. In the case of converting to M, all the M pixels are arranged in the error storage means, and the weighting error is accumulated at the corresponding pixel position of the error storage means. 4. A multi-valued image signal is corrected by an image correction signal to form a corrected image signal, and then the corrected image signal is converted into a binarized image signal or a multi-valued image signal and output.
An error between the corrected image signal and the binarized image signal or the multi-valued image signal is calculated, and this error is multiplied by a weighting coefficient set in advance to peripheral pixels of the pixel of interest to obtain a weighting error with respect to the peripheral pixels of the pixel of interest. In the image processing apparatus for accumulating the weighting error at the corresponding pixel position of the error storing means for storing N pixels of one line and generating the image correction signal using the accumulated error of the error storing means, one line has N pixels. 2 multi-valued image signals with larger M pixels
When converting to a binarized image signal or a multi-valued image signal, N pixels of the error storage means are arranged in advance in arbitrary pixels of M pixels, and weighting error is placed in arbitrary positions of M pixels in which N pixels are arranged. On the other hand, control for accumulating at the relevant pixel position of the error storage means is performed, and the weighting error is distributed to adjacent pixel positions of the error storage means with respect to positions other than arbitrary positions of M pixels in which N pixels are arranged. In the case of controlling the accumulation and converting a multi-valued image signal of M pixels in which one line is N pixels or less into a binarized image signal or a multi-valued image signal, all the M pixels are arranged in the error storage means. Accumulation control means for performing control for accumulating the weighting error at the relevant pixel position of the error storage means, and a multi-valued image signal of M pixels in which one line is larger than N pixels into a binarized image signal or a multi-valued image signal. When converting, the cumulative control means The cumulative control is switched depending on whether the position where the weighting error is accumulated is an arbitrary position of M pixels in which N pixels are arranged or a position other than the arbitrary position, and a multi-valued image signal of M pixels in which one line is N pixels or less is binarized. In the case of converting to an image signal or a multi-valued image signal, a switching means is provided for switching the cumulative control of the cumulative control means to only control for accumulating the weighting error at the corresponding pixel position of the error storage means. Error storage control device of image processing device.