JPH09307413A - Comparator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator which can increase its operating speed and also can reduce its power consumption. SOLUTION: A 1st switch circuit group including switch circuits 16, 17, 20, 21, 24 and 25 is turned on by a 1st clock signal ϕ1. Then a difference voltage signal is inputted to a differential amplifier 28 via the capacity elements 14 and 15. At the same time, both differential amplifiers 28 and 29 are set at each prescribed voltage level. A 2nd switch circuit group of switch circuits 18, 19, 22, 23, 26 and 27 is turned on by a 2nd clock signal ϕ2 to secure connection among both amplifiers 28 and 29 and a comparator 30 respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a comparator suitable for a high speed and high accuracy A / D converter.

[0002]

2. Description of the Related Art FIG. 3 is a block diagram of a conventional comparator.
The comparator shown in FIG. 3 includes the differential amplifiers 114 and 11 respectively.
5,116 and two switch circuits 108,109; 11 attached to each differential amplifier 114,115,116.
0, 111; 112, 113 are provided. Here, each differential amplifier 114, 115, 116 and each two switch circuits 108, 109; 110, 111; 112, 113 attached to each differential amplifier 114, 115, 116.
For the sake of convenience, the group of and is referred to as unit circuits 131, 132, and 133. Each of the differential amplifiers 114, 115, 116 has two input terminals, that is, an in-phase input terminal 114a, 115a, 116a and an in-phase input terminal 114b, 115b, 116b, and an in-phase output terminal 114c, 115c, 116c. It has two output terminals 114d, 115d, and 116d, and has two switch circuits 108 and 10 respectively.
9; 110, 111; 112, 113, one of the switch circuits 108, 110, 112 is provided for each differential amplifier 1
14, 115, 116 negative-phase input terminals 114a, 115
a, 116a and negative phase output terminals 114c, 115c, 11
6c, and the other switch circuits 109, 111, 113 on the other side are respectively connected to the differential amplifiers 114, 1
In-phase input terminals 114b, 115b, 11 of 15, 116
6b and the in-phase output terminals 114d, 115d, 116d.

The comparator is further provided with four switch circuits 104, 105, 106 and 107. These four switch circuits 104, 105, 10
Of 6, 107, the switch circuit 104 inputs the input voltage signal V1 from one end and transmits it to the other end. One end of the switch circuit 104 is connected to the terminal 100.

Further, the switch circuit 105 receives the reference voltage signal V2 from one end and transmits it to the other end. One end of the switch circuit 105 is connected to the terminal 101. Further, the switch circuit 106 has one end connected to one end of the switch circuit 105 and the other end connected to the other end of the switch circuit 104, and transmits the reference voltage signal V2 from one end to the other end.

The switch circuit 107 has one end also connected to one end of the switch circuit 105 and the other end connected to the other end of the switch circuit 105, and transmits the reference voltage signal V2 from one end to the other end. . Furthermore, the comparator shown in FIG. 3 includes a switch circuit 104 and a switch circuit 1.
06 connecting point between the other ends and the unit circuit 131 of the first stage
Of the differential amplifier 114, the reverse phase input terminal 114a of the differential amplifier 114, the connection point between the other ends of the switch circuits 105 and 107, and the common mode input terminal 114b of the differential amplifier 114. Between the phase output terminal 114c and the anti-phase input terminal 115a of the differential amplifier 115 that constitutes the second-stage unit circuit 132, and between the in-phase output terminal 114d of the differential amplifier 114 and the in-phase input terminal of the differential amplifier 115. 115b and the capacitive elements 117, 1 respectively.
18, 119 and 120 are arranged. Further, between the anti-phase output terminal 115c of the differential amplifier 115 and the anti-phase input terminal 116a of the differential amplifier 116 that constitutes the unit circuit 133 of the third stage, and the in-phase output terminal 115d of the differential amplifier 115. In-phase input terminal 116 of differential amplifier 116
Capacitance elements 121 and 122 are arranged between the respective capacitors b and b.

Further, between the anti-phase output terminal 116c of the differential amplifier 116 and the anti-phase input terminal 125a of the comparison circuit 125, and the in-phase output terminal 116d of the differential amplifier 116.
And the in-phase input terminal 125b of the comparison circuit 125, switch circuits 123 and 124 are provided, respectively. Further, the input voltage signal V1,
The reference voltage signal V2 is input, and the first clock signal φ1 and the second clock signal φ2 having opposite phases are input to the terminals 102 and 103. Switch circuits 104, 105,
108 to 113 are turned on / off by the first clock signal φ1, and the switch circuits 106, 107, 123, 1
24 is turned on and off by the second clock signal φ2.

In the comparator configured as described above,
The input voltage signal V1 and the reference voltage signal V2 are input to the terminals 100 and 101, and the “H” level first clock signal φ1 and the “L” level second clock signal φ2 are input to the terminals 102 and 103. Then, the switch circuits 104, 105, 10 are driven by the first clock signal φ1 at the'H 'level.
8 to 113 are turned on, and the switch circuits 106, 107, 123, and 124 are driven by the second clock signal φ2 at the'L 'level.
Turns off. Then, the input voltage signal V1 input to the terminal 100 is transmitted via the switch circuit 104 to the capacitive element 1
The reference voltage signal V2 input to the terminal 17 and also to the terminal 101 is transmitted via the switch circuit 105 to the capacitive element 1
18 is input. Further, each differential amplifier 114, 11
Input / output terminals of 5,116 are switch circuits 108 to 113
And each of the differential amplifiers 1
A predetermined voltage V3 is output from 14, 115 and 116. Then, the capacitor 117 is charged with the voltage (V3-V1) and the capacitor 118 is charged with the voltage (V3-V2). The voltage V3 is applied to both ends of each of the capacitive elements 119 to 122. Therefore, each capacitive element 119
The accumulated charge of each of the .about.122 is zero.

Next, the phases of the first clock signal φ1 and the second clock signal φ2 are inverted with respect to each other, whereby the first clock signal φ of the'L 'level is applied to the terminals 102 and 103.
1, the second clock signal φ2 of'H 'level is input. Then, this time, the switch circuits 104, 105, 10
8 to 113 are turned off, and the switch circuits 106, 107, 1
23 and 124 turn on. Then, the voltage (V3-V1 + V2) is input to the anti-phase input terminal 114a of the differential amplifier 114, and the voltage V3 is input to the in-phase input terminal 114b. Further, since the switch circuits 108 to 113 are off and the switch circuits 123 and 124 are on, the comparison circuit 1
The differential amplifiers 144, 115, 1 are provided between the two input terminals of the 25 negative-phase input terminal 125a and the in-phase input terminal 125b.
16 The voltage (V1
-V2) .alpha. Is input as the difference voltage. Comparison circuit 12
5 compares the input voltage with the reference voltage based on the input difference voltage, and outputs the comparison result from terminals 126 and 127.

FIG. 4 is a circuit diagram of each differential amplifier shown in FIG.
It is a circuit diagram at the time of comprising with a transistor. In this differential amplifier, a pair of differential input NMOS transistors 1 to which a differential voltage signal is input via terminals 130 and 131.
39, 140, a current source PMOS transistor 136, an NMOS transistor 141 to which a bias voltage signal is input via terminals 132, 133, a terminal 134,
A pair of differential output PMOSs that output a differential voltage from the 135
It is composed of transistors 137 and 138.

FIG. 5 is a circuit diagram when the comparison circuit shown in FIG. 3 is constituted by MOS transistors. This comparison circuit has a flip-flop composed of PMOS transistors 157 and 158 and NMOS transistors 159 and 160, to which a differential voltage is input via terminals 150 and 151, and a signal from the flip-flop, which is fed to terminals 153 and 1.
Inverters 162 and 163 for output to 54 and terminal 15
An inverter 155 and an NMOS transistor 161 to which the first clock signal φ1 shown in FIG.
And a PMOS transistor 156 to which the first clock signal φ1 is input via the inverter 155. Here, the differential voltage signal is input to the terminals 150 and 151 and the first low-level signal is input to the terminal 152.
When the clock signal φ1 is input, both the PMOS transistor 156 and the NMOS transistor 161 are turned off, and the PMOS transistors 157 and 158 and the NMO.
S transistors 159 and 160, and inverter 16
The differential voltage is charged in the input gate capacitances of 2,163. Next, the terminal 152 receives the first clock signal φ at the'H 'level.
When 1 is input, PMOS transistors 156 and NM
Both the OS transistors 161 are turned on, and the comparison result of the input difference voltage signals is output from the flip-flop to the terminals 153 and 154 via the inverters 162 and 163.

[0011]

By the way, in the comparator shown in FIG. 3, the offsets of the differential amplifiers 114, 115 and 116 are removed by accumulating charges in the capacitive elements 117 to 122, and at the same time, the differential amplifiers are removed. 114, 11
The difference voltage signal input to
3 between the differential amplifier 114 and the differential amplifier 115, and the differential amplifier 1
15 and the differential amplifier 116 between the capacitive element 11 and
9, 120; 121, 122 are inserted. Therefore, the signals output from the differential amplifiers 114 and 115 are
Via these capacitance elements 119, 120; 121, 122, the voltage of the differential amplifier 116 can be settled at high speed by being blocked by the signal of the opposite phase due to the mirror effect of the MOS transistors forming the differential amplifiers 115, 116. Is difficult. Also, these capacitive elements 119, 120; 12
1, 122 to charge the current for charging the differential amplifier 114,
It is necessary to flow to 115 and 116. Since these currents are comparatively large currents, power consumption increases, and since these currents flow for a long time, there is a problem in that the circuit does not operate at high speed. Furthermore, in order to increase the gain to the comparison circuit 125, the three-stage differential amplifiers 114, 1
15 and 116 are required, and these three-stage differential amplifier 11
There is also a problem that power consumption is further increased by 4, 115 and 116.

In view of the above circumstances, it is an object of the present invention to provide a comparator in which circuit operation speed and power consumption are reduced.

[0013]

Means for Solving the Problems A comparator of the present invention which achieves the above object is (1-1) two input terminals, a negative phase input terminal and a common phase input terminal, and a negative phase output terminal and a common phase output terminal. A first differential amplifier having two output terminals, a first switch circuit arranged between the negative-phase input terminal and the negative-phase output terminal of the first differential amplifier, and the first differential circuit. A first switch circuit including a second switch circuit arranged between an in-phase input terminal and an in-phase output terminal of the differential amplifier of (1), and outputting a differential voltage signal representing a differential voltage between the input voltage and the reference voltage (1- 2) A second differential amplifier having two input terminals, an anti-phase input terminal and an in-phase input terminal, and two output terminals, an anti-phase output terminal and an in-phase output terminal, and a second differential amplifier of the second differential amplifier. A third switch circuit arranged between the negative-phase input terminal and the negative-phase output terminal, A second-stage circuit including a fourth switch circuit arranged between an in-phase input terminal and an in-phase output terminal of the second differential amplifier, and inputting and amplifying a differential voltage signal (1-3) reverse-phase input Comparing circuit having two input terminals, a terminal and an in-phase input terminal, and inputting a difference voltage signal amplified by the latter-stage circuit from these two input terminals and comparing the magnitude of the input voltage and the reference voltage. (1-4) Fifth switch circuit that inputs one of the first voltage signal of the input voltage signal and the reference voltage signal from one end and transmits it to the other end in a disconnectable manner (1-5) input Of the voltage signal and the reference voltage signal,
A sixth switch circuit which receives one of the other second voltage signals different from the first voltage signal from one end and transmits the other disconnectably to the other end (1-6) the fifth switch circuit Of the first differential amplifier disposed between the other end of the first differential amplifier and the negative phase input terminal of the first differential amplifier.
(1-7) A second element arranged between the other end of the sixth switch circuit and the in-phase input terminal of the first differential amplifier.
(1-8) One of the first voltage signal and the second voltage signal is input from one end and transmitted to the other end in a disconnectable manner, and the other end is connected to the fifth voltage signal. Switch circuit connected to the other end of the switch circuit of (1-9) The voltage signal of the one side is input from one end and transmitted to the other end in a disconnectable manner, and the other end is the sixth circuit. Eighth switch circuit connected to the other end of the switch circuit (1-10) Between the negative phase output terminal of the first differential amplifier and the negative phase input terminal of the second differential amplifier Ninth switch circuit arranged (1-11) Tenth switch circuit arranged between the in-phase output terminal of the first differential amplifier and the in-phase input terminal of the second differential amplifier (1 -12) The negative phase output terminal of the second differential amplifier and the negative phase input terminal of the comparison circuit. (1-13) A twelfth switch circuit arranged between the common mode output terminal of the second differential amplifier and the common mode input terminal of the comparison circuit (1-13). -14) A first switch circuit group including the first, second, third, fourth, fifth and sixth switch circuits, and the seventh, eighth, ninth, tenth and eleventh switches. , And a twelfth switch circuit,
A switch control circuit for controlling with a first clock signal and a second clock signal having mutually opposite phases is provided.

Here, the second differential amplifier is (2-1) a pair of differential input MOS transistors forming two input terminals of the second differential amplifier, and a pair of differential input MOS transistors. A pair of self-bias type current source M for connecting the sources of the input MOS transistors in common and arranged between the source and the ground and connecting the gates to the drains of the pair of differential input MOS transistors.
An OS transistor, a pair of differential output MOS transistors whose sources are connected to a power source and whose gates and drains are commonly connected, a pair of differential output MOS transistors, and a pair of differential input MOS transistors Circuit composed of a pair of MOS transistors for resistance, which are arranged between the gate and a bias voltage is input to the gate. (2-2) The drain which constitutes the two output terminals of the second differential amplifier, and which serves as a power source. A first buffer circuit which is connected and whose gate is connected to the connection point between the gate and drain of the pair of differential output MOS transistors; and a first buffer circuit and the ground. A pair of MOSs having a gate connected to the source of the resistance MOS transistor
It is effective to have a pair of buffer circuits each including a second buffer circuit including a transistor.

Further, in the first differential amplifier and the second differential amplifier, the respective switch circuits forming the first switch circuit group are closed and the respective second switch circuit groups forming the second switch circuit group are closed. With the switch circuit open,
The voltage appearing at the negative phase output terminal and the common mode output terminal of the first differential amplifier and the voltage appearing at the negative phase input terminal and the common phase input terminal of the second differential amplifier are substantially the same voltage. It is preferably adjusted so that

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the comparator of the present invention. The comparator shown in FIG. 1 includes a differential amplifier 28 (first differential amplifier according to the invention) and two switch circuits 20 and 21 (first and second switch circuits according to the invention). First stage circuit 41 and differential amplifier 29 (second differential amplifier according to the present invention)
And two switch circuits 24 and 25 (the third and third in the present invention).
A second stage circuit 42 including a fourth switch circuit) is provided. Each of the differential amplifiers 28 and 29 has a negative phase input terminal 2
8a, 29a and two in-phase input terminals 28b, 29b, and two output terminals 28c, 29c and two in-phase output terminals 28d, 29d, and two switch circuits 20 each. , 21; 24 and 25, one of the switch circuits 20 and 24 is connected to each differential amplifier 2
8, 29 are provided between the negative-phase input terminals 28a, 29a and the negative-phase output terminals 28c, 29c, and the other switch circuits 21, 25 are the common-mode input terminals of the differential amplifiers 28, 29. 28b, 29b and in-phase output terminals 28d, 2
It is provided between 9d.

Further, the comparator is further provided with four switch circuits 16, 17, 18 and 19 (the fifth and fifth in the present invention).
Sixth, seventh, and eighth switch circuits) are provided.
Of these four switch circuits 16, 17, 18, and 19, the switch circuit 16 inputs the input voltage signal V1 from one end and transmits it to the other end. One end of the switch circuit 16 is connected to the terminal 10. In addition, the switch circuit 17
Receives the reference voltage signal V2 from one end and transmits it to the other end. One end of the switch circuit 17 is connected to the terminal 10. Further, the switch circuit 18 has one end
It is connected to one end of the switch circuit 17 and the other end thereof is connected to the other end of the switch circuit 16, and transmits the reference voltage signal V2 from one end to the other end. The switch circuit 19 has one end
Again, it is connected to one end of the switch circuit 17, the other end is connected to the other end of the switch circuit 17, and the reference voltage signal V2
Transfer from one end to the other.

Further, in the comparator shown in FIG. 1, the connection point between the other ends of the switch circuit 16 and the switch circuit 18 and the negative phase input terminal 28a of the differential amplifier 28 constituting the first stage circuit 41 are connected. Between the other ends of the switch circuits 17 and 19 and the in-phase input terminal 28b of the differential amplifier 28.
Capacitance elements 14 and 15 are respectively disposed between and. Further, the negative phase output terminal 28 of the differential amplifier 28
c and the negative-phase input terminal 29a of the differential amplifier 29 forming the latter-stage circuit 42, and between the common-mode output terminal 28d of the differential amplifier 28 and the common-mode input terminal 29b of the differential amplifier 29, Switch circuits 22 and 23 (the ninth and tenth switch circuits referred to in the present invention) are arranged respectively. Further, between the anti-phase output terminal 29c of the differential amplifier 29 and the anti-phase input terminal 30a of the comparison circuit 30, and between the in-phase output terminal 29d of the differential amplifier 29 and the in-phase input terminal 30b of the comparison circuit 30. Are switch circuits 2
6, 27 (the eleventh and twelfth switch circuits according to the present invention) are arranged.

Here, the switch circuits 16, 17, 20,
The first switch circuit group composed of 21, 24, 25 and the second switch circuit group composed of the switch circuits 18, 19, 22, 23, 26, 27 are mutually output from a switch control circuit (not shown). Opposite phase first clock signal φ
It is controlled by the first and second clock signals φ2, respectively. Further, the input voltage signal V1 and the reference voltage signal V2 are input to the terminals 10 and 11, and the first clock signal φ1 and the second clock signal φ2 having mutually opposite phases are input to the terminals 12 and 13.

In the comparator configured as described above,
Input voltage signal V1 and reference voltage signal V are applied to terminals 10 and 11.
2 is input to terminals 12 and 13, respectively,
The first clock signal φ of H'level and the second clock signal φ2 of'L 'level are input. Then, the switch circuits 16, 17, 20, 2 which are the first switch circuit group
1, 24, 25 are turned on, and the switch circuits 18, 19, 22, 23, 26, 27 which are the second switch circuit group are turned off. As a result, the input voltage signal V1 input to the terminal 10 is input to the capacitive element 14 via the switch circuit 16, and the reference voltage signal V2 input to the terminal 11 is input to the capacitive element 15 via the switch circuit 17. Entered in. Further, the anti-phase input terminal 28a and the anti-phase output terminal 28c of the differential amplifier 28 are connected via the switch circuit 20, and the in-phase input terminal 28b and the in-phase output terminal 28 are connected.
d is connected via the switch circuit 21, whereby the differential amplifier 28 outputs a predetermined voltage V3. Then, the voltage (V3−
V1) and voltage (V3-V2) are charged. Further, the anti-phase input terminal 29a and the anti-phase output terminal 29c of the differential amplifier 29 are connected via the switch circuit 24, and the in-phase input terminal 29b and the in-phase output terminal 29d are connected to the switch circuit 25.
The differential amplifier 29 outputs a predetermined voltage V4. However, since the switch circuits 22 and 23 that are the second switch circuit group are off,
Two output terminals of the differential amplifier 28 and two of the differential amplifier 29
The two input terminals are not connected, and the differential amplifier 28 and the differential amplifier 29 operate independently of each other. Therefore, the capacitance driven by the differential amplifier 28 is the capacitance elements 14 and 15
Is the capacitance of the differential amplifier 28 and the input gate capacitance of the differential amplifier 28, and the capacitance driven by the differential amplifier 29 is only the input gate capacitance of the differential amplifier 29. The current flowing through both is reduced.

Next, the phases of the first clock signal φ1 and the second clock signal φ2 are inverted from each other, and the terminals 12 and 13 are provided.
The first clock signal φ at the “L” level and the second clock signal φ2 at the “H” level are input to the respective input terminals. Then, the switch circuits 16, 17, 20, 21, 24, and 25, which are the first switch circuit group, are turned off,
Switch circuits 18, 19, which are the second switch circuit group,
22, 23, 26 and 27 are turned on. Then, since the switch circuit 16 is turned off and the switch circuit 18 is turned on, the voltage (V) is applied to the negative-phase input terminal 28a of the differential amplifier 28.
3-V1 + V2) is input. Also, the switch circuit 1
Since 7 is turned off and the switch circuit 19 is turned on, the voltage V3 is input to the negative-phase input terminal 28b of the differential amplifier 28. Also, since the switch circuits 22 and 23 are turned on,
As a difference voltage between the two input terminals of the differential amplifier 29,
A voltage obtained by multiplying the gain of the differential amplifier 28 is input. Further, since the switch circuits 26 and 27 are also turned on, a voltage obtained by multiplying the gain of the differential amplifier 29 between the two input terminals of the comparison circuit 30, that is, the product α of the gains of both the differential amplifier 28 and the differential amplifier 29. The voltage (V1-
V2) · α is input. The comparison circuit 30 compares the input voltage with the reference voltage based on the input voltage, and outputs the comparison result from the terminals 31 and 32.

As described above, in the comparator of this embodiment, the switch circuits 24 and 25 connect and disconnect the two output terminals of the differential amplifier 28 and the two input terminals of the differential amplifier 29. The adverse effect of the Miller effect of the input stage transistors forming the differential amplifier 29 on the signal from the differential amplifier 28 is reduced. Therefore, the voltage of the differential amplifier 29 is settled at high speed. The switch circuits 24 and 25 are also provided to settle the voltage of the differential amplifier 29 at high speed, and when the switch circuits 24 and 25 are turned on, the gate capacitance of the input stage of the differential amplifier 29 is set to a predetermined value. Since it is charged to the voltage of
When 2 and 23 are turned on, it takes only a short time to charge the gate capacitance of the input stage of the differential amplifier 29 by the voltage output from the differential amplifier 28, and the voltage of the differential amplifier 29 is settled at high speed. To be done.

Here, the switch circuits 20, 21, 24
When 25 is turned on, the differential amplifier 28 and the differential amplifier 29
If the output voltages from the two are set to be the voltage V3, the voltage V3 appears at the two input terminals of the differential amplifier 29 when the switch circuits 22 and 23 are turned on next, so that the differential voltage is generated. The voltage output from the amplifier 28 is
The voltage V3 is input to the differential amplifier 29. Therefore, the voltage of the differential amplifier 29 is settled to a predetermined voltage at a higher speed.

FIG. 2 is a circuit diagram showing an example of the case where the comparator shown in FIG. 1 is composed of MOS transistors. still,
The same components as those of the comparator shown in FIG. 1 are designated by the same reference numerals and different points will be described. The differential amplifier 28 shown in FIG. 2 includes a current-source PMOS transistor 54 and an NMOS transistor 59 to which a bias voltage signal is input via terminals 45 and 44, and a differential output that is diode-connected to output a differential voltage signal. It is composed of PMOS transistors 55 and 56, and differential input NMOS transistors 57 and 58 to which a differential voltage signal is input.

The differential amplifier 29 includes resistance NMOS transistors 66 and 67 to which a bias voltage signal is input via a terminal 46, and differential output PMOS transistors 64 and 65 that are diode-connected and output a differential voltage signal. , Differential input NMOS transistors 68 and 69 to which the differential voltage signal is input, current source NMOS transistors 70 and 71 to input the self-bias voltage signal, and differential output PM
An NMOS transistor 74 for inputting the voltage signal output from the OS transistor 64 and a gate for differential input N
An NMOS transistor 75, which is connected to the drain of the MOS transistor 69 and receives a self-bias voltage signal having a phase opposite to the voltage signal output from the differential output PMOS transistor 64, and the differential output PMOS transistor 6
5 is a self-bias voltage having a phase opposite to that of the NMOS transistor 76 for inputting the voltage signal output from the output terminal 5 and the voltage signal output from the differential output PMOS transistor 65 with the gate connected to the drain of the differential input NMOS transistor 68. It is composed of an NMOS transistor 77 which receives a signal.

The comparison circuit 30 uses the first clock signal φ1.
Inverter 86 to which is input, NMOS transistor 8
5, a PMOS transistor 80 to which the first clock signal φ1 is input via the inverter 86, and PM
OS transistors 81 and 82, NMOS transistor 8
And a flip-flop composed of 3,84. The switch circuit 1 which is the first switch circuit group
6, 17, 20, 21, 24, 25, and switch circuits 18, 19, 22, 2 that are the second switch circuit group.
Reference numerals 3, 26 and 27 are each composed of an NMOS transistor.

Here, the input voltage signal V1 and the reference voltage signal V2 are input to the terminals 10 and 11, and the terminals 12 and 1 are also connected.
The first clock signal φ having the “H” level and the second clock signal φ2 having the “L” level are input to the circuit 3. Then, the switch circuits 16, 17, 2 which are the first switch circuit group
0, 21, 24, 25 are turned on, and the switch circuits 18, 19, 22, 23, 26, 2 which are the second switch circuit group.
7 is turned off, so that the input voltage signal V1 input to the terminal 10 passes through the switch circuit 16 and the capacitive element 14
And the reference voltage signal V2 input to the terminal 11 is input to the capacitive element 15 via the switch circuit 17. Further, in the differential amplifier 28 having the pair of differential input NMOS transistors 57 and 58, the input and output sides are connected via the switch circuits 20 and 21, whereby a feedback operation is performed and a predetermined voltage V3 is output. It Therefore, the capacitive element 14 is charged with the voltage (V3-V1),
Further, the capacitor 15 is charged with the voltage (V3-V2). On the other hand, a pair of differential input NMOS transistors 6
In the differential amplifier 29 having 8, 69, PM for differential output
The output voltage signals from the OS transistors 64 and 65 are NM
It is input to the OS transistors 74 and 76 (first buffer circuit according to the invention). The output voltage signal is dropped by the resistance transistor NMOS transistors 66 and 67, and the voltage signal having a phase opposite to that of the voltage signal from the differential output PMOS transistors 64 and 65 is supplied to the NMOS transistors 75 and 77 (the present invention). The second buffer circuit).

Here, since the switch circuits 24 and 25 are turned on by the first clock signal φ1, the differential amplifier 29
The input / output voltage of is the voltage V4. Further, since the switch circuits 22, 23, 26, 27 are turned off by the second clock signal φ2, the differential amplifier 28 and the differential amplifier 29 operate independently. Here, the capacitance driven by the differential amplifier 28 is the capacitance of the capacitive elements 14 and 15 and the differential input NM.
Only the gate capacitance of the OS transistors 57 and 58,
The capacity driven by the differential amplifier 29 is NM for differential input.
Since there is only the gate capacitance of the OS transistors 68 and 69, the capacitance to be driven can be reduced and the differential amplifier 2
8. The current flowing through the differential amplifier 29 is reduced.

Next, the phases of the first clock signal φ1 and the second clock signal φ2 are inverted from each other, and the terminals 12, 13 are
, The first clock signal φ of the'L 'level and the second clock signal φ2 of the'H' level are input. Then, this time, the switch circuits 16 and 1 which are the first switch circuit group.
7, 20, 21, 24, 25 are turned off, and the switch circuits 18, 19, 22, 23, 2 which are the second switch circuit group.
6,27 turn on. Since the switch circuits 16 and 17 are turned off and the switch circuits 18 and 19 are turned on, the voltage (V3-V1 + V2) is input to the differential input NMOS transistor 57 of the differential amplifier 28, and the differential input NMOS is input.
The voltage V3 is input to the transistor 58. Further, since the switch circuits 22 and 23 are turned on, a voltage obtained by multiplying the gain of the differential amplifier 28 is input to the differential input NMOS transistors 68 and 69 which form the differential amplifier 29. Further, since the switch circuits 26 and 27 are turned on, the voltage obtained by multiplying the gain of the differential amplifier 29 in the comparison circuit 30 (where the product of the gains of the differential amplifier 28 and the differential amplifier 29 is α, is the voltage ( V1-V2) .alpha.) Is input. The comparison circuit 30 compares the input voltage with the reference voltage based on the input voltage, and outputs the comparison result from the terminals 31 and 32.

Here, N constituting the first buffer circuit
The voltage signals input to the gates of the MOS transistors 74 and 76 and the voltage signals input to the gates of the NMOS transistors 75 and 77 that form the second buffer circuit are input in opposite phase. Therefore, even a minute difference voltage signal can be greatly amplified.

Since the ON resistance of the NMOS transistors forming the switch circuit can be reduced by level-shifting the voltage signal to a signal in the low voltage range, the ON resistance of the NMOS transistors forming the switch circuits 26 and 27 and the comparison circuit 30. The CR product with the input capacitance of can be made small, and therefore the settling time can be shortened. further,
If the input / output voltage V4 fed back by the switch circuits 24 and 25 is designed to substantially match the feedback voltage V3 of the differential amplifier 28, when the switch circuits 22 and 23 are turned on, the voltage from the differential amplifier 28 is changed. Since the output voltage is input to the differential amplifier 29 centered on the voltage V3, the settling time is further shortened.

Next, when the phases of the first clock signal φ1 and the second clock signal φ2 are inverted again with respect to each other, the terminals 12 and 13 respectively have the first clock signals φ and ′ at the “H” level. The second clock signal φ2 at L ′ level is input. Then, the switch circuits 26 and 27 are turned off by the second clock signal φ2 at the'L 'level, while'
The comparison circuit 3 receives the H'level first clock signal φ1.
Since both the PMOS transistor 80 and the NMOS transistor 85 forming 0 are turned on, the flip-flop constituted by the PMOS transistors 81 and 82 and the NMOS transistors 83 and 84 operates, and the flip-flop operates to input the input voltage and the reference voltage. The size of is compared,
The comparison result is output from the terminals 31 and 32 via the inverters 87 and 88.

As described above, in the comparator of this embodiment, the currents flowing through the differential amplifier 28 and the differential amplifier 29 are reduced, so that the differential input NMOS transistors 57 and 58 of the differential amplifier 28 and the differential amplifier. 29 differential input NMOs
Even if the transistor ratio W / L (gate width / gate length) of the S transistors 68 and 69 is reduced, a sufficient gain can be obtained. Therefore, the offsets of the differential amplifier 28 and the differential amplifier 29 can be reduced, and high accuracy can be guaranteed without adding offset removing means.

[0034]

As described above, according to the present invention,
Since the output side of the first-stage circuit and the input side of the latter-stage circuit are connected / disconnected by the switch circuit, the voltage can be settled at high speed, and the circuit operation can be speeded up and power consumption can be reduced.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an embodiment of a comparator of the present invention.

FIG. 2 is a circuit diagram showing an example of a case where the comparator shown in FIG. 1 is composed of MOS transistors.

FIG. 3 is a configuration diagram of a conventional comparator.

FIG. 4 is a circuit diagram when each differential amplifier shown in FIG. 3 is configured by MOS transistors.

5 is a circuit diagram when the comparison circuit shown in FIG. 3 is configured by MOS transistors.

[Explanation of symbols]

10, 11, 12, 13, 31, 32, 44, 45, 4
6 terminals 14 and 15 capacitive elements 16 to 27 switch circuits 28 and 28 differential amplifiers 28a, 29a and 30a anti-phase input terminals 28b, 29b and 30b in-phase input terminals 28c and 29c anti-phase output terminals 28d and 29d in-phase output terminal 30 comparison Circuits 54 to 56, 64, 65, 80 to 82 PMOS transistors 57 to 59, 66 to 71, 74 to 77, 83 to 85 N
MOS transistor 87,88 Inverter

Claims (3)

[Claims] 1. A first differential amplifier having two input terminals, an anti-phase input terminal and an in-phase input terminal, and two output terminals, an anti-phase output terminal and an in-phase output terminal, and the first differential amplifier. A first switch circuit arranged between the negative phase input terminal and the negative phase output terminal of the dynamic amplifier; and a second switch circuit arranged between the common mode input terminal and the common phase output terminal of the first differential amplifier. First-stage circuit that outputs a differential voltage signal that represents a differential voltage between an input voltage and a reference voltage, two input terminals, a negative-phase input terminal and a common-mode input terminal, and a negative-phase output terminal and a common-mode output. A second differential amplifier having two output terminals, a third switch circuit arranged between the negative-phase input terminal and the negative-phase output terminal of the second differential amplifier, and A fourth switch disposed between the common mode input terminal and the common mode output terminal of the second differential amplifier. A second-stage circuit for inputting and amplifying a differential voltage signal, and two input terminals of a negative-phase input terminal and an in-phase input terminal. From these two input terminals, after being amplified by the second-stage circuit, Of the input voltage signal and the reference voltage signal from one end of the comparison circuit for comparing the magnitude of the input voltage and the reference voltage A fifth switch circuit that transmits to the other end of the input voltage signal and a reference voltage signal, which is different from the first voltage signal, and the other second voltage signal that is input from one end A sixth switch circuit freely transmitting to the other end; a first capacitive element arranged between the other end of the fifth switch circuit and a negative phase input terminal of the first differential amplifier; The other end of the sixth switch circuit and the first difference A second capacitive element arranged between the amplifier and a common-mode input terminal; one voltage signal of the first voltage signal and the second voltage signal is input from one end and the other end is connected and disconnected freely A seventh switch circuit having the other end connected to the other end of the fifth switch circuit, the one voltage signal being input from one end and being disconnectably connected to the other end, An eighth switch circuit having the other end connected to the other end of the sixth switch circuit, a negative phase output terminal of the first differential amplifier and a negative phase input terminal of the second differential amplifier A ninth switch circuit arranged between the common mode output terminal of the first differential amplifier and a common mode input terminal of the second differential amplifier; Between the negative-phase output terminal of the second differential amplifier and the negative-phase input terminal of the comparison circuit An eleventh switch circuit, a twelfth switch circuit arranged between an in-phase output terminal of the second differential amplifier and an in-phase input terminal of the comparison circuit, and the first, second and third switch circuits. A first switch circuit group including third, fourth, fifth and sixth switch circuits;
The seventh, eighth, ninth, tenth, eleventh, and twelfth
And a switch control circuit for controlling the second switch circuit group including the switch circuit with the first clock signal and the second clock signal having mutually opposite phases. 2. The pair of differential input MOS transistors, wherein the second differential amplifier constitutes two input terminals of the second differential amplifier, and the sources of the pair of differential input MOS transistors. And a pair of self-biased current source MOS transistors having a gate connected to the drains of the pair of differential input MOS transistors, the source being connected to the power supply. A pair of differential output MOS transistors whose gates and drains are commonly connected, and a bias voltage applied to the gate between the pair of differential output MOS transistors and the pair of differential input MOS transistors. And a differential circuit including a pair of resistance MOS transistors to which is input, and two output terminals of the second differential amplifier. A first buffer circuit including a pair of MOS transistors having a drain connected to a power source and a gate connected to a connection point between the gate and the drain of the pair of differential output MOS transistors, and the first buffer circuit 2. A pair of buffer circuits comprising a second buffer circuit formed between a pair of MOS transistors whose gate is connected to the source of the resistance MOS transistor and which is arranged between the resistor and the ground. The described comparator. 3. The first differential amplifier and the second differential amplifier each constitutes the second switch circuit group when each of the switch circuits constituting the first switch circuit group is closed. When the switch circuit is open, the voltage appearing at the negative phase output terminal and the common mode output terminal of the first differential amplifier, and the negative phase input terminal and the common phase input terminal of the second differential amplifier are 2. The comparator according to claim 1, wherein the voltages that appear are adjusted to be substantially the same voltage.