JPH09307141A - Group iii nitride semiconductor light emitting element - Google Patents
Group iii nitride semiconductor light emitting elementInfo
- Publication number
- JPH09307141A JPH09307141A JP14835096A JP14835096A JPH09307141A JP H09307141 A JPH09307141 A JP H09307141A JP 14835096 A JP14835096 A JP 14835096A JP 14835096 A JP14835096 A JP 14835096A JP H09307141 A JPH09307141 A JP H09307141A
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- Prior art keywords
- layer
- protective film
- light emitting
- nitride semiconductor
- group iii
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、製造が簡単で静電
耐圧を向上させた３族窒化物半導体を用いた発光素子に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a light emitting device using a group III nitride semiconductor which is easy to manufacture and has improved electrostatic breakdown voltage.
【０００２】[0002]
【従来技術】従来、３族窒化物半導体を用いた青色発光
の発光素子が知られている。この発光素子では、素子の
表面上にSiO2から成る保護膜が形成されている。そし
て、この保護膜の形成においては、完全な絶縁性を得る
ために、ＰＶＤ法やＣＶＤ法との煩雑で時間のかかる方
法が採用されている。2. Description of the Related Art Conventionally, a blue light emitting device using a group III nitride semiconductor has been known. In this light emitting device, a protective film made of SiO 2 is formed on the surface of the device. In forming this protective film, a complicated and time-consuming method, which is different from the PVD method or the CVD method, is adopted in order to obtain perfect insulation.
【０００３】[0003]
【発明が解決しようとする課題】よって、発光素子の製
造が煩雑となり、製造に時間がかかるという問題があ
る。又、高温で保護膜を形成する場合には、発光素子の
エピタキャル成長層に悪影響を与え、素子特性が劣化し
たり、素子寿命が短くなるという問題がある。さらに、
半導体発光素子に関しては、静電耐圧の向上が必要な課
題となっている。Therefore, there is a problem that the manufacturing of the light emitting device becomes complicated and the manufacturing takes time. Further, when the protective film is formed at a high temperature, it has a bad influence on the epitaxy growth layer of the light emitting device, resulting in deterioration of device characteristics and shortening of device life. further,
With respect to semiconductor light emitting elements, there is a need to improve electrostatic breakdown voltage.
【０００４】本発明は、上記の課題を解決するために成
されたものであり、その目的は、素子特性を劣化させる
ことなく、製造を容易にすると共に、静電耐圧を向上さ
せることである。The present invention has been made to solve the above problems, and an object thereof is to facilitate manufacture and improve electrostatic breakdown voltage without deteriorating element characteristics. .
【０００５】[0005]
【課題を解決するための手段】本発明は、３族窒化物半
導体から成る少なくともｐ層とｎ層とが積層され、上層
の一部を除去して、下層の電流供給層の一部を露出さ
せ、最上層及び前記電流供給層の露出部分に電極を形成
した発光素子において、発光素子の表面上に、比抵抗0.
1 Ωcm〜1 ×105 Ωcmの保護膜を形成したことを特徴と
する。0.1 Ωcmより小さいと、ｐ層とｎ層間の絶縁効果
が低下するので望ましくなく、1 ×105 Ωcmより大きい
場合には、高温で形成したり、ＰＶＤ、ＣＶＤ法等の煩
雑な方法で形成する必要があると共に、逆方向の静電耐
圧の向上の効果がなくなるので望ましくない。According to the present invention, at least a p-layer and an n-layer made of a group 3 nitride semiconductor are laminated, a part of an upper layer is removed, and a part of a lower current supply layer is exposed. Then, in the light emitting element in which electrodes are formed on the exposed portion of the uppermost layer and the current supply layer, a specific resistance of 0.
A protective film having a thickness of 1 Ωcm to 1 × 10 5 Ωcm is formed. If it is smaller than 0.1 Ωcm, the insulating effect between the p layer and the n layer is deteriorated, which is not desirable, and if it is larger than 1 × 10 5 Ωcm, it is formed at a high temperature, or is formed by a complicated method such as PVD or CVD. This is not desirable because it is necessary and the effect of improving the electrostatic withstand voltage in the opposite direction is lost.
【０００６】ここで、保護膜は、望ましくは、金属アル
コレート（Ｍ−ＯＲ）又は珪素化合物を有機溶剤又は水
に溶かした溶液を塗布後、加熱乾燥して得られる膜であ
り、その厚さは、300 Å〜3 μｍである。さらに、望ま
しくは、保護膜は、電極間の保護膜を通る経路の保護膜
抵抗と電極間のｐ層とｎ層を通る駆動電流経路の素子抵
抗との関係において、順方向電圧に対して、保護膜抵抗
は素子抵抗よりも十分に大きく、逆方向電圧に対して、
保護膜抵抗は素子抵抗よりも十分に小さくなるように形
成されている。Here, the protective film is preferably a film obtained by applying a solution of a metal alcoholate (M-OR) or a silicon compound in an organic solvent or water, followed by heating and drying, and its thickness. Is 300 Å to 3 μm. Further preferably, the protective film has a relationship between a protective film resistance of a path passing through the protective film between the electrodes and a device resistance of a drive current path passing through the p layer and the n layer between the electrodes, with respect to a forward voltage, The protective film resistance is sufficiently larger than the element resistance, and for the reverse voltage,
The protective film resistance is formed to be sufficiently smaller than the element resistance.
【０００７】[0007]
【発明の作用及び効果】保護膜を比抵抗0.1 Ωcm〜1 ×
105 Ωcmの範囲で形成している。このため、この保護膜
は、ＰＶＤ、ＣＶＤ法等の煩雑な方法を用いずに、例え
ば、金属アルコレート（Ｍ−ＯＲ）又は珪素化合物を有
機溶剤又は水に溶かした溶液を塗布後、加熱乾燥するこ
とで得られる。よって、製造が簡単となる。又、高温加
熱が必要でないので、素子特性を劣化させ、素子寿命を
短くすることが防止される。又、保護膜を比抵抗が0.1
Ωcm〜1 ×105 Ωcmの範囲となるように形成すること
で、順方向電圧に対して、保護膜抵抗は素子抵抗よりも
十分に大きく、逆方向電圧に対して、保護膜抵抗は素子
抵抗よりも十分に小さくなるように形成できる。従っ
て、この発光素子の逆方向の静電耐圧を向上させること
ができる。[Advantages and effects of the invention] The protective film has a specific resistance of 0.1 Ωcm to 1 ×.
It is formed in the range of 10 5 Ωcm. Therefore, this protective film is applied with a solution in which a metal alcoholate (M-OR) or a silicon compound is dissolved in an organic solvent or water without applying a complicated method such as PVD or CVD method, and then dried by heating. It is obtained by doing. Therefore, manufacturing becomes simple. Further, since high temperature heating is not necessary, deterioration of element characteristics and shortening of element life can be prevented. Also, the protective film has a specific resistance of 0.1.
By forming it in the range of Ωcm to 1 × 10 5 Ωcm, the protective film resistance is sufficiently larger than the element resistance with respect to the forward voltage and the protective film resistance with respect to the reverse voltage. Can be formed to be sufficiently smaller than Therefore, the electrostatic breakdown voltage of the light emitting element in the reverse direction can be improved.
【０００８】[0008]
【実施例】以下、本発明を具体的な実施例に基づいて説
明する。なお本発明は下記実施例に限定されるものでは
ない。図１は本願実施例の発光素子100 全体図を示す。
発光素子100 は、サファイア基板１を有しており、その
サファイア基板１上に0.05μｍのAlN バッファ層２が形
成されている。EXAMPLES The present invention will be described below based on specific examples. The present invention is not limited to the following examples. FIG. 1 shows an overall view of the light emitting device 100 according to the embodiment of the present invention.
The light emitting device 100 has a sapphire substrate 1, and a 0.05 μm AlN buffer layer 2 is formed on the sapphire substrate 1.
【０００９】そのバッファ層２の上には、順に、膜厚約
4.0 μｍ、電子濃度2 ×1018/cm3のシリコン(Si)ドープ
GaN から成る高キャリア濃度ｎ+ 層３、膜厚約0.5 μｍ
の電子濃度5 ×1017/cm3のシリコン(Si)ドープのGaN か
ら成るｎ層４、膜厚約100 ｎｍ，亜鉛(Zn)とシリコン(S
i)がそれぞれ、 5×1018/cm3にドープされたIn0.20Ga
0.80N から成る発光層５，膜厚約100 ｎｍ，ホール濃度
2×1017/cm3, マグネシウム（Mg) 濃度 5×1019/cm3ド
ープのAl0.09Ga0.92N から成るｐ伝導型のクラッド層
６、膜厚約200 ｎｍ，ホール濃度 3×1017/cm3のマグネ
シウム（Mg) 濃度 5×1019/cm3ドープのGaN から成る第
１コンタクト層７１、膜厚約50ｎｍ，ホール濃度 6×10
17/cm3のマグネシウム（Mg) 濃度 1×1020/cm3ドープの
GaN から成るｐ+ の第２コンタクト層７２が形成されて
いる。On the buffer layer 2, a film thickness of about
4.0 μm, silicon (Si) doped with 2 × 10 18 / cm 3 electron concentration
High carrier concentration n + layer 3 made of GaN, thickness about 0.5 μm
N layer 4 of GaN doped with silicon (Si) having an electron concentration of 5 × 10 17 / cm 3 , a film thickness of about 100 nm, zinc (Zn) and silicon (S
i) are each doped with 5 × 10 18 / cm 3 of In 0.20 Ga
Emitting layer composed of 0.80 N, thickness about 100 nm, hole concentration
2 × 10 17 / cm 3 , magnesium (Mg) concentration 5 × 10 19 / cm 3 p-conductivity type clad layer 6 made of Al 0.09 Ga 0.92 N, film thickness about 200 nm, hole concentration 3 × 10 17 / cm 3 magnesium (Mg) concentration 5 × 10 19 / cm 3 first contact layer 71 made of GaN, film thickness about 50 nm, hole concentration 6 × 10
17 / cm 3 magnesium (Mg) concentration 1 × 10 20 / cm 3 doped
A p + second contact layer 72 of GaN is formed.
【００１０】そして、第２コンタクト層７２の上面全体
にNiから成る厚さ25Åの第１電極層８１が形成され、そ
の第１電極層８１の上にAuから成る厚さ60Åの第２電極
層８２が形成されている。この第１電極層８１と第２電
極層８２とでｐ型GaN に対する電極層８が構成される。
この電極層８は透明である。又、第２電極層８２の上面
の隅の部分にNiから成る厚さ1000Åの第１金属層９１、
Auから成る厚さ1.5 μｍの第２金属層９２、Alから成る
厚さ300 Åの第３金属層９３が形成されている。この３
重層により、電極パッド９が形成されている。一方、ｎ
+ 層３上にはAlから成る電極パッド１０が形成されてい
る。そして、電極パッド９と電極パッド１０のワイヤボ
ンディングされる領域に窓９Ａと窓１０Ａが形成された
SiO2から成る保護膜１１が基板１の最上層上に形成され
ている。A first electrode layer 81 made of Ni and having a thickness of 25 Å is formed on the entire upper surface of the second contact layer 72, and a second electrode layer made of Au and having a thickness of 60 Å is formed on the first electrode layer 81. 82 is formed. The first electrode layer 81 and the second electrode layer 82 form the electrode layer 8 for p-type GaN.
This electrode layer 8 is transparent. In addition, the first metal layer 91 made of Ni and having a thickness of 1000 Å is formed on the corner of the upper surface of the second electrode layer 82
A second metal layer 92 made of Au and having a thickness of 1.5 μm, and a third metal layer 93 made of Al and having a thickness of 300 Å are formed. This 3
The electrode pad 9 is formed of multiple layers. On the other hand, n
An electrode pad 10 made of Al is formed on the + layer 3. Then, the window 9A and the window 10A were formed in the area of the electrode pad 9 and the electrode pad 10 to be wire-bonded.
A protective film 11 made of SiO 2 is formed on the uppermost layer of the substrate 1.
【００１１】次に、この構造の半導体素子の製造方法に
ついて説明する。上記発光素子100 は、有機金属気相成
長法（以下ＭＯＶＰＥ）による気相成長により製造され
た。用いられたガスは、アンモニア(NH3) 、キャリアガ
ス（H2）、トリメチルガリウム(Ga(CH3)3)（以下「TMG
」と記す) 、トリメチルアルミニウム(Al(CH3)3)（以
下「TMA 」と記す) 、トリメチルインジウム(In(CH3)3)
（以下「TMI 」と記す) 、シラン(SiH4)、ジエチル亜鉛
(Zn(C2H5)2)(以下、「DEZ 」と記す) とシクロペンタジ
エニルマグネシウム(Mg(C5H5)2)(以下「CP2Mg 」と記
す）である。Next, a method of manufacturing a semiconductor device having this structure will be described. The light emitting device 100 was manufactured by vapor phase growth using metal organic chemical vapor deposition (hereinafter, MOVPE). The gases used were ammonia (NH 3 ), carrier gas (H 2 ), and trimethylgallium (Ga (CH 3 ) 3 ) (hereinafter “TMG
), Trimethyl aluminum (Al (CH 3 ) 3 ) (hereinafter referred to as “TMA”), trimethyl indium (In (CH 3 ) 3 )
(Hereinafter referred to as “TMI”), silane (SiH 4 ), diethylzinc
(Zn (C 2 H 5 ) 2 ) (hereinafter referred to as “DEZ”) and cyclopentadienyl magnesium (Mg (C 5 H 5 ) 2 ) (hereinafter referred to as “CP 2 Mg”).
【００１２】まず、有機洗浄及び熱処理により洗浄した
ａ面を主面とし、単結晶のサファイア基板１をM0VPE 装
置の反応室に載置されたサセプタに装着する。次に、常
圧でH2を流速2 liter/分で約30分間反応室に流しながら
温度1100℃でサファイア基板１をベーキングした。First, a single-crystal sapphire substrate 1 is mounted on a susceptor placed in a reaction chamber of an MOVPE apparatus, with the a-plane cleaned by organic cleaning and heat treatment as a main surface. Next, the sapphire substrate 1 was baked at a temperature of 1100 ° C. while flowing H 2 into the reaction chamber at a flow rate of 2 liter / min at normal pressure for about 30 minutes.
【００１３】次に、温度を 400℃まで低下させて、H2を
20 liter／分、NH3 を10 liter／分、TMA を 1.8×10-5
モル／分で約90秒間供給してAlN のバッファ層２を約0.
05μｍの厚さに形成した。次に、サファイア基板１の温
度を1150℃に保持し、H2を20liter／分、NH3 を10 lite
r／分、TMG を 1.7×10-4モル／分、H2ガスにより0.86p
pm に希釈されたシランを20×10-8モル／分で40分導入
し、膜厚約4.0 μｍ、電子濃度 1×1018/cm3、シリコン
濃度 4×1018/cm3のシリコン(Si)ドープGaN から成る高
キャリア濃度ｎ+ 層３を形成した。[0013] Next, by lowering the temperature to 400 ° C., and H 2
20 liter / min, NH 3 10 liter / min, TMA 1.8 × 10 -5
The AlN buffer layer 2 was supplied at about 0.1 mol / min for about 90 seconds.
It was formed to a thickness of 05 μm. Next, the temperature of the sapphire substrate 1 was maintained at 1150 ° C., H 2 was 20 liter / min, and NH 3 was 10 lite.
r / min, TMG 1.7 × 10 -4 mol / min, 0.86p by H 2 gas
Silane diluted at 20 × 10 −8 mol / min was introduced for 40 minutes at a film thickness of about 4.0 μm, an electron concentration of 1 × 10 18 / cm 3 , and a silicon concentration of 4 × 10 18 / cm 3 (Si). 3.) A high carrier concentration n + layer 3 made of doped GaN was formed.
【００１４】上記の高キャリア濃度ｎ+ 層３を形成した
後、続いて温度を1100°C に保持し、H2を20 liter／
分、NH3 を10 liter／分、TMG を 1.12 ×10-4モル／
分、H2ガスにより0.86ppm に希釈されたシランを10×10
-9モル／分で30分導入し、膜厚約5.0 μｍ、電子濃度 5
×1017/cm3、シリコン濃度 1×1018/cm3のシリコン(Si)
ドープGaN から成るｎ層４を形成した。After forming the high carrier concentration n + layer 3, the temperature is maintained at 1100 ° C. and H 2 is reduced to 20 liter / hour.
Min, NH 3 at 10 liter / min, TMG at 1.12 × 10 -4 mol / min
Min, silane to 10 × 10 diluted to 0.86ppm with H 2 gas
Introduced at -9 mol / min for 30 minutes, film thickness about 5.0 μm, electron concentration 5
× 10 17 / cm 3 , silicon (Si) with a silicon concentration of 1 × 10 18 / cm 3
An n layer 4 made of doped GaN was formed.
【００１５】続いて、温度を800 ℃に保持し、N2又はH2
を20 liter／分、NH3 を10 liter／分、TMG を0.2 ×10
-4モル／分、TMI を1.6 ×10-4モル／分、H2ガスにより
0.86ppm に希釈されたシランを10×10-8mol/分で、DEZ
を 2×10-4モル/ 分で、30分間供給して厚さ100nm のシ
リコンと亜鉛が、それぞれ、 5×1018/cm3にドープさた
In0.20Ga0.80N から成る発光層５を形成した。Subsequently, the temperature was kept at 800 ° C. and N 2 or H 2 was added.
20 liter / min, NH 3 10 liter / min, TMG 0.2 × 10
-4 mol / min, TMI 1.6 × 10 -4 mol / min, by H 2 gas
Silane diluted to 0.86 ppm at 10 × 10 -8 mol / min, DEZ
Was supplied at a rate of 2 × 10 −4 mol / min for 30 minutes, and silicon and zinc having a thickness of 100 nm were doped to 5 × 10 18 / cm 3 , respectively.
The light emitting layer 5 made of In 0.20 Ga 0.80 N was formed.
【００１６】続いて、温度を1100℃に上げて、N2又はH2
を20 liter／分、NH3 を10 liter／分、TMG を1.12×10
-4モル／分、TMA を0.47×10-4モル／分、及び、CP2Mg
を2×10-5モル／分で 6分間導入し、膜厚約100 ｎｍの
マグネシウム(Mg)ドープのAl0.08Ga0.92N から成るクラ
ッド層６を形成した。クラッド層６のマグネシウム濃度
は 5×1019/cm3である。この状態では、クラッド層６
は、まだ、抵抗率108 Ωcm以上の絶縁体である。Subsequently, the temperature is raised to 1100 ° C. and N 2 or H 2 is added.
20 liter / min, NH 3 10 liter / min, TMG 1.12 × 10
-4 mol / min, 0.47 × 10 -4 mol / min of TMA and CP 2 Mg
Was introduced at 2 × 10 −5 mol / min for 6 minutes to form a cladding layer 6 made of magnesium (Mg) -doped Al 0.08 Ga 0.92 N and having a thickness of about 100 nm. The magnesium concentration of the cladding layer 6 is 5 × 10 19 / cm 3 . In this state, the cladding layer 6
Is an insulator having a resistivity of 10 8 Ωcm or more.
【００１７】次に、温度を1100℃に保持し、N2又はH2を
20 liter／分、NH3 を10 liter／分、TMG を1.12×10-4
モル／分、及び、CP2Mg を 2×10-5モル／分で 1分間導
入し、膜厚約200 ｎｍのマグネシウム(Mg)ドープのGaN
から成る第１コンタクト層７１を形成した。第１コンタ
クト層７１のマグネシウム濃度は 5×1019/cm3である。
この状態では、第１コンタクト層７１は、まだ、抵抗率
108 Ωcm以上の絶縁体である。Next, the temperature is maintained at 1100 ° C., and N 2 or H 2 is added.
20 liter / min, NH 3 is 10 liter / min, TMG is 1.12 × 10 -4
Mol / min, and CP 2 Mg was introduced at 2 × 10 -5 mol / min for 1 minute, and magnesium (Mg) -doped GaN with a film thickness of about 200 nm
The first contact layer 71 made of was formed. The magnesium concentration of the first contact layer 71 is 5 × 10 19 / cm 3 .
In this state, the first contact layer 71 still has the resistivity
It is an insulator of 10 8 Ωcm or more.
【００１８】次に、温度を1100℃に保持し、N2又はH2を
20 liter／分、NH3 を10 liter／分、TMG を1.12×10-4
モル／分、及び、CP2Mg を 4×10-5モル／分で3 分間導
入し、膜厚約50ｎｍのマグネシウム(Mg)ドープのGaN か
ら成るｐ+ の第２コンタクト層７２を形成した。第２コ
ンタクト層７２のマグネシウム濃度は 1×1020/cm3であ
る。この状態では、第２コンタクト層７２は、まだ、抵
抗率108 Ωcm以上の絶縁体である。Next, the temperature was maintained at 1100 ° C. and N 2 or H 2 was added.
20 liter / min, NH 3 is 10 liter / min, TMG is 1.12 × 10 -4
Mol / min and CP 2 Mg were introduced at 4 × 10 −5 mol / min for 3 minutes to form a p + second contact layer 72 of magnesium (Mg) -doped GaN having a thickness of about 50 nm. The magnesium concentration of the second contact layer 72 is 1 × 10 20 / cm 3 . In this state, the second contact layer 72 is still an insulator having a resistivity of 10 8 Ωcm or more.
【００１９】次に、反射電子線回折装置を用いて、第２
コンタクト層７２，第１コンタクト層７１，及びクラッ
ド層６に一様に電子線を照射した。電子線の照射条件
は、加速電圧約10KV、資料電流１μＡ、ビームの移動速
度0.2mm/sec 、ビーム径60μｍφ、真空度5.0 ×10-5To
rrである。この電子線の照射により、第２コンタクト層
７２，第１コンタクト層７１，クラッド層６は、それぞ
れ、ホール濃度 6×1017/cm3,3×1017/cm3,2×1017/c
m3、抵抗率 2Ωcm, 1 Ωcm,0.7Ωcmのｐ伝導型半導体と
なった。このようにして多層構造のウエハが得られた。Next, using a reflection electron beam diffractometer, the second
The contact layer 72, the first contact layer 71, and the cladding layer 6 were uniformly irradiated with an electron beam. The electron beam irradiation conditions are: accelerating voltage of about 10 KV, material current of 1 μA, beam moving speed of 0.2 mm / sec, beam diameter of 60 μmφ, vacuum degree of 5.0 × 10 −5 To.
rr. By this electron beam irradiation, the second contact layer 72, the first contact layer 71, and the cladding layer 6 have hole concentrations of 6 × 10 17 / cm 3 , 3 × 10 17 / cm 3 , 2 × 10 17 / c, respectively.
It became a p-conduction type semiconductor having m 3 and resistivity of 2Ωcm, 1Ωcm, 0.7Ωcm. Thus, a wafer having a multilayer structure was obtained.
【００２０】続いて、ｎ+ 層３の電極パッド１０を形成
するために、第２コンタクト層７２、第１コンタクト層
７１、クラッド層６、発光層５、ｎ層４の一部を、エッ
チングにより除去した。Subsequently, in order to form the electrode pad 10 of the n + layer 3, a part of the second contact layer 72, the first contact layer 71, the cladding layer 6, the light emitting layer 5 and the n layer 4 is etched. Removed.
【００２１】次に、10-7Torr程度の高真空にて、一様
に、厚さ25ÅにNiを蒸着し、続いて、厚さ60ÅにAuを蒸
着し、フォトレジストの塗布、フォトリソグラフィー工
程、エッチング工程を経て、第２コンタクト層７２の上
に第１電極層８１、第２電極層８２を形成した。これに
より、Ni/Au の透明な電極層８が形成された。そして、
電極パッド９を形成する領域を除いて最上層の全面にレ
ジストを塗布して、10-7Torr程度の高真空にて、Ni、A
u、Alを、順次、厚さ、1000Å、1.5 μｍ、300 Åに蒸
着した。その後、レジストをリフトオフすることで、必
要な箇所に第１金属層９１、第２金属層９２、第３金属
層９３を形成した。このようにして、３層構造の電極パ
ッド９を形成した。一方、ｎ+ 層３に対しては、Alを蒸
着して電極パッド１０を形成した。Next, Ni is vapor-deposited uniformly to a thickness of 25 Å in a high vacuum of about 10 -7 Torr, and then Au is vapor-deposited to a thickness of 60 Å to apply a photoresist and perform a photolithography process. Then, the first electrode layer 81 and the second electrode layer 82 were formed on the second contact layer 72 through the etching process. As a result, a transparent electrode layer 8 of Ni / Au was formed. And
Except for the region for forming the electrode pads 9 by coating a resist on the uppermost layer of the entire surface at a high vacuum of about 10 -7 Torr, Ni, A
u and Al were sequentially evaporated to a thickness of 1000 °, 1.5 μm, and 300 °. Thereafter, the first metal layer 91, the second metal layer 92, and the third metal layer 93 were formed at necessary places by lifting off the resist. Thus, the electrode pad 9 having a three-layer structure was formed. On the other hand, the electrode pad 10 was formed on the n + layer 3 by depositing Al.
【００２２】次に、上記の基板１を加熱炉に配設し、加
熱炉の雰囲気を１m Torr以下にまで排気し、その後大気
圧までN2で封入した。そして、その状態で雰囲気温度を
400℃〜700 ℃の範囲の温度に設定して、数秒〜10分程
度、基板１を加熱した。Next, the substrate 1 was placed in a heating furnace, the atmosphere in the heating furnace was evacuated to 1 m Torr or less, and then filled with N 2 to atmospheric pressure. And in that state, change the ambient temperature
The substrate 1 was heated at a temperature in the range of 400 ° C. to 700 ° C. for several seconds to 10 minutes.
【００２３】次に、上記のように形成された基板１の最
上層の上に一様に、エチルシリケート(Si(OC2H5)4)を主
成分とする溶液を塗布した後、300 〜400 ℃の範囲で加
熱して乾燥した。これにより、SiO2から成る膜が5000Å
の厚さに形成された。その後、フォトレジストの塗布、
フォトリソグラフィー工程、エッチング工程を経て、電
極パッド９、電極パッド１０のワイヤボンディング領域
に当たる部分のSiO2膜に窓９Ａ、窓１０Ａをドライエッ
チングにより形成した。このようにして、SiO2から成る
保護膜１１が形成された。Next, a solution containing ethyl silicate (Si (OC 2 H 5 ) 4 ) as a main component is uniformly applied on the uppermost layer of the substrate 1 formed as described above, and then 300- It was heated and dried in the range of 400 ° C. As a result, a film made of SiO 2 will be 5000 Å
Formed to a thickness of After that, apply photoresist,
After the photolithography process and the etching process, the windows 9A and 10A were formed by dry etching on the SiO 2 film in the portions corresponding to the wire bonding regions of the electrode pads 9 and 10. Thus, the protective film 11 made of SiO 2 was formed.
【００２４】第３金属層９３のAlと保護膜１１のSiO2と
は接合度が高いので、第３金属層９３と保護膜１１との
間にエッチング液が浸透することが防止される。よっ
て、保護膜１１のマスクされた部分はエッチングされな
いため、窓９Ａの側壁は垂直となる。この結果、保護膜
１１は第１金属層９１、第２金属層９２、第３金属層９
３の側面を完全に覆うことになり、保護膜として十分に
機能する。Since the Al of the third metal layer 93 and the SiO 2 of the protective film 11 have a high degree of bonding, the etching solution is prevented from penetrating between the third metal layer 93 and the protective film 11. Therefore, since the masked portion of the protective film 11 is not etched, the side wall of the window 9A becomes vertical. As a result, the protective film 11 includes the first metal layer 91, the second metal layer 92, and the third metal layer 9
Since the side surface of 3 is completely covered, it functions sufficiently as a protective film.
【００２５】この保護膜１１の比抵抗は2 ×104 Ωcmで
あった。又、電極パッド９と電極パッド１０との間の抵
抗は、順電圧に対して165 Ω、逆電圧に対して90ｋΩで
あった。保護膜１１がない場合の逆電圧に対する抵抗が
17ＭΩであるので、逆電圧に対して保護膜１１を介して
電流が流れるので、逆電圧に対する静電耐圧が向上する
のが分かる。又、逆方向静電圧20Ｖまで破壊されなかっ
た。The specific resistance of this protective film 11 was 2 × 10 4 Ωcm. The resistance between the electrode pad 9 and the electrode pad 10 was 165 Ω for the forward voltage and 90 kΩ for the reverse voltage. Resistance to reverse voltage without protective film 11
Since it is 17 MΩ, a current flows through the protective film 11 against a reverse voltage, so that it can be seen that the electrostatic breakdown voltage against the reverse voltage is improved. Also, it was not destroyed up to a reverse static voltage of 20V.
【００２６】尚、第３金属層９３は、保護膜１１に対す
る接合度が第２金属層９２の構成元素の金よりも強いも
のであれば良い。例えば、Alの他、Ni、Tiを用いること
ができる。保護膜１１は、上記のようにSiO2とする他、
TiO2, ZnS,MgF2, ZrO,Al2O3,Si3N4 等を用いることがで
きる。これらの膜は透明である。It should be noted that the third metal layer 93 may have a degree of bonding to the protective film 11 that is stronger than the constituent element gold of the second metal layer 92. For example, in addition to Al, Ni and Ti can be used. The protective film 11 is made of SiO 2 as described above,
TiO 2, ZnS, MgF 2, ZrO, Al 2 O 3, Si 3 N 4 and the like can be used. These membranes are transparent.
【００２７】尚、上記の保護膜１１の厚さは、300 Å〜
3 μｍが望ましい。300 Åより薄いと水分の侵入防止、
傷付き防止等の保護膜としての機能が低下し、3 μｍよ
り厚いと、透明性が損なわれるので望ましくない。又、
上記実施例では、発光ダイオードについて示したが、本
発明をレーザダイオードにも応用することができる。The protective film 11 has a thickness of 300 Å
3 μm is desirable. If it is thinner than 300Å
If it is thicker than 3 μm, the function as a protective film for preventing scratches is deteriorated, and transparency is impaired. or,
Although the light emitting diode is shown in the above embodiment, the present invention can be applied to a laser diode.
【図１】本発明の具体的な実施例に係る発光ダイオード
の構成を示した構成図。FIG. 1 is a configuration diagram showing a configuration of a light emitting diode according to a specific embodiment of the present invention.
１０…発光ダイオード １…サファイア基板 ２…バッファ層 ３…高キャリア濃度ｎ+ 層 ４…ｎ層 ５…発光層 ６１…ｐ層 ６２…コンタクト層 ７，８…電極10 ... Light emitting diode 1 ... Sapphire substrate 2 ... Buffer layer 3 ... High carrier concentration n + layer 4 ... N layer 5 ... Light emitting layer 61 ... P layer 62 ... Contact layer 7, 8 ... Electrode
Claims (4)
とｎ層とが積層され、上層の一部を除去して、下層の電
流供給層の一部を露出させ、最上層及び前記電流供給層
の露出部分に電極を形成した発光素子において、 前記発光素子の表面上に形成された、比抵抗0.1 Ωcm〜
1 ×105 Ωcmの保護膜を有することを特徴とする３族窒
化物半導体発光素子。1. At least a p-layer and an n-layer made of a Group III nitride semiconductor are laminated, a part of an upper layer is removed to expose a part of a lower current supply layer, and an uppermost layer and the current supply. In a light emitting device having an electrode formed on an exposed portion of a layer, a specific resistance formed on the surface of the light emitting device is 0.1 Ωcm to
A Group III nitride semiconductor light-emitting device having a protective film of 1 × 10 5 Ωcm.
Ｒ）又は珪素化合物を有機溶剤又は水に溶かした溶液を
塗布後、加熱乾燥して得られる膜であることを特徴とす
る請求項１に記載の３族窒化物半導体発光素子。2. The protective film is a metal alcoholate (MO).
2. The group III nitride semiconductor light emitting device according to claim 1, wherein the film is obtained by applying a solution of R) or a silicon compound dissolved in an organic solvent or water and then heating and drying.
ことを特徴とする請求項１に記載の３族窒化物半導体発
光素子。3. The Group III nitride semiconductor light emitting device according to claim 1, wherein the protective film has a thickness of 300 Å to 3 μm.
膜抵抗と前記電極間の前記ｐ層と前記ｎ層を通る駆動電
流経路の素子抵抗との関係において、順方向電圧に対し
て、前記保護膜抵抗は前記素子抵抗よりも十分に大き
く、逆方向電圧に対して、前記保護膜抵抗は前記素子抵
抗よりも十分に小さくなるように前記保護膜が形成され
ていることを特徴とする請求項１に記載の３族窒化物半
導体発光素子。4. A relationship between a protective film resistance of a path passing through the protective film between the electrodes and a device resistance of a drive current path passing through the p layer and the n layer between the electrodes with respect to a forward voltage. The protective film resistance is sufficiently larger than the element resistance, and the protective film is formed so that the protective film resistance is sufficiently smaller than the element resistance with respect to a reverse voltage. The Group III nitride semiconductor light emitting device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14835096A JP3596171B2 (en) | 1996-05-16 | 1996-05-16 | Group III nitride semiconductor light emitting device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14835096A JP3596171B2 (en) | 1996-05-16 | 1996-05-16 | Group III nitride semiconductor light emitting device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09307141A true JPH09307141A (en) | 1997-11-28 |
| JP3596171B2 JP3596171B2 (en) | 2004-12-02 |
Family
ID=15450805
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14835096A Expired - Fee Related JP3596171B2 (en) | 1996-05-16 | 1996-05-16 | Group III nitride semiconductor light emitting device |
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| Country | Link |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002021605A1 (en) * | 2000-09-04 | 2002-03-14 | Epivalley Co., Ltd. | The semiconductor led device and producing method |
| WO2013180204A1 (en) * | 2012-06-01 | 2013-12-05 | 三菱重工業株式会社 | Method and device for fabricating protective film for light emitting element |
-
1996
- 1996-05-16 JP JP14835096A patent/JP3596171B2/en not_active Expired - Fee Related
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2002021605A1 (en) * | 2000-09-04 | 2002-03-14 | Epivalley Co., Ltd. | The semiconductor led device and producing method |
| EP1320902A1 (en) * | 2000-09-04 | 2003-06-25 | Epivalley Co. Ltd | The semiconductor led device and producing method |
| US7053417B2 (en) | 2000-09-04 | 2006-05-30 | Epivalley Co., Ltd. | Semiconductor led device and producing method |
| EP1320902A4 (en) * | 2000-09-04 | 2006-10-04 | Epivalley Co Ltd | The semiconductor led device and producing method |
| WO2013180204A1 (en) * | 2012-06-01 | 2013-12-05 | 三菱重工業株式会社 | Method and device for fabricating protective film for light emitting element |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3596171B2 (en) | 2004-12-02 |
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