JPH09306185A - Semiconductor memory and its driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress dispersion of threshold voltage after two stages erasing operation in a non-volatile semiconductor memory to which electrically writable and erasable memory cells are mounted. SOLUTION: This device is provided with a leakage current discriminating circuit 12 constituted with a transistor Tr1 for pre-charge and an inverter Inv1 independently of a current detecting type sense amplifier 11, a column line BLn is switched so as to be connected to either of both circuits 11, 12 by a switching circuit SW constituted with transistors Tr3, Tr5 and Tr8. After drain stress is applied at the two stages erasing operation, transistors Tr1, Tr3 are turned on, a potential Vdd is supplied to the column lime BLn and they are pre-charged. Drain stress is applied little by little until a potential of the column line is not lowered to the prescribed value or less when the transistor Tr1 is turned off and a fixed time elapses. Thereby, a leak current is suppressed to the prescribed minute level, and threshold voltage of each memory is made uniform.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device which is electrically erasable and writable, and more particularly to an improvement in verify operation of a memory cell of a flash EEPROM.

[0002]

2. Description of the Related Art Non-volatile semiconductor memory devices, particularly flash EEPR capable of electrically erasing and writing data
In OM, it is important to design a control circuit for suppressing variations in threshold voltage of transistors in each memory cell after erasing data.

FIG. 6 shows a conventional general flash EEP.
It is a figure which shows the circuit structure of ROM. In the figure, MA
Is a memory cell M (i, j) (i = 1 to 1) composed of a double gate transistor having a floating gate and a control gate.
(m, j = 1 to n) are arranged in a matrix of m rows and n columns, and 7 is the memory cell array M
A column decoder for selecting the column A, 8 is a column decoder for selecting the row of the memory cell array MA, and 9 is each memory cell M (i, j) in the memory cell array MA.
Source potential control circuit for controlling the source potential of the column decoder 1, column decoder 7, column decoder 8 and source potential control circuit 9
Reference numeral 11 is a current detection type sense amplifier circuit used for reading data of each memory cell M (i, j) in the memory cell array MA. The control gate of each memory cell M (i, j) is connected to the row decoder 8 via each row line WL1, ..., WLm, and the source of each memory cell M (i, j) is connected to the source potential control circuit via the source line SLB. 9 are connected respectively. The drain of each memory cell M (i, j) is connected to each column line BL1, ...,
The column lines BL1, ...,
BLn are Nch transistors CTr1, ...,
It is connected to the sense amplifier circuit 11 and the column decoder 7 via CTrn. That is, each transistor CTr
Each source of 1, ..., CTrn is connected to each memory cell M (i,
Each of the transistors CTr1, ..., CT is connected to the drain of j).
Each gate of rn is connected to the column decoder 7 and each transistor CT.
The drains of r1, ..., CTrn are sense amplifier circuits 11
Connected to each other.

In the flash EEPROM having the above-described structure, a two-step erase operation (sequence) of data stored in the memory cell and a method of checking the completion of the erase operation will be described below. This two-step erasing operation is performed to ensure that the threshold voltage of the memory cell is set to a target value after the data in the memory cell is surely erased and before the data is written.

FIG. 7 is a flowchart showing the sequence of the two-step erase method used when erasing the data in the memory cell. However, before the erase operation shown in this flowchart, data is written in all the memory cells to raise the threshold voltage of the memory cells. Then, the following erase operation is performed from this state.

First, in step ST1, all memory cells are over-erased. In this step, the threshold voltages of all memory cells are lowered to a negative value so that data is surely erased.

Next, in step ST2, over-erase verification is performed on all the memory cells. In this step, the sense amplifier circuit 11 determines whether or not the overerasing of data in step ST1 is properly performed, and if the data is unacceptable, the process returns to step ST1.

Next, in step ST3, drain stress is applied to all memory cells. Here, shallow writing is performed so that the threshold voltages of all the memory cells have desired values.

Next, in step ST4, drain stress verification is performed on all the memory cells. here,
The current detection type sense amplifier circuit 11 determines whether or not the threshold voltage of all memory cells is equal to or higher than the drain stress verify voltage shown in FIG. 8C, and steps ST3 and ST4 are performed until this condition is satisfied. Repeat.

Here, in the above conventional verify operation,
The current detection type sense amplifier circuit 11 connected to the column line of the memory cell array via the column decoder 7 determines whether the leak current on the column line conforms to the reference. This is because this leak current flows between the source and drain of the selected memory cell, and if this leak current is large, erroneous reading of data may occur. However,
At the time of this judgment, it is not possible to judge a minute leak current which is less than the sensitivity of the sense amplifier circuit 11. This leak current tends to increase at a high temperature at a high temperature. Therefore, even in a memory cell confirmed to have no leak current at room temperature, a leak current exceeding the detection sensitivity of the sense amplifier circuit may occur at a high temperature. is there. Therefore, at the time of rewriting, it is necessary to raise the threshold voltage to the extent that a leak current smaller than the detection sensitivity is generated in anticipation of an increase in the usage state under high temperature.

Therefore, after the processes of steps ST1 to ST4 are performed, in step ST5, an additional drain stress is applied to all the memory cell column lines so that the leak current on the column lines causes the current detection type sense amplifier circuit 11 to leak. Set to a state where the value is considered to be a minute value below the detection sensitivity.

FIG. 8 is a cross-sectional view for explaining the voltage condition applied to the selected memory cell and its operation in the main steps of the two-step erase method. However, in the figure, 15 is a control gate, 16 is a floating gate, 1
Reference numeral 7 denotes a source and 18 denotes a drain.

As shown in FIG. 8A, step ST1
When over-erasing is performed with, a high voltage (Vs =
12.5 V) is applied and the control gate 15 is grounded, so that the electrons accumulated in the floating gate 16 are extracted to the source 17 by utilizing the tunnel phenomenon. At this time, sufficient erasing is performed so that all memory cells are over-erased.

Next, as shown in FIG. 8B, when the drain stress is applied in step ST3, the control gate 15 and the source 17 of the memory cell are grounded, and the drain 18 has a constant voltage (Vd). = 5V) is applied. That is, the A.D. generated when electrons move at high speed between the source and the drain. H. C. (Avalanche HotC
Arrier) is used to inject electrons into the floating gate 16 to raise the threshold voltage of the memory cell.

As shown in FIG. 8C, step ST2
When performing the over-erase verification in step 1 or the drain stress verification in step ST4, the control gate 15 and the source 17 are installed and the drain 1
A verify voltage (Vd = 1V) lower than that in steps ST2 and ST4 is applied to 8 and the data in the memory cell is read to determine whether the threshold value is set normally.

FIG. 9 is a diagram for explaining changes in the distribution state of the threshold voltage of the memory cell during each operation of the conventional two-step erase method described above. As shown in the figure, in the overerase operation (step ST1), the threshold voltage of the memory cell is changed from the high write state A to the low overerase state B of about 0 or less. In the drain stress operation (step ST3), the threshold voltage of the memory cell is raised to the state C, which is a value of approximately 0 or more, but is relatively low. In the additional drain stress operation (step ST5), the threshold voltage of the memory cell is raised from the state C to a higher state D.

[0017]

However, the above-mentioned conventional flash EEPROM has the following two problems.

The first problem is that even if the additional drain stress operation is performed so that the leak current does not occur at the time of high temperature use, the leak current at the time of use is different because the characteristics of each memory cell and the column line vary. It is difficult to surely suppress the value below a certain level. Therefore, it is difficult to eliminate the risk of erroneous reading due to the leak current during use.

As a second problem, when the additional drain stress is applied, if the drain stress is excessively applied, the threshold voltage of the memory cell rises excessively, resulting in the write state shown in FIG. There is also. That is, the application condition of the additional drain stress must be set to an appropriate condition so that the threshold voltage does not exceed the 0 or 1 judgment level of the data while originally suppressing the leak current at the time of high temperature reading. I won't. However, even in the same memory cell array, variations in threshold voltage of memory cells for each column line, deterioration of current capacity of memory cells due to application of rewriting stress, or film thickness of gate oxide film due to manufacturing process, etc. Since there is a subtle variation in the optimum application condition of the additional drain stress depending on these states, it is difficult to converge the variation in the threshold voltage of the memory cell after the erase operation within a predetermined value. . for that reason,
There is a possibility that the data may be inverted due to the increase in the threshold voltage.

The present invention has been made in view of the above points, and an object thereof is a semiconductor memory device having a nonvolatile memory cell capable of electrically writing and erasing, and a memory after erasing data. A non-volatile semiconductor memory device capable of controlling the threshold voltage of a cell and a driving method thereof are provided.

[0021]

In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention electrically comprises a double gate transistor having a floating gate and a control gate for accumulating charges. A memory cell array in which memory cells capable of writing and erasing data are arranged along rows and columns, and for performing operations such as writing, reading, and erasing data in each memory cell in the memory cell array. A peripheral circuit section, a column line provided in each column of the memory cell array, connecting the drains of the memory cells and extending to the peripheral circuit section, and arranged in the peripheral circuit section,
A column decoder for selecting one of the column lines that is electrically connected to the peripheral circuit section and a control gate of each memory cell provided in each row of the memory cell array are connected to each other and extend to the peripheral circuit section. A row line, a row decoder arranged in the peripheral circuit section for selecting one of the row lines that is conducted to the peripheral circuit section, and a floating gate of the memory cell arranged in the peripheral circuit section. Presumed to be a semiconductor memory device provided with a control circuit for controlling to perform a two-step erasing operation in which charges are extracted until the threshold voltage becomes negative and then returned to a predetermined threshold voltage, the semiconductor memory device is provided in the peripheral circuit section. A first sense amplifier circuit connected to the column line for reading data in the memory cell at high speed, and arranged in the peripheral circuit section, connected to the column line, and after the two-step erase A second sense amplifier circuit for determining whether or not the leak current after precharging the column line is equal to or lower than a predetermined level, and the column line is arranged in the peripheral circuit section and the column line serves as the first sense amplifier circuit. And a switching circuit for switching to connect to either one of the second sense amplifier circuit.

With this configuration, it is possible to control the leak current of the column line by using the second sense amplifier circuit instead of using the current detection type sense amplifier used for reading data as in the conventional case. That is, the second sense amplifier circuit can be used to control the leakage current after precharging the column line after the two-step erasing to a finer predetermined level or less. Therefore, by setting the predetermined level in consideration of the difference in leak current between high temperature and room temperature, it is possible to prevent erroneous reading due to the leak current during high temperature use. Further, by controlling the leak current to a predetermined level, the threshold voltage of the memory cell is adjusted to be substantially constant, and it is possible to reliably prevent the generation of the memory cell in which the threshold voltage is inverted.

A semiconductor memory device according to a second aspect is the semiconductor memory device according to the first aspect, wherein the first and second sense amplifier circuits are:
A precharge transistor having a drain connected to the power supply and an inverter connected to the source of the precharge transistor are provided, and a predetermined value serving as a reference for detecting the potential of the column line by the second sense amplifier circuit is set. It is configured to have an inversion potential of the inverter.

With this structure, the operation of claim 1 can be obtained only by providing the conventional semiconductor memory device with the switching circuit, and a highly reliable semiconductor memory device can be obtained while suppressing an increase in cost. .

According to a third aspect of the present invention, there is provided a method for driving a semiconductor memory device, comprising a memory cell which is composed of a double gate transistor having a floating gate and a control gate for accumulating charges and which can electrically write and erase data. A memory cell array arranged along rows and columns, a peripheral circuit section for performing operations such as writing, reading, and erasing data in each memory cell of the memory cell array, and each memory cell array in each column. To select a column line that is provided between the drains of the memory cells and that extends to the peripheral circuit section and a column line that is arranged in the peripheral circuit section and that is connected to the peripheral circuit section among the column lines. Of column decoders and row lines provided in each row of the memory cell array, connecting the control gates of the memory cells to the peripheral circuit section, and arranged in the peripheral circuit section. On the premise of a semiconductor memory device including a row decoder for selecting a row line electrically connected to the peripheral circuit section among the respective row lines, an arbitrary memory cell in the memory cell array is selected and a floating gate is selected. A first step of performing over-erase in which the threshold voltage of the memory cell is reduced to a negative value by extracting charges from the memory cell; A drain stress operation of applying a voltage, a second step of performing the second step, a third step of applying a predetermined voltage to the column line, and a third step of performing the precharge. After that, a fourth step of stopping the precharge and lowering the potential of the column line, and a predetermined step after starting the fourth step A fifth step of determining whether or not the potential of the column line is equal to or less than a predetermined value when a time period has elapsed, and the potential of the column line is not reduced to a predetermined value or less in the fifth step. It is a method of repeating the above second to fifth steps until the value becomes equal to or more than a value.

According to this method, the potential of the column line after precharging is lowered mainly by the leak current, so that the time required for the potential to drop from the precharge potential to a predetermined value or less becomes constant, The leak current value of the selected memory cell is controlled to a substantially uniform level, and the threshold voltage of each memory cell after the two-step erase is controlled to be substantially uniform. That is, it is possible to effectively prevent erroneous reading due to an increase in leak current even when used at a high temperature without causing data inversion.

Moreover, since the additional drain stress is unnecessary, the erase sequence is simplified and the rewriting operation and the inspection time are shortened.

[0028]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing the circuit configuration of the semiconductor memory device according to the embodiment. In the figure, MA is a memory cell M (i, j) (i = 1 to m, composed of double gate transistors having a floating gate and a control gate).
j = 1 to n) are arranged in a matrix of m rows and n columns, 7 is a column decoder for selecting columns of the memory cell array MA, and 8 is for selecting rows of the memory cell array MA. Column decoder, 9 is a source potential control circuit for controlling the source potential of each memory cell M (i, j) in the memory cell array MA, 1 is the operation of the column decoder 7, column decoder 8 and source potential control circuit 9. Reference numeral 11 denotes a current detection type sense amplifier circuit used for reading data of each memory cell M (i, j) in the memory cell array MA. A peripheral circuit section is constituted by the circuits 7 to 12 described above. The control gate of each memory cell M (i, j) is connected to the row decoder 8 via each row line WL1, ..., WLm, and the source of each memory cell M (i, j) is connected to the source potential control circuit via the source line SLB. 9 are connected respectively. The drain of each memory cell M (i, j) has a column line BL1, ..., B.
These column lines BL1, ..., B are respectively connected to Ln.
Ln are Nch transistors CTr1, ..., C, respectively.
Sense amplifier circuit 11 and column decoder 7 via Trn
It is connected to the. That is, each transistor CTr
Each source of 1, ..., CTrn is connected to each memory cell M (i,
Each of the transistors CTr1, ..., CT is connected to the drain of j).
Each gate of rn is connected to the column decoder 7 and each transistor CT.
The drains of r1, ..., CTrn are sense amplifier circuits 11
Connected to each other. The above structure is the same as that of the conventional semiconductor memory device shown in FIG.

Here, as a feature of this embodiment, a leak current determination circuit 12 for determining a leak current on each of the column lines BL1, ..., BLn is provided. The switching circuit SW is configured to be able to alternately switch the connection with each of the column lines BL1, ..., BLn between the sense amplifier circuit 11 and the leak current determination circuit 12. However, the sense amplifier circuit 11, the leak current determination circuit 12, and the switching circuit SW are integrally incorporated in the circuit described below.

FIG. 2 is a circuit diagram of the current detection type sense amplifier circuit 11, the leak current determination circuit 12 and the switching circuit S shown in FIG.
It is the electric circuit diagram of the circuit which integrates W, and the table which shows the signal state in this circuit. However, in FIG. 2, only BLn of the column lines BL1, ..., BLn is representatively shown, and a case where the column line BLn is selected will be described as an example.

The operation and specific configuration of each part will be described below with reference to the electric circuit diagram and table of FIG.

In the circuit shown in the figure, a Pch transistor Tr1, an Nch transistor Tr2, an inverter I
The nv1, Pch transistor Tr6, and Nch transistor Tr7 form a current detection type sense amplifier circuit 11 (first sense amplifier circuit) that determines 0 or 1 of data during a read operation. Further, the Pch transistor Tr1 and the inverter Inv1 form a leak current determination circuit 12 (second sense amplifier circuit). Further, the column line BLn is connected to the current detection type sense amplifier circuit 11 and the leak current determination circuit 12 by the circuit connecting the nodes N1 and N2 via the Nch transistor Tr3 and the inverter including the Pch transistor Tr5 and the Nch transistor Tr8. A switching circuit is configured to switch to connect to either one.

At the time of normal reading, the signal "L" is supplied as SIN1 (sense amplifier disconnection signal), SIN2 (sense amplifier drive signal) and SIN3 (load transistor drive signal). When the signal SIN1 becomes “L”, the Nch transistor Tr3 is turned off, and the node N1 and the column line BLn are no longer electrically connected via the Nch transistor Tr3. That is, the leak current determination circuit 12 and the column line are separated from each other. Also,
When the signal SIN2 becomes “L”, the Pch transistor Tr5 is turned on and the Nch transistor Tr8 is turned off, and the current detection type sense amplifier circuit 11 is activated. Further, when the signal SIN3 becomes "L", the Pch transistor Tr1 which is a load transistor is turned on.

In this state, when the column decoder 7 selects and turns on the Nch transistor Tr4 (transistor CTrn shown in FIG. 1), if the data of the selected memory cell is 0, the potential of the node N2 becomes "H". , The potential of the node N3 becomes “L” by the operation of the inverter composed of the Pch transistor Tr6 and the Nch transistor Tr8, and the Nch transistor Tr2 is turned off. Therefore, the potential of the node N1 is "H".
On the other hand, when the data of the selected memory cell is 1, the potential of the node N2 is "L" because a current flows through the memory cell.
Therefore, the potential of the node N2 becomes “H”, and Nch
The transistor Tr2 is turned on. Therefore, the potential of the node N1 is "L". Therefore, by detecting the level of the output SOUT obtained by inverting the potentials “L” and “H” signals of the node N1 by the inverter Inv1,
It can be determined whether the data of the selected memory cell is 0 or 1.

On the other hand, at the time of precharge in the verify operation after the drain stress, "H" is supplied as the signal SIN1 and the signal SIN2, and "L" is supplied as the signal SIN3. When the signal SIN1 becomes “H”, the Nch transistor Tr3 is turned on, and the node N1
And the node N2 are electrically connected. On the other hand, when the signal SIN2 becomes “H”, the Pch transistor T
Since r5 is off and the Nch transistor Tr8 is on, the potential of the node N3 becomes "L". Therefore, N
The ch transistor Tr2 is off. That is, the current detection type sense amplifier circuit 11 is separated from the column line BLn. Further, when the signal SIN3 becomes “L”, the Pch transistor Tr1 is turned on,
The voltage Vdd is supplied to the nodes N1 and N2. And
By selecting the Nch transistor Tr4 by the column decoder 7, the potential of the column line BLn is precharged.
The Nch transistor Tr1 functions as a load transistor and a precharge transistor.

When discharging, the signal SIN
Since the signal SIN3 is switched to "H" while 1 and SIN2 remain unchanged, the Pch transistor Tr1 is turned off. Then, when the time elapses as it is, the potential of the column line BLn is discharged only by the leak current of the memory cell on the column line BLn, and the potential decreases.
In the memory cell at the time of this discharge operation, the control gate and the source are grounded and the stress is applied only to the drain. The change in the column line potential at this time will be described in detail below.

The procedure of the drain stress verify will be described below with reference to FIGS. 3 and 4. FIG.
FIG. 6 is a diagram for explaining a time change of a column line potential at the time of drain stress verification. FIG. 4 is a flowchart showing an erase sequence of the two-stage erase method.

First, in steps ST1 to ST3, the same processing as steps ST1 to ST3 in the conventional method is performed. After that, drain stress verify is performed in step ST4, and this drain stress verify step ST4 is divided into sub-steps of steps ST41 to ST43.

First, in step ST41, the column line BLn of the selected memory cell is precharged. That is, the signal SIN1 is set to "H" and the signal SIN2 is set to "H".
In addition, by setting the personal number SIN3 to "L", the voltage Vdd is supplied to the column line BLn via the node N1 by the above-mentioned action, and the column line potential gradually increases to the voltage Vn as shown in FIG.
rise to the level of dd.

Next, in step ST42, the column line BLn of the memory cell is discharged by a leak current. That is, the signal SIN1 is set to "H" and the signal SIN
The supply of the voltage Vdd to the column line BLn is cut off by setting the signal SIN3 to “H” while keeping 2 at “H”.
Therefore, with the passage of time, the charges charged in the column line BLn are discharged by the leak current of the selected memory cell, and the potential of the column line BLn gradually decreases as shown in FIG.

Next, in step ST43, a strobe is set up when a certain time has elapsed. That is, the column line BL
The level of the potential of n is the inverted output SOU of the inverter Inv1.
It can be identified by T. Therefore, after sufficiently precharging the potential of the column line BLn to the voltage Vdd, the column line Bn
The time tDCW necessary for discharging until the potential of Ln reaches the inversion level of the inverter Inv1 is obtained, and a strobe is set when the time tDCW has elapsed after precharging to determine whether the output signal SOUT is high or low. Of. At this time, if the potential of the column line BLn has not reached the inversion level of the inverter Inv1 or less, the determination is OK, and the control ends. On the other hand, if the column line potential at that time has reached the inversion level of the inverter Inv1 or lower, the determination result in step ST43 becomes NG, the process returns to step ST3, and steps ST41 to ST41-4.
The control of 3 is repeated.

The above drain stress and drain stress verify are repeatedly carried out step by step until the judgment becomes stepwise OK, that is, until the voltage does not fall below the inversion level of the inverter Inv1 within the discharge time of time tDCW or less. . By this operation, the leak current on the column line after the drain stress can be set to a target value with good controllability.

On the other hand, in the conventional device, the minute leak current itself to be finally set is not detected, but
The leakage current value on the bit line was suppressed from the over-erased state to the level at which it does not malfunction (erroneous read) at room temperature, which is the guaranteed rewrite temperature, and then the high-temperature read was finally considered with the additional drain stress time width. Although this is a method to suppress the minute leak current to be set, this time width has a problem in controllability because an approximate required time was set based on sample evaluation and the same time was set for all bit lines. It was

On the other hand, in the present embodiment, the potential precharged to Vdd is discharged by the minute leak current itself to be finally set, and the determination is made by the inversion voltage of the inverter Inv1 for each bit line having a different state. Therefore, it becomes possible to control the minute leak current to a predetermined level, and it is possible to suppress variations in the threshold voltage Vt of each memory cell.

FIG. 5 shows the distribution state of the threshold voltage of the memory cell in steps ST11 and ST13 of the two-step erase method according to this embodiment. As shown in FIG. 5, by accurately controlling the leak current value, the variation in the threshold voltage after erasing causes the variation in the threshold voltage after erasing by the conventional two-step erasing method (see FIG. 9). You can see that it is suppressed compared to.

Therefore, in the present embodiment, the drain current is applied so that the time tDCW until the potential on the node N1, that is, the column line after the drain stress is applied reaches the inversion level is uniform, so that the leak current value is reduced. Control to a predetermined level. Therefore, it is not necessary to perform additional drain stress as in the conventional EEPROM having a non-volatile memory, so that the threshold voltage of a memory cell in which the threshold voltage value of each memory cell varies during overerasure is written. There is no problem that the state value is inverted. On the other hand, by adjusting the predetermined level of the leak current in advance so that the leak current does not increase in the high temperature state, even if the semiconductor memory device is used, even if the read is performed under the high temperature condition, It is possible to effectively prevent erroneous reading due to the error.

In such a stepwise repetitive operation, by setting the drain stress time shorter (the time interval is finer), the change curve of the column line potential shown in FIG. 3 does not fall below the inversion level. Since the rise width from the inversion level at this time becomes small, it becomes possible to control the leak current on the column line more uniformly to a target value.

In addition, in the present embodiment, the additional drain stress in the conventional two-step erase method is not required and the erase sequence is simplified, so that the rewriting operation and the inspection time can be shortened.

In the present embodiment, an example in which the leak current judging circuit 12 on the column line and the current detection type sense amplifier 11 are combined has been described, but the leak current judging circuit 12 on the column line is used as a single circuit. Or, it can be applied to a combination with a circuit of another system. In addition, the leak current determination circuit 12 on the column line and the current detection type sense amplifier 11 form the Pch transistor Tr1 and the inverter In
Although v1 is shared, the two need not necessarily share members. However, as in the present embodiment, the Pch transistor Tr1 and the inverter Inv
The configuration in which 1 is shared has an advantage that a highly reliable flash memory can be configured with almost no increase in the cost of the semiconductor memory device.

Further, the Nch transistor Tr3 which outputs the sense amplifier disconnection signal and connects the precharge / discharge system of the column line may be a Pch transistor or a CMOS type transfer gate.

[0052]

As described above, according to the first or second aspect of the present invention, there is provided a memory cell array having a non-volatile memory cell composed of a double gate transistor and capable of electrically writing and erasing data. In a semiconductor memory device having a two-stage erase operation, it is determined whether or not the leak current of the column line after precharge is equal to or less than a predetermined value, separately from the sense amplifier circuit for reading data. A leak current determination circuit is provided for this purpose, and a switching circuit that switches the connection with the column line to any of the circuits is provided, so the leak current of the memory cell is controlled to a minute predetermined level via the column line. Therefore, it is possible to effectively prevent erroneous reading due to generation of a memory cell in which the threshold level is inverted and leakage current during use. It is possible to improve the reliability of the storage device.

According to a third aspect of the present invention, as a method of driving a semiconductor memory device, the potential of a column line does not drop below a predetermined voltage when a predetermined time has elapsed after precharging the column line after a two-stage erase operation. Therefore, it is possible to equalize the threshold voltage of each memory cell of the semiconductor memory device and to eliminate the additional drain stress in the conventional two-step erase method, thereby simplifying the erase sequence and
Rewriting operation and inspection time can be shortened.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a semiconductor memory device according to a first embodiment.

FIG. 2 is an electric circuit diagram of a circuit formed by combining a current detection type sense amplifier circuit and a leak current determination circuit on a column line of the semiconductor memory device according to the first embodiment.

FIG. 3 is a graph showing a time change of a column line potential according to the drain stress verify method according to the first embodiment.

FIG. 4 is a flowchart showing a sequence of a two-step erasing method according to the second embodiment.

FIG. 5 is a diagram showing a distribution state of threshold voltages of memory cells during each operation of the two-step erase method according to the second embodiment.

FIG. 6 is an electric circuit diagram of a conventional semiconductor memory device.

FIG. 7 is a flowchart showing a sequence of a conventional two-step erasing method.

FIG. 8 is a diagram showing voltage application conditions for a selected memory cell during conventional over-erase, drain stress, over-erase verify, and drain stress verify.

FIG. 9 is a diagram showing a distribution state of a memory cell threshold voltage at each operation of a conventional two-step erasing method.

[Explanation of symbols]

 7 column decoder 8 row decoder 9 source potential control circuit 10 control circuit 11 sense amplifier circuit 12 leak current determination circuit 15 control gate 16 floating gate 17 source 18 drain MA memory cell array SW switching circuit N node Tr transistor M memory cell BL column line WL Row line CTr transistor

Claims (3)

[Claims] 1. A memory having memory cells each having a floating gate for accumulating charges and a control gate and capable of electrically writing and erasing data, the memory cells being arranged along a row and a column. A cell array, writing data to each memory cell in the memory cell array,
Peripheral circuit part for performing operations such as reading and erasing,
A column line that is provided in each column of the memory cell array and that connects the drains of the memory cells and that extends to the peripheral circuit section, and a column line that is arranged in the peripheral circuit section and is electrically connected to the peripheral circuit section of the column lines. A column decoder for selecting a column line, a row line provided in each row of the memory cell array and connecting control gates of the memory cells to the peripheral circuit section, and a row line arranged in the peripheral circuit section. A row decoder for selecting a row line that is electrically connected to the peripheral circuit section among the lines, and after extracting charges from the floating gate of the memory cell arranged in the peripheral circuit section until the threshold voltage becomes negative. In a semiconductor memory device having a control circuit for controlling to perform a two-step erase operation for returning to a predetermined threshold voltage, the semiconductor memory device is arranged in the peripheral circuit section and connected to the column line. A first sense amplifier circuit for reading out data in a memory cell at high speed and a memory cell arranged in the peripheral circuit section and subjected to the two-step erasure to determine whether or not a leak current in a column line is below a predetermined level. And a switching circuit arranged in the peripheral circuit section for switching to connect the column line to either the first sense amplifier circuit or the second sense amplifier circuit. A semiconductor memory device comprising: 2. The semiconductor memory device according to claim 1, wherein the second sense amplifier circuit includes a precharge transistor having a drain connected to a power supply, and an inverter connected to a source of the precharge transistor. The semiconductor memory device is characterized in that the predetermined value serving as a reference for detecting the potential of the column line by the second sense amplifier circuit is the inverted potential of the inverter. 3. A memory in which memory cells, each of which is composed of a double-gate transistor having a floating gate and a control gate for accumulating charges, and which can electrically write and erase data, are arranged along rows and columns. A cell array, a peripheral circuit section for performing operations such as writing, reading, and erasing data to and from each memory cell of the memory cell array, and a drain of each memory cell provided in each column of the memory cell array are connected. A column line extending to the peripheral circuit section,
A column decoder arranged in the peripheral circuit section for selecting a column line that is electrically connected to the peripheral circuit section among the column lines and a control gate of each memory cell provided in each row of the memory cell array are connected to each other. Of the semiconductor memory device including a row line extending to the peripheral circuit section and a row decoder arranged in the peripheral circuit section for selecting a row line that is electrically connected to the peripheral circuit section among the row lines. A first step of performing a method of driving, which is a driving method, in which an arbitrary memory cell in the memory cell array is selected and electric charges are extracted from a floating gate to lower a threshold voltage of the memory cell to a negative value; A second step of performing a drain stress operation of applying a power supply voltage to the memory cell in the over-erased state through the column line for a certain time, and the second step After that, a third step of applying a predetermined voltage to the column line is precharged, and after performing the third step, the precharge is stopped to reduce the potential of the column line. A fourth step; and a fifth step of determining whether or not the potential of the column line is equal to or less than a predetermined value when a predetermined time has elapsed after starting the fourth step, and the fifth step A method for driving a semiconductor memory device, wherein the steps 2 to 5 are repeated until the potential of the column line does not drop below a predetermined value in step.