JP3397407B2 - Nonvolatile semiconductor memory device and erasing method therefor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a method of relieving an over-erased bit of a flash memory which can be electrically electrically erased in a chip or in a block.

[0002]

2. Description of the Related Art FIG. 22 is an IEEE Journal.
of Solid-State Circuits, V
ol. 23, No. FIG. 5 is a block diagram of a conventional flash memory described in Pages 1157 to 1163 of October 1988.

As shown in FIG. 1, a Y gate 2, a source line switch 3, an X decoder 4 and a Y decoder 5 are provided around the memory array 1. An address register 6 is connected to the X decoder 4 and the Y decoder 5, and an address signal inputted from the outside is inputted. Memory array 1
An input data register (writing circuit) 7 and a sense amplifier 8 are connected to each other via a Y gate 2. The input data register 7 and the sense amplifier 8 are the input / output buffer 9
It is connected to the. A program voltage generating circuit 10 and a verify voltage generating circuit 11 are provided in the flash memory, and each of the voltage generating circuits 10 and 11 generates a voltage of a level different from Vcc and Vpp supplied from the outside.
It is supplied to the Y gate 2 and the X decoder 4. Further, the flash memory is provided with a command register 12 and a command decoder 13 for setting an operation mode according to data input from the outside. Further, an input signal buffer 14 is provided, and control signals WE, CE, and OE from the outside are input to the input signal buffer 14.

FIG. 23 is a sectional view of a memory cell (memory transistor) which constitutes the memory array of FIG. The memory cell includes a floating gate 16 and a control gate 17 formed above the semiconductor substrate 15.
And a source diffusion region 18 and a drain diffusion region 19 selectively formed on the surface of the semiconductor substrate 15.

Floating gate 16 and semiconductor substrate 1
The oxide film 20 between 5 is thin (about 100 Å), and the floating gate 1 utilizing the tunnel phenomenon is used.
It is possible to move the electrons to 6.

The operation of the memory cell is as follows. At the time of programming, a program voltage of about 6.5 V is applied to the drain 19 and the voltage Vpp is applied to the control gate 17.
(12V) is applied and the source 18 is grounded. Therefore, the memory cell is turned on and a current flows. At this time, avalanche breakdown occurs near the drain 19 and electron-hole pairs are generated. The holes flow to the ground potential through the semiconductor substrate 15, and the electrons flow in the channel direction to flow into the source 18. However, some electrons are accelerated by the electric field between the floating gate 16 and the drain 19 and injected into the floating gate 16. As a result, the threshold voltage of the memory cell rises. This state is defined as storage of information "0".

On the other hand, erasing is performed by opening the drain 19, grounding the control gate 17, and applying the voltage Vpp to the source 18. Then, a tunnel phenomenon occurs due to the electric field between the source 18 and the floating gate 16, and the electrons in the floating gate 16 are extracted. As a result, the threshold voltage of the memory cell drops. This is defined as storage of information "1".

FIG. 24 shows a circuit diagram of the memory array of FIG. 22 and its peripheral circuits. As shown in the figure, the memory cells MC are arranged in a matrix, the drains are connected to the bit lines BL (BL1 to BL3) in column units, and the control gates are arranged in word lines WL (WL1 to W3) in row units.
L3). The word line WL is connected to the X decoder 4, and the bit line BL is the output Y1 of the Y decoder 5.
.About.Y3 are connected to the I / O line 27 via the Y gate transistors 2 whose gates are respectively input. I / O line 2
7, a sense amplifier 8 and a write circuit 7 are connected,
The sources of all the memory cells MC are connected to the source line switch 3 via the source line 28.

Next, the operation will be described. First, FIG.
A case where writing is performed in the memory cell MC surrounded by a dotted line will be described as an example. The write circuit 7 is activated according to the data input from the outside, and the program voltage is supplied to the I / O line 27. At the same time, X decoder 4 and Y
Based on an address signal (not shown) taken in by the decoder 5, the Y decoder 5 activates the signal Y1 and outputs the signal Y1.
The Y gate 2 to which 1 is applied is turned on, and the X decoder 4 is
The word line WL1 is selected and the voltage Vpp is applied. The source line 28 is grounded by the source line switch 3 during programming.

Then, a current flows only in one memory cell MC surrounded by a dotted line in the figure, hot electrons are generated, the threshold voltage is increased, and "0" is written.

Erasing is performed as follows. First, the X decoder 4 and the Y decoder 5 are deactivated, and all the memory cells are deselected. That is, the control gate 17 of each memory cell is grounded and the drain 19 is opened, while a high voltage is supplied to the source line 28 by the source line switch 3. Thus, due to the tunnel phenomenon, the threshold voltage of the memory cell shifts to the lower side and "1" is written. Since the source line 28 is common in the chip or the block, the erasing is collectively performed on all the memory cells MC in the chip or the block.

Next, the read operation will be described by taking as an example the case of reading from the memory cell MC surrounded by the dotted line in FIG. First, when the address signal is Y decoder 5 and X
The selected Y gate 2 (signal Y1 applied) and word line WL1 decoded by the decoder 4 are "H" (Vcc)
Becomes At this time, the source line 28 is connected to the source line switch 3
Grounded by. When this memory cell MC is written, its threshold voltage is high. Therefore, even if "H" is given to the control gate 17 of the memory cell MC by the word line WL1, the voltage is the threshold voltage of the memory cell MC. Since it is lower than the voltage, the memory cell MC does not turn on, and no current flows from the bit line BL1 to the source line 28.

On the other hand, when the memory cell is erased, its voltage becomes higher than the threshold voltage of the memory cell, so that the memory cell is turned on and a current flows from the bit line BL1 to the source line 28.

Therefore, the read data "1" or "0" is obtained by detecting with the sense amplifier 8 whether or not a current flows through the memory cell MC.

In the EPROM, erasing is performed by irradiation of ultraviolet rays. Therefore, when the floating gate becomes electrically neutral, electrons are not extracted from the floating gate any more, and the threshold voltage of the memory transistor is about 1V. Not the following:

On the other hand, EE used for flash memory
In the extraction of electrons using the tunnel phenomenon of a PROM or the like, it is possible that electrons are excessively extracted from the floating gate and the floating gate is positively charged. This phenomenon is called overerase (or overerase). When overerased, the threshold voltage of the memory transistor becomes negative, which hinders subsequent reading and writing.

That is, even if the level of the word line is "L" and the level applied to the control gate of the memory transistor is "L" when it is unselected during reading,
Bit line BL through the over-erased memory transistor
Since a current flows from the source line 28 to the source line 28, the memory cell to be read on the same bit line erroneously reads "1" even if the threshold voltage is high in the "0" written state. Further, even during writing, a leak current flows through the over-erased memory cell, which deteriorates the writing characteristics and further disables writing. For this reason, the erase operation is performed in stages, read after the erase to check whether the erase is performed correctly (hereinafter referred to as verify), and if there is a bit that is not erased, perform the erase again. Conventionally, a method of preventing an erase pulse from being applied to a memory cell is applied.

25 and 26 are flowcharts of the program and erase operations including the verify operation described above, and FIGS. 27 and 28 are timing waveform diagrams of the operations, respectively. 25 to 28 and FIG. 22.
Each step of erasing and programming will be described with reference to. In the conventional flash memory, erasing and program mode setting are performed by a combination of input data. That is, the mode is set by the input data when the bar WE rises.

First, the case of a program will be described. First, the voltages Vcc and Vpp are raised (step S1), and then the control signal bar WE is lowered.

Then, at the next rise of the control signal bar WE, the input data (40H) is latched in the command register 12 (step S2). After that, the input data is decoded by the command decoder 13, and the operation mode becomes the program mode. Then, the control signal bar WE is lowered again, the address from the outside is latched in the address register 6, and the data D is risen at the rising edge of the control signal bar WE.
IN is latched by the write circuit 7 (step S3).
Next, the program pulse is applied to the program voltage generation circuit 10
And is applied to the X decoder 4 and the Y decoder 5. Thus, as described above, the program ("0" write) operation is performed (step S4).

Next, the control signal bar WE is lowered, and the input data (COH) is output at the subsequent rise of the control signal bar WE.
Are latched in the command register 12, and the operation mode becomes the program verify mode (step S5). At this time, the erase / program verify voltage generation circuit 11 causes the program verify voltage (~ 7.
0 V) is generated and applied to the X decoder 4. Since the voltage applied to the control gate 17 of the memory cell is higher than the normal read voltage of 5 V, the memory cell in which writing is insufficient is likely to be turned on, and the writing failure can be more reliably generated. Next, reading is performed (step S7), and the write data is confirmed (step S8). At this time, if the writing is insufficient, the writing is further repeated. If the data has been written (step S9), the operation mode is set to the read mode and the program ends.

Next, the case of erasing will be described. First, the voltages Vcc and Vpp are raised (step S1
0), followed by writing "0" to all bits using the program flow described above (step S11). This is because the memory cell is over-erased when the erased memory cell is further erased. Next, control signal bar W
E is lowered, and the erase command (20H) is input at the subsequent rise of the control signal bar WE (step S12). Then, the control signal bar WE is lowered again, and the erase command (20H) is input at the subsequent rise of the control signal bar WE (step S13). At this time, an erase pulse is generated inside the chip, and the voltage Vpp is applied to the source 18 of the memory cell through the source line switch 3 until the subsequent fall of the control signal bar WE (step S14). The address is also latched at this falling edge. At the subsequent rise of the control signal bar WE, the erase verify command (A0H) is latched, and the operation mode becomes the erase verify mode (step S15). At this time, the erase / program verify voltage generation circuit 11 causes the erase verify voltage (.about.3.2).
V) is generated and applied to the X decoder 4. Since the voltage applied to the control gate 17 of the memory cell is lower than the voltage (5 V) at the time of normal reading, it becomes difficult to turn on a memory cell that is not sufficiently erased, and the erase failure can be detected more reliably. Next, reading is performed (step S16) to confirm the erased data. This time,
If the erasing is insufficient, the erasing is repeated. If it has been erased, the address is increased (step S17),
The erase data of the next address is verified. If the verified address is the last address (step S18), the operation mode is set to the read mode (step S20), and the erase operation ends.

[0023]

The conventional non-volatile semiconductor memory device is configured as described above to prevent over-erasure from occurring. However, a remedy for a memory cell in an over-erased state is provided. There was a problem that I did not take it.

The present invention has been made to solve the above problems, and it is an object of the present invention to obtain a non-volatile semiconductor memory device and an erasing method thereof capable of detecting or repairing an over-erased memory cell. To aim.

[0025]

[0026]

[0027]

[0028]

SUMMARY OF THE INVENTION Claims according to the present invention
1. The nonvolatile semiconductor memory device according to 1, is electrically written,
A plurality of memory transistors erasable, and write operation to selectively increase any one of the threshold voltage prior Symbol plurality of memory cells to lower the threshold <br/> value voltages of the plurality of memory transitional is te has a function of executing an erasing operation, if the memory transistors of a normal erased state of being lowered to a predetermined level threshold voltage of the turned off and over has a reduced threshold voltage above a predetermined level than the threshold voltage of the normal erase state Even if the memory transistor is in the erased state, the verify voltage generating means for generating a verify voltage of a level to be turned on, and the memory transistor in the over-erased state
An off voltage that generates an off voltage at the level forcibly turning off.
And pressure generating means, executes a pre-Symbol erase operation, then the one of the plurality of memory transistors, the verify voltage is applied to the gate of the memory transistor in the selected state, the off-voltage to the gate of the memory transistor of the unselected by applying, on the basis of the oN / oFF of the memory transistors of the selected state, the running over-erase verify operation to verify whether normal erased state or over-erased state, the memory transistors of the selected state in an over-erased state If there is
The write operation is performed on the memory transistor in the over-erased state, and the threshold value in the normal erased state is applied to the memory transistor in the over-erased state after the writing operation is performed.
Not erased having a threshold voltage higher than a predetermined level above the voltage
Run the unerased verify operation for verifying whether removed by state, when the verification result of the non erase verification operation instructs the unerased state, and a erase-write execution unit that perform the erase operation again ing.

[0029]

[0030]

[0031]

According to a second aspect of the present invention, there is provided an erasing method for a non-volatile semiconductor memory device, comprising electrically writing and erasing.
It has a plurality of possible memory transistors.
A book that selectively raises one of the threshold voltages of the memory cell.
The write operation and the threshold voltage of the plurality of memory transistors
A machine that executes the erase operation to lower the pressure to enter the erased state.
A method for erasing a nonvolatile semiconductor memory device having a function, comprising: performing the erasing operation;
Normal erasure for the memory transistor on which the operation was executed
Threshold voltage lower than the threshold voltage for
Whether it is a memory transistor in the over-erased state with pressure
Step to execute over-erase verify operation to verify whether
When the obtained verification result of the over-erase verify operation, when the verification result showed the presence of the memory transistor over-erased, and executing the write operation for the previous SL memory transistor over-erased, before Symbol against the memory transistor after the write operation execution, the normal consumption
Threshold voltage that is higher than the threshold voltage in the left state by a predetermined level or more
Unerased verify to verify whether or not there is an unerased state
And performing an operation, when the verification result of the unerased verify operation indicated the presence of a memory transistor unerased state, and a step for executing the pre-Symbol erase operation.

[0033]

The erasing / writing executing means of the non-volatile semiconductor memory device according to claim 1 of the present invention performs the erasing operation.
After overwriting, in the over-erase state by the over-erase verify operation.
Write to memory transistors that are found to be
Operation is performed, and after this write operation, unerased verify
A memory transaction that is recognized as unerased by operation
If there is a register, the erase operation is performed.
The memory transistor in the over-erased state after performing
In addition, the unerased state can be
Memory transistors that have become
It

According to a second aspect of the present invention, the method for erasing a non-volatile semiconductor memory device comprises:
The unerased verify for the memory transistor after the operation is executed.
A) and the verification result of the unerased verify operation is not erased.
Erased when the presence of a memory transistor in the off state is indicated
By executing the operation, the
Rescue even erased memory transistors
You can

[0035]

[0036]

[0037]

[0038]

[0039]

【Example】

<Principle of the Invention> FIG. 2 is a graph showing VG-ID characteristics of a memory cell (memory transistor). In addition, VG
Is the gate voltage and ID is the drain current. Also,
FIG. 3 is an explanatory diagram for explaining the operation. In FIG. 2, L1
Is the VG-ID characteristic curve in the programmed ("0" written) state, L2 is the VG-ID in the erased ("1" written) state
A characteristic curve, L3, is a VG-ID characteristic curve in the overerased state.

As shown in the figure, since the memory cell in the over-erased state is turned on even when the gate voltage VG is 0V,
Even if the word line WL is in the non-selected state, if the bit line is in the selected state, a cell current is caused to flow, which affects read and write characteristics. In order to detect an over-erased memory cell having a VG-ID characteristic like L3 in FIG. 2, the following condition 1. ~ 3. It is necessary to have a function that satisfies the condition of.

Condition 1. Regardless of the state of the memory cell, the non-selected memory cell is always turned off.

Condition 2. It is determined whether the selected memory cell is in the over-erased state.

Condition 3. The same read operation as the normal read operation can be performed.

The condition 1 is to prevent an erroneous read operation from being performed by turning on an unselected memory cell and flowing a current regardless of whether the selected memory cell is on or off.

To satisfy the condition 1, as shown in FIG. 3B, it is sufficient to apply a negative voltage of a level at which the memory cell in the over-erased state is turned off to the non-selected word line WL. However, when a high negative voltage is applied, erroneous erasing occurs as shown in FIG. 3 (c), so it is ideal to generate a negative voltage as high as possible, for example, a negative voltage of about -Vcc within a range where erroneous erasing does not occur. .

To satisfy the condition 2, a voltage of 0 V is applied to the word line WL in the selected state, and the selected memory cell is turned on (see FIG. 3 (a)) / off, and the over-erased state / normal erase is performed. It suffices to detect the state.

To satisfy the condition 3, the address of the memory cell in the over-erased state can be detected by using the normal read method as it is.

<First Embodiment> FIG. 1 is a block diagram showing the structure of a flash memory according to an embodiment of the present invention. As shown in the figure, a negative voltage generating circuit 31 is newly provided.

In addition to the conventional function, the command decoder 13 'receives an external command for instructing the overerase verify mode via the input signal buffer 14 and decodes the command to instruct the overerase verify mode. The mode signal OEV is output to the negative voltage generation circuit 31 and the X decoder 32.

The negative voltage generating circuit 31 is a circuit which receives the operation mode signal OEV from the command decoder 13 'and generates a negative voltage when the operation mode signal OEV indicates the over-erase verify mode.

In addition to the function of the conventional X decoder 4 (FIG. 22), the X decoder 32 receives the operation mode signal OEV, and when the operation mode signal OEV indicates the overerase verify mode, 0V and a negative voltage are applied to the word line. It further has a function of selectively supplying. Therefore, by verifying ON / OFF of the memory cell in the selected state in which 0V is applied to the gate, it is possible to verify whether or not the memory cell in the selected state is in the over-erased state.

Further, the timer 15 supplies a pulse signal for defining the program time or the erase time to the command decoder 13 '. Note that other configurations are the same as the conventional configuration shown in FIG. 22, and therefore description thereof will be omitted.

FIG. 4 is a circuit diagram showing details of the memory array 1 and its peripheral portion. As shown in the figure, the memory cells MC are arranged in a matrix, the drains are connected to the bit lines BL (BL1 to BL3) in column units, and the control gates are arranged in word lines WL (WL1 to W3) in row units.
L3). The word line WL is connected to the X decoder 32, and the bit line BL is the output Y of the Y decoder 5.
1 to Y3 are connected to the I / O line 27 via the Y gate transistor 2 whose gates are respectively input. The sense amplifier 8 is connected to the I / O line 27, and all the memory cells MC
Is connected to the source line switch 3 via the source line 28.

Further, a negative voltage is supplied from the negative voltage generating circuit 31 to the X decoder 32, and the X decoder 32 can supply the negative voltage to the word line WL.

FIG. 5 is a circuit diagram showing the internal structure of the negative voltage generating circuit 31. As shown in the figure, PMOS transistors T0 to Tn (n is an even number of n ≧ 2) having a common drain and gate are connected in series, the gate of the PMOS transistor T0 is grounded, and the gate of the transistor Ti (i = 1 to n) is connected. Is connected to one electrode of the capacitor Ci. Also,
The source of the transistor Tn is the NMOS transistor Q1
Is connected to the source, NMOS transistor Q1 is the power supply voltage Vcc is applied to the gate.

Further, the oscillator 41 uses the operation mode signal OE.
When V indicates the over-erase verification mode, it becomes active, oscillates at a predetermined frequency, outputs the oscillation signal φ to the other electrodes of the capacitors C1, C3, ... Cn-1, and outputs the inverted oscillation signal bar φ to the capacitor. Output to the other electrodes of C2, C4, ... Cn.

The oscillator 41 is in the oscillating state , and the oscillation signal φ
And the inverted oscillation signal bar φ are output, the transistor T
Due to the charge pump phenomenon caused by 1 to Tn and capacitors C1 to Cn, a negative voltage VNCP that is considerably lower than 0V is output from the drain of the transistor Q1.

FIG. 6 is a circuit diagram showing a part of the negative voltage supply portion of the X decoder 32. As shown in the figure, one PMOS transistor Q10 and four CMOS inverters 51 to 54 are provided corresponding to each predecode signal bar X (only bar X1 and bar X2 are shown in FIG. 6).
The signal XOEV is applied to the gate of the PMOS transistor Q10, the predecode signal bar X is applied to one electrode, and the input portion of the CMOS inverter 51 and C are applied to the other electrode.
The output part of the MOS inverter 52 is connected. Note that C
The sources of the PMOS transistors PM of the MOS inverters 51 and 52 are both connected to the power source Vcc, and the sources of the NMOS transistors NM are both connected to the negative voltage VNCP.
The CMOS inverter 51 and the CMOS inverter 52 are loop-connected.

The predecode signal bar X is a signal which is selectively set to "L" based on the address input obtained from the address register 6, and the signal XOEV is delayed for a predetermined time only when the mode signal OEV falls. In addition to appearing, the signal has the same value as the operation mode signal OEV.

The output of the CMOS inverter 51 is CMOS
It is also connected to the input of the inverter 53, the output of the CMOS inverter 53 is connected to the corresponding word line WL, and is also connected to the input of the CMOS inverter 54.
The output of the S inverter 54 is fed back to the input of the CMOS inverter 53. PM of CMOS inverters 53 and 54
A negative voltage VNCP is applied to both sources of the OS transistor PM, and both sources of the NMOS transistor NM are grounded. A circuit that performs a normal program operation, a read operation, and the like has the same configuration as the conventional one.

[0061] In such a configuration, the signal XOEV becomes "L", when the "L" level predecode signal bar X instructs the selection, CMOS inverters 51 and 5
Since "L" is latched in the loop consisting of 2 and the output of the CMOS inverter 51 becomes "H", the output of the CMOS inverter 53 becomes "L" (GND) and the word line WL in the selected state is "L" (GND). ). On the other hand, the pre-decode signal bar X instructs the non-selected "H" level Noto
Then , "H" is latched in the loop formed by the CMOS inverters 51 and 52, and the output of the CMOS inverter 51 becomes "L". Therefore, the output of the CMOS inverter 53 becomes the negative voltage VNCP, and the word line WL in the non-selected state is The negative voltage VNCP is applied.

As described above, the negative voltage generating circuit 31 has the negative voltage VNC of -kV when the operation mode signal OEV is "H".
P, and the X decoder 32 outputs the operation mode signal OEV.
When the over erase verify mode is instructed, the selected word line WL can be set to the GND level and the non-selected word line WL can be set to the negative voltage VNCP. For example, as shown in FIG. 9, when the predecode signal bar X1 is "L", the word line W
When L1 is selected, in the period T1, the word line WL
1 becomes 0V (GND), the other non-selected word lines WL (only WL2 is shown) become -kV (= negative voltage VNCP), the predecode signal bar X2 is "L" and the word line W
When L2 is selected, in the period T2, the word line WL
2 becomes 0V (GND), and the other non-selected word lines WL (only WL1 is shown) become -kV (= negative voltage VNCP).

7 and 8 are a timing chart and a flow chart showing the operation of the flash memory of the first embodiment, respectively. The operation of the first embodiment will be described below with reference to these drawings.

First, the voltages Vcc and Vpp are raised (step S31), the address is initialized (step S32), and then the control signal bar WE is lowered.

Then, at the next rise of the control signal bar WE, the input data instructing the over-erase verify mode is latched in the command register 12, and at the same time, the address from the outside is latched in the address register 6 (step S).
33). After that, the input data is the command decoder 13 '.
Then, the operation mode signal OEV instructing the over-erase verify mode is output, and the over-erase verify mode is set. Subsequently, the X decoder 32 sets 0V to the word line WL designated by the address and sets the unselected word line W to 0V.
By applying a negative voltage VNCP to L, the output control signal bar O
By verifying the on / off state of the selected memory cell MC based on “1” / “0” of the verify data obtained through the sense amplifier 8 during the “L” period of E,
It is verified whether the memory cell MC is in the overerased state (step S34).

Then, in step S35, it is checked whether or not the address is the final address. If it is the final address, the process proceeds to step S37. If it is not the final address, the address is incremented in step S36 and the process proceeds to step S33. Hereinafter, the operations of steps S33 to S36 are repeated until the over-erase verification of the final address is completed.

If the final address is determined in step S36, the operation mode is set to the read mode in step S37, and the overerase verify operation is completed.

In the example of FIG. 7, the address signal ADD1
.About.ADD3 show that the memory cells MC connected to the word lines WL1 to WL3 are sequentially selected.

As described above, since the flash memory of the first embodiment can perform the overerase verify operation by setting the overerase verify mode, it is possible to detect the memory cell MC in the overerase state.

<Second Embodiment> FIG. 10 shows a second embodiment of the present invention.
5 is a flowchart showing a method of programming an overerased bit in a flash memory which is an embodiment of the present invention. This method is applied to the flash memory of the first embodiment shown in FIG.

Referring to FIG. 10, first of all, voltage V
cc and Vpp are raised (step S41), the address is initialized (step S42), the program count number X = 0 is initialized (step S43), and then the control signal bar WE is lowered.

Then, at the next rise of the control signal bar WE, the input data instructing the overerase verify mode is latched in the command register 12 (step S44).
Thereafter, the input data is decoded by the command decoder 13 ', the operation mode signal OEV instructing the overerase verify mode is output, and the overerase verify mode is set.

Next, an external address is latched in the address register 6, and the X decoder 32 applies 0 V to the word line WL designated by the address and the negative voltage VNCP to the unselected word line, In step S45, the on / off state of the selected memory cell MC is verified based on "1" / "0" of the verify data obtained via the sense amplifier 8 during the "L" period of the output control signal bar OE. As a result, it is verified whether the memory cell MC is in the overerased state, and if it passes (normal erased state), step S46.
Otherwise, the process moves to step S49.

Then, in step S46, it is checked whether or not the address is the final address. If the address is the final address, a non-defective product determination is made in step S48. If it is not the final address, the address is incremented in step S47 and the process proceeds to step S43. To do. Hereinafter, steps S43 to S4 are performed until the over-erase verification of the final address is completed.
The operation of 6 is repeated.

On the other hand, if it is determined in step S45 that the over-erased state has occurred, the process proceeds to step S49 and step S49.
Then, it is checked whether the program count number X has reached 25, and if X = 25, it is determined as a defective product in step S53. If not, the process proceeds to step S50.

Then, in step S50, the input data instructing the program mode at the next rise of the control signal bar WE is latched in the command register 12 to be in the program mode, and the memory cell MC judged to be in the over-erased state.
Then, the program operation is executed, the program count number X is incremented by 1 in step S52, and the process returns to step S44.

After that, until step S45 is passed or until it is determined at step S49 that X = 25, step S4 is performed.
The operations of 4, 45 and 49 to 52 are repeated.

As described above, in the over-erase bit programming method for the flash memory of the second embodiment, the over-erase verify operation is performed, and then the program operation is performed on the memory cell MC in the over-erased state. The erased memory cell MC can be relieved. Furthermore, if there is a memory cell MC that cannot be repaired, it can be determined as a defective product.

<Third Embodiment> FIG. 11 shows a third embodiment of the present invention.
3 is a block diagram showing a configuration of a flash memory that is an embodiment of the present invention. FIG. As shown in the figure, a control circuit 33 is newly provided. The control circuit 33 receives the operation mode signal OEV and outputs a control signal to the timer 15, address register 6, input / output buffer 9, program voltage generation circuit 10, verify voltage generation circuit 11, negative voltage generation circuit 31, and X decoder 32. To do.

The control circuit 33 has a command decoder 13 '.
When it receives the operation mode signal OEV for instructing the over-erase bit automatic write command, it becomes active and initializes the address register 6 so that "L" is output to all the data pins of the input / output buffer 9. Next, the predecode signal bar X in the X decoder 32 is selectively set to "L", and at the same time, the negative voltage generating circuit 31 outputs the negative voltage VNC of -kV.
P is output to the X decoder 32, an over-erase verify operation is performed in the same manner as in the first embodiment, and the sense amplifier 8 outputs the verify result.

Then, when the verify result indicates the overerase state "1", the control circuit 33 deactivates the negative voltage generating circuit 31 and once stops the overerase verify operation. Next, from the input / output buffer 9, the overerased state “1”
Inverted "0" data is input to the input data register, and the program voltage generated from the program voltage generation circuit 10 is supplied to the X decoder 32 and the Y decoder 5 for a time determined by the timer 15 to supply an over-erased bit memory cell. carry out the program for the MC.

When the programming is completed, the control circuit 33 restarts the over-erase verify operation again. If the over-erased memory cell MC is not detected, it is incremented to the next address and output to the address register 6. ,
While performing the above-mentioned over-erase verify operation, the program operation for the over-erased memory cell is executed. And
When the over-erase verification operation up to the final address is completed, a control signal is sent to the input / output buffer 9 to set a predetermined data pin of the input / output buffer 9 to “H” and the operation is completed. The rest of the configuration is similar to that of the flash memory of the first embodiment shown in FIG. 1 and its explanation is omitted.

[0083] Therefore, with respect to the flash memory of the third embodiment, after giving the command register 12 a signal indicative of over-erased bit auto-program command via the input signal buffer 14, the control signal (output enabler <br /> enable signal) bar OE and to "L", the leave read state, a predetermined data pin within a predetermined time ne to "H"
If it is determined that the over-erase verify operation is normally completed, a signal for ending the over-erase bit automatic write command is given to end the operation, and if a predetermined data pin remains “L” even after a predetermined time elapses. The flash memory may be regarded as a device failure and a signal for ending the over-erase bit automatic write command may be given to end the operation.

FIG. 12 is a flow chart showing the automatic erase bit automatic write operation of the flash memory of the third embodiment. Referring to the figure, first, the voltages Vcc and V
pp is raised (step S61), the next rise of the control signal bar WE latches the input data instructing the over-erase bit automatic write operation mode in the command register 12 (step S62), and then the input data is command decoder. The operation mode signal OEV which is decoded by 13 'and indicates the over-erase bit automatic write operation mode is output to the control circuit 33 to enter the over-erase bit automatic write operation mode.

Thereafter, the operations of steps S63 to S68 are performed under the control of the control circuit 33. First, the address is initialized (step S63), and the X decoder 32 applies 0V to the word line WL designated by the address and the negative voltage VNCP to the unselected word line WL, and then the step S64.
Based on the "1" / "0" of the verification data obtained through the Dese Nsuanpu 8, by verifying the ON / OFF state of the selected memory cell MC, the memory cell MC
Is over-erased, and if it passes (normal erased state), it proceeds to step S65, and if not, it proceeds to step S67.
Move to.

Then, in step S65, it is checked whether or not the address is the final address. If the address is the final address, a predetermined data pin connected to the input / output buffer 9 for instructing the non-defective product is instructed to be "H" in step S68. If it is not the final address, the address is incremented in step S66, and the process proceeds to step S64. Hereinafter, the operations of steps S64 to S66 are repeated until the over-erase verification of the final address is completed.

On the other hand, if it is determined in step S64 that the memory cell MC is in the over-erased state , the process proceeds to step S67, the program operation is executed for the over-erased bit, that is, the memory cell MC determined to be in the over-erased state, and the process returns to step S64.

Thereafter, the operations of steps S64 and S67 are repeated until the step S64 is passed.

As described above, the flash memory of the third embodiment performs the overerase verify operation only by setting the overerase bit automatic write operation mode, and detects the overerased memory cell MC by the overerase verify operation. Since the program operation is automatically performed on the memory cell MC, it is possible to automatically detect and repair the over-erased memory cell MC. In addition, it is possible to automatically perform defective product determination processing when there is a memory cell MC that cannot be repaired.

<Fourth Embodiment> FIG. 13 shows a fourth embodiment of the present invention.
3 is a block diagram showing a configuration of a flash memory that is an embodiment of the present invention. FIG. As shown in the figure, a new automatic erase control circuit 3 is newly added.
4 and an overerased bit automatic write control circuit 35 are provided. The overerased bit automatic write control circuit 35
Receiving the operation mode signal OEV, the timer 15, address register 6, input / output buffer 9, program voltage generating circuit 10, verify voltage generating circuit 11, negative voltage generating circuit 3
A control signal is output to the 1 and X decoders 32 to control the over-erase bit automatic write operation similarly to the control circuit 33 of the third embodiment.

[0091] On the other hand, the automatic erase control circuit 34 receives the operation mode signal OEV, timer 15 control, the source line switch 3, the address register 6, output buffer 9, a program voltage generating circuit 10, the verify voltage generating circuit 1 1 A control signal is output to control the erase operation.

That is, when the operation mode signal OEV directs an automatic erase operation with over-erase bit automatic write, the automatic erase control circuit 34 sets all the outputs of the data pins of the input / output buffer 9 to "L", and then the address register. 6 is initialized, a program pulse is applied to all the bits (memory cells) to perform the write operation before erasure, the address register 6 is initialized again, and the high voltage Vpp is completely supplied from the source line switch 3 within the time set by the timer 15. The erase operation is performed on all bits by sequentially applying to the bit sources. Then, during this erase operation, an erase verify operation is also executed.

That is, in order to suppress the occurrence of over-erased memory cells MC by the automatic erasing operation by the automatic erasing control circuit 34, as shown in FIG. After writing, erase operation is performed. Then, the overerase bit automatic write control circuit 35 relieves the overerase bit A1 generated when the erase operation is performed by the overerase bit automatic write operation,
The thresholds of all the memory cells MC are set within the shaded area. The rest of the configuration is similar to that of the flash memory of the first embodiment shown in FIG. 1 and its explanation is omitted.

FIG. 14 is a flow chart showing the automatic erase operation with automatic erase bit automatic write of the flash memory of the fourth embodiment. Referring to the figure, first,
The voltages Vcc and Vpp are raised (step S71), and at the next rise of the control signal bar WE, the input data instructing the automatic erasing operation mode with over-erasing bebbit automatic writing is latched in the command register 12 (step S7).
2), then the input data is decoded by the command decoder 13 ', the over-consumption rust Tsu preparative operation mode signal OEV automatic erase control circuit 34 and the over-erased bit automatic write control circuit for instructing automatic auto-erase operation mode with write Three
5 is output, and the automatic erasing operation mode with over-erasing bit automatic writing is set.

After that, the operations of steps S73 to S78 are performed under the control of the automatic erasure control circuit 34. First, the pre-erase write operation is executed (step 73), then the address is initialized (step S74), and then step S
At 75, all the memory cells M from the source line switch 3
By supplying the high voltage Vpp to the source of C, the erase operation is executed for all the memory cells MC of the memory array 1.

Then, in step S76, the verify voltage generation circuit 11 causes the erase verify voltage (.about.3.2).
V) is generated by the X decoder 32, by applying a verify voltage to the word line WL designated by the address, based on the "1" / "0" of the verification data obtained through the cell <br/> Nsuanpu 8 , By verifying the on / off state of the selected memory cell MC,
Is verified to be in an erased state, and if it passes (erased state), the process proceeds to step S77, and if not, to step S75.
Return to.

Then, in step S77, it is checked whether or not the address is the final address. If the address is the final address, the process proceeds to step S79. If the address is not the final address, the address is incremented in step S78, and the process proceeds to step S76. Hereinafter, the operations of steps S76 to S78 are repeated until the erase verification of the final address is completed.

On the other hand, if it is not erased in step S76
If it is determined , the process returns to step S75, the erase operation is executed again for all the memory cells MC, and step S76
Return to. After that, the operations of steps S75 and S76 are repeated until the step S76 is passed.

After step S79, steps S79 to S8 are performed under the control of the overerased bit automatic write control circuit 35.
The operation of 4 is performed. First, initialize the address (step S 79), the X decoder 32, a 0V to the word line WL designated by the address, by the non-selected word line WL is a negative voltage VNCP applied, step S80 Dese By verifying the on / off state of the selected memory cell MC based on "1" / "0" of the verify data obtained via the sense amplifier 8, the memory cell MC
Is verified whether it is over-erased, pass (normal erased state)
If so, go to step S81. If not, go to step S8.
Move to 3.

Then, in step S81, it is checked whether or not the address is the final address. If the address is the final address, a predetermined data pin connected to the input / output buffer 9 for instructing the non-defective product determination in step S84 is set to "H". If it is not the final address, the address is incremented in step S82, and the process proceeds to step S80. Hereinafter, the operations of steps S80 to S82 are repeated until the over-erase verification of the final address is completed.

On the other hand, if it is determined in step S80 that the memory cell MC is in the over-erased state , the process proceeds to step S83, the program operation is executed for the over-erased bit, that is, the memory cell MC determined to be in the over-erased state, and the process returns to step S80. . Or later,
Until the pass at step S80, steps S80 and S
The operation of 83 is repeated.

As described above, the flash memory according to the fourth embodiment is set only in the automatic erase operation mode with over-erase bit automatic write, and after performing the write operation before erase and the erase operation with erase verify automatically, An over-erase verify operation is performed, and when this over-erase verify operation is performed, a program operation is automatically performed on the over-erased memory cell MC as in the third embodiment. After this, the detection and repair processing of the over-erased memory cell MC can be performed. In addition, it is possible to automatically perform defective product determination processing when there is a memory cell MC that cannot be repaired.

<Fifth Embodiment> FIG. 16 shows a fifth embodiment of the present invention.
3 is a flowchart showing an operation of an unerased bit erasing method of the flash memory which is the embodiment of the present invention. This method is applied to the flash memory of the first embodiment shown in FIG.

Referring to the figure, first, the voltage Vc
c and Vpp are raised (step S91), and then "0" is written in all bits by using the same program flow as in the conventional case (step S92).

After that, the program count number X and the erase count number Y are initialized to 0 (step S93), and then the erase command is input (step S94) to perform the erase operation, and all bits of the memory array 1 are processed. Is erased (step S95). Then, after the erase count number Y is incremented (step S96), the address is initialized (step S97).

Then, an erase verify command is input (step S98), and it is verified in step S99 whether the erase count number Y reaches 1000. If not, the process proceeds to step S100, and if so, step S10.
Go to 6.

In step S100, the erase verify operation is executed to verify whether or not the memory cell MC is in the erased state. If the memory cell MC passes (erased state), step S10 is performed.
If not, the process returns to step S94.

In step S101, an over-erase verify command is input from the outside, and in step S102, the over-erase verify operation is executed, whereby the memory cell MC
Is over-erased, and if it passes (normal erased state), it proceeds to step S103, and if not, it proceeds to step S1.
Move to 07.

[0109] Then, at step S103, checks whether the address is the last address, if the last address was judged to be good, if the final address step S1
The address is incremented in 04, and step S10
The program count number X is set to 0 in step S98.
Move to. Hereinafter, the operations of steps S98 to S105 are repeated until the over-erase verification of the final address is completed.

On the other hand, if the program count number X is judged to be 1000 in step S99, the erase verify operation is executed in step S106. If the program passes (erased), the process proceeds to step S101. judge.

If it is determined in step S100 that the memory cell is not in the erased state, the process returns to step S94 and the erase operation is performed again on all the memory cells MC.

On the other hand, if it is determined in step S102 that the overerased state has occurred, the process proceeds to step S107 and step S1.
In 07, it is determined whether or not the program count number X has reached 25. If it has reached it, it is determined to be a defective product, and if it has not reached, the process proceeds to step S108.

In step S108, a program command is input from the outside, and in step S109, an overerase bit program operation is performed to generate an overerase bit, that is, an overerase state.
The program operation is executed for the memory cell MC determined to be in the state , the program count number X is incremented in step S110, an erase verify command is input from the outside in step S98, and over-erase after programming is performed in step S100 or step S106. memory cell <br/> Le state to perform whether the erase verify operation has become non-erased state.

If it is determined in step S100 that the over-erased memory cell after programming is in the non-erased state, the erase command is input again in step S94.
Then , the erase operation is performed to erase all the bits of the memory array 1 (step S95).

FIG. 17 is a graph showing the VG-ID characteristic of the memory cell MC. In the figure, L4 is a normal write state characteristic curve, L6 is a normal erased state characteristic curve, L7 is an over erased state characteristic curve, L5 is an unerased state characteristic curve, and DV is an erase verify voltage. As shown in the figure, if the memory cell MC in the over-erased state is programmed, the threshold value may rise above the normal erased state and reach the characteristic curve in the unerased state indicated by L5. The memory cell MC in such a state is erased again and L
The flash memory of the fifth embodiment is capable of returning to the normal erased state shown in FIG.

In the flash memory of the fifth embodiment, there is a memory cell MC which is in an unerased state even after 1000 erase operations, or a memory cell which is in an over-erased state after 25 program operations. If the cell MC exists, it is determined to be defective.

As described above, in the over-erase bit programming method for the flash memory of the fifth embodiment, the over-erase verify operation is performed, and then the programming operation is performed on the memory cell MC in the over-erased state. The erased memory cell MC can be relieved. Furthermore, if there is a memory cell MC that cannot be repaired, it can be determined as a defective product.

In addition, after the unerased verify operation is performed, if there is an unerased memory cell MC, the erasing operation is performed so that the memory cell MC that has been unerased by the program operation is also removed. Can be rescued. Furthermore, if there is a memory cell MC that cannot be repaired, it can be determined as a defective product.

<Sixth Embodiment> FIG. 18 shows a sixth embodiment of the present invention.
3 is a block diagram showing a configuration of a flash memory that is an embodiment of the present invention. FIG. As shown in the figure, a control circuit 36 is newly provided. The control circuit 36 controls the operation mode signal OEV.
In response, the timer 15, the source line switch 3, the address register 6, the input / output buffer 9, the program voltage generating circuit 10, the verify voltage generating circuit 11, the negative voltage generating circuit 3 are received.
1 and outputs a control signal to the X decoder 32 to control the automatic erasing operation with overerasure countermeasures.

That is, when the operation mode signal OEV instructs the automatic erase operation with overerasure countermeasure, the control circuit 36 sets all the outputs of the data pins of the input / output buffer 9 to "L", and then initializes the address register 6. , The program pulse is applied to all bits (memory cells) to perform the pre-erase write operation, the address register 6 is initialized again, and the high voltage Vpp is supplied from the source line switch 3 to the source of all bits within the time set by the timer 15. Sequential application is performed to erase all bits. Then, during this erase operation, an erase verify operation is also executed, and if there is an unerased memory cell MC, the erase operation is executed.

Further, the control circuit 36 executes the over-erase verify operation if it passes the erase verify, and executes the program operation for the memory cell MC in the over-erased state.
Then, after the program operation, the memory cell M in the non-erased state
If C exists, the erase operation is re-executed, and if there is an over-erased memory cell MC, the program operation is performed. In addition,
The other structure is the same as that of the flash memory of the first embodiment shown in FIG. 1, and therefore its explanation is omitted.

FIG. 19 is a flow chart showing the automatic erase operation with overerasure countermeasure of the sixth embodiment. Referring to the figure, first, the voltages Vcc and Vpp are raised (step S111), and at the next rise of the control signal bar WE, the input data for instructing the automatic erase operation mode with overerasure countermeasure is the command register. 12 (step S112), and then the input data is the command decoder 1
The operation mode signal OEV which is decoded by 3'and indicates the automatic erase operation mode with overerasure countermeasure is output to the control circuit 36, and the automatic erase operation mode with overerasure countermeasure is set.

Thereafter, the operations of steps S113 to S121 are performed under the control of the control circuit 36. First, step S
At 113, the pre-erase write operation is executed. Next, in step S114, the high voltage Vpp is supplied from the source line switch 3 to the sources of all the memory cells MC, thereby executing the erase operation for all the memory cells MC of the memory array 1. Then, in step S115, the address is initialized.

Then, in step S116, an erase verify operation is performed to verify whether or not the memory cell MC is in the erased state. If the memory cell MC passes (erased), step S1
If not, the process returns to step S114.

Then, in step S117, it is verified whether the memory cell MC is in the over-erase state by executing the over-erase verify operation, and if the memory cell MC is in the over-erase state (normal erase state), the process proceeds to step S118, otherwise. S120
Move to.

Then, in step S118, it is checked whether or not the address is the final address. If the address is the final address, in step S121 it is determined as a non-defective product, a predetermined data pin is set to "H", and the process is terminated. If not, the address is incremented in step S119,
Control goes to step S116. Hereinafter, steps S116 to S11 are performed until the erase verification of the final address is completed.
The operation of 9 is repeated.

On the other hand, it is not in the erased state in step S116.
If it is determined that the erase operation is performed again on all the memory cells MC, the process returns to step S114.
Address initialization is performed at 115, and the process returns to step S116. After that, the operations of steps S114 to S116 are repeated until the step S116 is passed.

On the other hand, if it is determined in step S117 that the memory cell MC is judged to be in the over-erased state, the operation proceeds to step S120, the program operation is executed for the memory cell MC judged to be in the over-erased bit, that is, the over-erased state, and the processing returns to step S116. ,
After the erase verify operation, the process returns to step S117. Thereafter, steps S116 and S117 are performed until the step S116 fails or the step S117 is passed.
And the operations of S120 are repeated.

As described above, the flash memory of the sixth embodiment automatically performs the pre-erase write operation and the erase operation with erase verify simply by setting the automatic erase operation mode with over-erase countermeasure, and then the over-erase verify operation. When performing the over-erase verify operation, the program operation is automatically performed for the memory cell MC in the over-erased state as in the third and fourth embodiments. After being automatically performed, the detection and repair processing of the over-erased memory cell MC can be automatically performed. In addition, it is possible to automatically perform defective product determination processing when there is a memory cell MC that cannot be repaired.

[0130] In addition, the flash memory of the sixth embodiment, subsequently subjected to non-erase verification operation, as long presence of the memory cell MC of the non-erased state recognized by the non-erase verification operation and executes the erase operation As a result, the memory cell M which has not been erased by the program operation
C can also be rescued. In addition, it is possible to automatically perform defective product determination processing when there is a memory cell MC that cannot be repaired.

<Seventh Embodiment> FIG. 20 shows a seventh embodiment of the present invention.
3 is a block diagram showing an internal configuration of a timer of the flash memory which is the embodiment of FIG. The timer shown in the figure corresponds to the timer 15 in the flash memories of the first to sixth embodiments shown in FIGS. 1, 11, 13, and 18.

In the figure, the signal PRS is a signal which becomes "H" at the time of programming, the signal POE is a signal which becomes "H" only at the time of programming the over-erased bit, and TIME is an output signal of the timer 15. In the flash memory having the configuration shown in FIG. 1, the signal PRS and the signal POE are signals output from the command decoder 13 ', and in the flash memory having the configuration shown in FIG. 11, the signal PRS is output from the command decoder 13' or the control circuit 33. The signal POE is a signal output, and the signal POE is a signal output from the control circuit 33. In the flash memory having the configuration shown in FIG. 13, the signal PRS is a signal output from the command decoder 13 ′ or the overerase bit automatic write control circuit 35, and the signal POE is output from the overerase bit automatic write control circuit 35. Signal. Further, in the flash memory having the configuration shown in FIG. 18, the signal PRS is a signal output from the command decoder 13 ′ or the control circuit 36, and the signal POE is a signal output from the control circuit 36.

As shown in FIG. 20, the oscillation signal φ of the oscillation circuit 61 is output to one input of the transfer gate 65 through the frequency dividing circuits 62 to 64 connected in series, and only the frequency dividing circuit 62 is output. After that, it is output to the transfer gate 66.

The oscillating circuit 61 and the frequency dividing circuits 62 to 64 are activated when the signal PRS is "H", and perform an oscillating operation and a frequency dividing operation, respectively. Signal POE is transfer gate 6
5 of the PMOS gate portion and N of the transfer gate 66
Is output to the MOS gate portion, the inverter 67
Is input to the NMOS gate section of the transfer gate 65 and the PMOS gate section of the transfer gate 66. Then, the signal obtained from the other input of the transfer gates 65 and 66 becomes the output signal TIME.

In such a configuration, during normal programming, the signal PRS becomes "H" and the signal POE becomes "L", so that the transfer gate 65 is turned on and the transfer gate 66 is turned off, so that it is relatively long. An output signal TIME having a pulse width is output. On the other hand, when the over-erased bit is programmed, the signal PRS becomes “H” and the signal POE becomes “H”, the transfer gate 66 is turned on and the transfer gate 65 is turned off. Therefore, the output signal TIME having a relatively short pulse width is output. Is output.

Therefore, the memory cell MC in the over-erased state
On the other hand, when executing the over-erase bit program, the program operation is performed within a relatively short program time,
Since the program operation time having a positive correlation with the rise of the threshold voltage is shorter than the normal time, the threshold of the memory cell MC in the over-erased state is raised too much to reduce the risk of leaving it in the non-erased state. it can.

<Eighth Embodiment> FIG. 21 shows an eighth embodiment of the present invention.
3 is a circuit diagram showing an internal configuration of a program voltage generation circuit 10 of the flash memory which is the embodiment of FIG. The program voltage generating circuit shown in FIG.
This corresponds to the program voltage generation circuit 10 in the flash memories of the first to sixth embodiments shown by 8.

As shown in the figure, the transistors Q11 to Q11
A current mirror circuit 42 composed of Q15 and having "H" as a high voltage Vpp, a CMOS inverter 43 composed of transistors Q16 and Q17, and transistors Q18 to Q23.
And resistors R1 and R2. The configuration of the characteristic part will be described below.

The resistors R1 and R2 are connected in series between Vpp and ground, and the node N1 between the resistors R1 and R2 forms one differential transistor Q1 in the current mirror circuit 42.
3 is connected.

The signal obtained from the drain of the PMOS transistor Q22 whose source is the high voltage Vpp becomes the program voltage VP of the program voltage generating circuit 10, the drain of the NMOS transistor Q21 is connected to the gate of the transistor Q22, and the source of the transistor Q21 is Grounded.

The signal POE is N with Vcc applied to its gate.
The output of the inverter 43 is input to the gate of the transistor Q15 of the inverter 43 and the current mirror circuit 42 via the MOS transistor Q19.
It is given to the gate of 1. The signal POE is a signal which becomes "H" only when programming an overerased bit.

In such a configuration, since the signal POE becomes "L" during normal programming, the transistor Q
Since 15 is turned off and the current mirror circuit 42 is deactivated and the transistor Q21 is turned on, the program voltage VP becomes Vpp. On the other hand, since the signal POE becomes "H" at the time of programming the overerased bit, the transistor Q15
Turns on and the current mirror circuit 42 becomes active,
A voltage obtained by resistance-dividing the high voltage Vpp from the resistors R1 and R2 is output as the program voltage VP.

Therefore, the memory cell MC in the over-erased state
On the other hand, when the over-erase bit program is executed, the program operation is performed at a relatively low program voltage. It is possible to reduce the risk of causing the non-erased state by raising the MC threshold too much.

[0144]

As described above, the non-volatile semiconductor memory device according to the first aspect of the present invention can be verified.
Voltage generation means, off-voltage generation means and erase / write operation
Since the row means is provided, over-erasure is performed after the erase operation is executed.
Memory transistor over-erased by verify operation
Can be verified. In addition, over-erased memo
Write to the transistor and write
It is in the non-erased state due to the unerased verify operation after the operation.
Erase operation if there is a memory transistor recognized as
It can be performed. As a result, the erase operation was performed.
After that, it is possible to rescue the over-erased memory transistor.
Yes, and it was in the unerased state after the above write operation
The memory transistor can also be repaired.

Nonvolatile according to claim 2 of the present invention
The method of erasing a semiconductor memory device includes writing an overerased bit.
The unerased verify for the memory transistor after the operation is executed.
A) and the verification result of the unerased verify operation is not erased.
Erased when the presence of a memory transistor in the off state is indicated
By executing the operation, the
Rescue even erased memory transistors
You can

[0146]

[0147]

[0148]

[0149]

[0150]

[0151]

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a flash memory that is a first embodiment of the present invention.

FIG. 2 is a graph showing drain current-gate voltage characteristics of a memory cell.

FIG. 3 is an explanatory diagram for explaining the operation of the first embodiment.

FIG. 4 is an explanatory diagram showing a memory array and its periphery.

5 is a circuit diagram showing an internal configuration of the negative voltage generating circuit of FIG.

FIG. 6 is a circuit diagram showing a part of an internal configuration of the X decoder of FIG.

FIG. 7 is a timing chart showing the operation of the first embodiment.

FIG. 8 is a flowchart showing the operation of the first embodiment.

FIG. 9 is a timing chart showing the operation of the X decoder.

FIG. 10 is a flowchart showing a method of programming an overerased memory cell according to a second embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a flash memory that is a third embodiment of the present invention.

FIG. 12 is a flowchart showing the operation of the third embodiment.

FIG. 13 is a block diagram showing a configuration of a flash memory that is a fourth embodiment of the present invention.

FIG. 14 is a flowchart showing the operation of the fourth embodiment.

FIG. 15 is a graph showing a threshold distribution of memory cells.

FIG. 16 is a flowchart showing an operation of a programming method for an overerased memory cell according to a fifth embodiment of the present invention.

FIG. 17 is a graph showing drain current-gate voltage characteristics of a memory cell.

FIG. 18 is a block diagram showing a configuration of a flash memory that is a sixth embodiment of the present invention.

FIG. 19 is a flowchart showing the operation of the sixth embodiment.

FIG. 20 is a circuit diagram showing an internal configuration of a timer in a flash memory which is a seventh embodiment of the present invention.

FIG. 21 is a circuit diagram showing an internal configuration of a program voltage generating circuit in a flash memory which is a seventh embodiment of the present invention.

FIG. 22 is a block diagram showing a configuration of a conventional flash memory.

FIG. 23 is a cross-sectional view showing a memory cell structure of a conventional flash memory.

FIG. 24 is a circuit diagram showing the periphery of the memory array of FIG. 22.

FIG. 25 is a flowchart showing a conventional write operation.

FIG. 26 is a flowchart showing a conventional erase operation.

FIG. 27 is a timing diagram showing a conventional write operation.

FIG. 28 is a timing diagram showing a conventional erase operation.

[Explanation of symbols]

1 memory array 2 Y gate 3 Source line switch 5 Y decoder 6 Address register 7 Input data register 8 sense amplifier 9 I / O buffer 10 Program voltage generator 11 Verify voltage generator 12 Command register 13 'command decoder 14 Input signal buffer 15 timer 31 Negative voltage generator 32 X decoder 33 Control circuit 34 Automatic erasure control circuit 35 Over erase bit automatic write control circuit 36 Control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-6-28875 (JP, A) JP-A-5-210991 (JP, A) JP-A-5-89688 (JP, A) JP-A-6- 203590 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 16/00

Claims (2)

(57) [Claims] 1. A plurality of memos that can be electrically written and erased.
Any one of the plurality of memory cells having a retransistor
Write operation that selectively raises the threshold voltage
Note: An eraser that lowers the threshold voltage of multiple memory transistors.
Non-volatile semiconductor memory device having a function of executing
A location, a normal erased state of being lowered to a predetermined level threshold voltage of the memory
If it is a transistor, it is turned off, and the threshold value of the normal erased state
Over-extinguishing with a threshold voltage lower than the voltage by more than a predetermined level
If the memory transistor is in the off state,
Verify voltage generating means for generating a verify voltage, and forcibly even the memory transistor in the over-erased state
Off voltage generation that generates off voltage at the level to turn off
Means for performing the erase operation, and thereafter performing the erase operation.
Of the selected memory transistor
The verify voltage is applied to the
In applying the off-voltage to the gate of the transistor
ON / OFF of the memory transistor in the selected state
Based on the above, verify whether the normal erased state or over erased state
Over-erase verify operation is executed and the selected memory
If the transistor is in the over-erased state,
Performing the write operation on the memory transistor,
The memory transistor in the over-erased state after executing this write operation
The threshold voltage of the
Whether or not it is in the non-erased state with the threshold voltage increased by more than
The unerased verify operation to be verified is executed to
When the verification result of the refine operation indicates the unerased state,
Erasing / writing executing means for executing the erasing operation again
A non-volatile semiconductor memory device comprising: 2. A plurality of memos that can be electrically written and erased.
Any one of the plurality of memory cells having a retransistor
Write operation that selectively raises the threshold voltage
Note: The threshold voltage of multiple memory transistors is lowered to erase them.
Non-volatile with the function to execute the erase operation to leave
A method for erasing a non- volatile semiconductor memory device, the method comprising the steps of performing the erasing operation and the memory transistor on which the erasing operation is performed.
The voltage has dropped below the threshold voltage for normal erasing by a specified level or more.
With an over-erased memory transistor having a different threshold voltage
Perform over-erase verify operation to verify whether there is
And a verification result of the over-erase verification operation,
Results showed the presence of over-erased memory transistors
When the memory transistor in the over-erased state is
The step of executing the write operation, and the memory transistor after executing the write operation,
The voltage rises above the threshold voltage in the normal erased state by a predetermined level or more.
Unerased to verify whether it is in an unerased state with a certain threshold voltage
The step of executing the verify operation and the verification result of the unerased verify operation indicate that the unerased state is
When the presence of a memory transistor is indicated, the erase operation is
A non-volatile semiconductor memory device having steps of executing
Erase method.