JPH0628875A - Method for erasing frash type eeprom - Google Patents

Abstract

PURPOSE:To prevent excess erasure, to widen a read margin and to be advanta geous for acceleration by impressing negative voltage to the control gate of a nonselective cell at a verifying time. CONSTITUTION:By impressing e.g. 1V to a word line WL1, and selecting a bit line BL1, the threshold value voltage Vth of a cell at an intersection between the word line WL1 and the bit line BL1 is read, and whether it is an erasure decision level or below or not is judged. E.g. -5V negative voltage is impressed to the control gate of the nonselective cell at the verifying time. Further, after it is confirmed that the threshold value voltages Vth of all cells are the decision level or below, rewriting is performed for an excess erasure cell in word line unit till the threshold value voltage becomes 0V or above. Thus, the excess erasure is prevented even in an initial state and even when the number of times of rewriting is increased, and the read margin is taken widely and an erasure method advantageous for acceleration is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a flash type E ² PR.
The present invention relates to an OM erasing method, which relates to an erasing method for a flash type E ² PROM in which pre-erase programming is performed on all cells to be erased and then erasing and verifying are repeated.

[0002]

^2. Description of the Related Art Flash (batch erase) type E ² PROM
In the above, since the capacitive coupling ratio between the source and the floating gate differs depending on the cell, the threshold voltage V _th after erasure varies. Variation in the threshold voltage V _th is the threshold voltage V _th is the cause of over-erasure of less than 0V.

A cell in the over-erased state becomes a fatal defect. That is, when a cell on the bit line is read, if an overerased cell exists on the same bit line, a current flows through the cell in the overerased state, so that the cell in the off state (written state) is turned on. You will make an incorrect decision. In addition, since the current flows through the cell in the over-erased state, the potential of the bit line cannot be sufficiently raised, so that writing cannot be performed.

[0004]

By the way, conventionally, when erasing a flash type E ² PROM, after erasing before writing "0" to all cells of a sector to be erased, erasing and The verify operation was repeated to erase the data little by little, and the erase operation was completed when the threshold voltage V _th fell below the judgment level.

However, in the above-described conventional erasing method, since erasing and verifying are repeatedly performed and data is erased little by little, depletion (Dep
It became a letion), and there was a possibility that it would be over-erased. Further, as the number of times of rewriting increases, as shown in FIG. 7, there is a problem that the V _th distribution is widened and the possibility of over-erasing is further increased. Also, to avoid over-erasing,
The threshold level of the threshold voltage V _th at the time of erasing may be set high, but if it is set to about 3 V, the read margin becomes narrow,
There was also a problem that it hindered the speedup.

The present invention has been made in view of the above-mentioned points, and there is no excessive erasure even when the number of times of rewriting is increased, not to mention the initial state, and the read margin can be widened.
Another object of the present invention is to provide a method of erasing a flash type E ² PROM which is advantageous for speeding up.

[0007]

To achieve the above object, according to the present invention, after performing pre-erase programming on all cells to be erased, erasing and verifying are repeated until the threshold voltage falls below a judgment level. Flash type E ² PR
In the OM erasing method, a negative voltage is applied to the control gates of non-selected cells during verification. After erasing, rewriting and verification are repeatedly performed on the overerased cell until it is not overerased, and a negative voltage is applied to the control gate of the non-selected cell at the time of verification during this rewriting.

[0008]

By applying a negative voltage to the control gate of the non-selected cell at the time of verification, no current flows in the overerased cell, so that verification can be performed even if the overerased cell exists. Therefore, the erase determination level can be set lower than that in the related art, and the pulse width of the drain applied erase pulse can be made wider than that in the related art, since overerasure may be performed during the erase. In addition, the threshold voltage V of all cells
After confirming that _th becomes equal to or lower than the determination level, rewriting and verifying are performed on the overerased cells in units of word lines until the threshold voltage V _th becomes 0 V or more.
The V _th distribution is set within a fairly narrow range on the low potential side.

[0009]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing an example of the circuit configuration of an E ² PROM according to the present invention. In FIG. 1, the cell
A row decoder 2 is connected to the word lines WL _{1 to} WL _n of the array 1, and a column decoder 3 is connected to the bit lines BL _{1 to} BL _m . The row decoder 2 drives various voltages, and therefore, for example, a positive power supply V _ROWP having a voltage value of 1V, 5V, 12V.
, And a negative power supply V _ROWN having a voltage value of −5 V, −10 V, and a C-MOS inverter configuration of MOS transistors T ₁ and T _{2 of} opposite conductivity type connected in series with each other.

In the row decoder 2, the drains of the MOS transistors T ₁ and T ₂ are connected to the word line WL, and the gates are commonly connected to form a row input Row in. Row input Row in is 0V / V _PP or 0V / V _DD
Level conversion circuit (not shown) according to each operation mode
Generated through. As a result, in each operation mode, the voltage applied to each word line WL during selection / non-selection is as shown in Table 1.

[Table 1] The MOS transistors T ₁ and T ₂ of the C-MOS inverter structure are formed in a double well structure as shown in FIG.

A control circuit 4 for controlling write, rewrite, read, erase and verify operations is provided commonly to each of the _m bit lines BL _{1 to} BL _m . In this control circuit 4, the MOS switch 5 is used for reading and verifying.
Is on, and when writing and rewriting, MO
The S switch 6 is in the on state. Then, the data read via the sense amplifier 7 is output as read data as it is at the time of reading, and the MO data at the time of verifying.
It is latched by the latch circuit 9 via the S switch 8.

On the other hand, at the time of normal writing, the data supplied from the I / O buffer (not shown) is the latch circuit 10.
Is applied to the drain electrode of the memory cell selected by the row decoder 2 and the column decoder 3 after being level-converted by the level conversion circuit 12 and further latched by the latch circuit 9 via the MOS switch 11. It The level conversion circuit 12 performs level conversion into a power supply voltage of 6 V for writing and 5 V for reading, for example.

Next, the processing procedure of the erasing method according to the present invention will be described with reference to the flowchart of FIG. In addition,
In pre-erase programming, in order to make the threshold voltage V _th before erasing uniform, "0" is written to all cells to be erased in block units (or all cells at once) in which the cell array 1 is divided into blocks. It is assumed that First, the erase cycle (A) will be described with reference to the timing chart of FIG. First, for example, -10 is added to each word line WL.
Erasing is performed by applying V, for example, 5 V to the source electrode of each cell (step S11).

Next, by applying, for example, 1 V to the word line WL ₁ and selecting the bit line BL ₁ (steps S12 and S13), the word line WL ₁ and the bit line B are selected.
The threshold voltage V _th of the cell located at the intersection of L ₁ is read, and it is determined whether or not this threshold voltage V _th is equal to or lower than the erase determination level of 1 V (V _th ≦ 1 V) (step S
14). During this verification, the control gates of non-selected cells via the word line WL ₂ to WL _n for example, a negative voltage of -5V is applied.

If it is determined in step S14 that V _th > 1V, the process returns to step S11 to erase all the cells collectively, and the additional erase and verify are performed with the threshold voltage V _th of 1 V or less. Repeat until
On the other hand, if it is determined that V _th ≦ 1 V, then step S15
Then, the next bit line BL ₂ is selected (step S1
6) Then, returning to step S14, the bit line BL ₂
Of the threshold voltage V _th is determined, and this verification is repeated for all bit lines (step S15).

After erasing and verifying the word line WL ₁ , the next word line WL ₂ is selected through step S17 (step S18), and then the process returns to step S13 and the bit lines BL _{1 to} BL _m are sequentially processed. The above process is repeated, and verification and additional erasing are repeated until the threshold voltage V _th becomes 1 V or less for all word lines (step S17).

As described above, by applying a negative voltage to the control gates of the non-selected cells at the time of verify, no current flows in the over-erased cells, so even if a plurality of word lines are simultaneously erased, that is, over-erased. You can verify even if cells exist. Therefore, since it does not matter if the erase operation is over-erased, it is possible to set the erase determination level lower than that of the conventional one (about 1 V) and to make the pulse width of the drain applied erase pulse wider than that of the conventional one. In this example, the additional erasing after the verify is performed collectively for all cells, but it is also possible to perform the additional erasing for each cell group connected to the selected word line, that is, for each row. .

Next, the V _th adjustment cycle (B) will be described with reference to the timing chart of FIG. First,
The potential of the word line WL ₁ is set to 0V, and the bit line BL ₁
By selecting (steps S21 and S22), the threshold voltage V _th of the cell located at the intersection of the word line WL ₁ and the bit line BL ₁ is read, and this threshold voltage V _th is 0.
It is determined whether or not it is V or less, that is, whether or not it is an overerased cell (step S23). At the time of this verification, the word lines WL ₂ to
A negative voltage of, for example, −5 V is applied via WL _n so that current does not flow even in the overerased cell.

When it is determined in step S23 that the cell is an over-erased cell, 12 V is applied to the word line WL ₁ to write to the over-erased cell (step S24). At the time of this rewriting, the word line WL of the non-selected cell
The potential of _{2 to} WL _n is maintained at 0V. Further, the shift amount of the threshold voltage V _th is suppressed to be small by using the write pulse having the narrow pulse width. Although 12 V is applied to the control gate of the cell at the time of rewriting through the word line WL, the control gate voltage is 5 to 1
An appropriate value can be taken within the range of 2V.

The verification and rewriting processes are
This is repeated until all cells connected to the word line WL ₁ are not over-erased (steps S25 and S26). Then, the next word line WL ₂ is selected (step S27),
Then, the process returns to step S23 and the bit lines BL _{1 to} BL
_The above-described processing is sequentially repeated for _m , and verification and rewriting are repeated until all over-erased cells are eliminated for all word lines (step S28).

As described above, after erasing with an erase pulse having a relatively wide pulse width and confirming that the threshold voltage V _{th of} all cells has become equal to or lower than the judgment level (1 V in this example), word line unit By rewriting the over-erased cell until the threshold voltage V _th becomes 0 V or more, the V _th distribution can be set in a considerably narrow range (0 to 1 V) as shown in FIG. It is possible to realize erasure without excessive erasure in which the V _th distribution is uniform on the low potential side. Further, since the threshold voltage V _{th is set} to 0 V or more by rewriting, the problem of excessive erasing does not occur not only in the initial state but also when the number of rewriting after passing to the user increases. Further, since the erase determination level can be set low, the read margin can be widened, which is advantageous for speeding up, and there is a margin in the read margin even if the power supply voltage is expected to be 3V (3V / 12V) in the future.

It should be noted that in FIG. 2, deletion (step S1
The processing of 1) and rewriting (step S24) may be performed collectively for all cells of the cell array 1, or may be performed in block units by dividing the cell array 1 into blocks. You may do it.

[0023]

As described above, according to the present invention,
By applying a negative voltage to the control gate of the non-selected cell at the time of verify, the current does not flow to the over-erased cell and the verification can be performed even if there is an over-erased cell. Since it does not matter, the erasing determination level can be set lower than the conventional level, and the pulse width of the drain applied erasing pulse can be set wider than the conventional level.

Further, after confirming that the threshold voltages V _{th of} all cells have become equal to or lower than the determination level, rewriting is performed on the over-erased cells in units of word lines until the threshold voltage V _th becomes 0 V or higher. By doing so, it is possible to realize erasure without excessive erasure in which the V _th distribution after erasure is uniform on the low potential side. Further, since the threshold voltage V _{th is set} to 0 V or more by rewriting, the problem of excessive erasure does not occur not only in the initial state but also when the number of rewrites after passing to the user increases, and the erasing determination level is further lowered. Because it can be set,
The read margin can be widened, which is advantageous for speeding up, and the read margin can have a margin even if the power supply voltage is expected to be 3 V in the future.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a circuit configuration of an E ² PROM according to the present invention.

FIG. 2 is a flowchart showing a processing procedure of an erasing method according to the present invention.

FIG. 3 is a timing chart of an erase cycle.

FIG. 4 is a timing chart of a V _th adjustment cycle.

FIG. 5 is a structural diagram of a MOS transistor having a C-MOS inverter configuration.

FIG. 6 is a V _th distribution diagram according to the present invention.

FIG. 7 is a V _th distribution diagram according to a conventional example.

[Explanation of symbols]

 1 cell array 2 row decoder 3 column decoder 4 control circuit 7 sense amplifier 9 and 10 latch circuit 12 level conversion circuit

Claims (5)

[Claims] 1. A flash type E ² PR in which pre-erase programming is performed on all cells to be erased, and then erasing and verifying are repeated until a threshold voltage falls below a judgment level.
In the OM erasing method, a flash type E ² PR is characterized in that a negative voltage is applied to the control gate of a non-selected cell at the time of verification.
How to erase OM. 2. The flash type E ^{2 according} to claim 1, wherein additional erasure after verification is performed in a lump.
How to erase PROM. 3. The flash type E ^{2 according} to claim 1, wherein the additional erasing after the verification is performed in units of rows.
How to erase PROM. 4. After erasing, rewriting and verifying are repeatedly performed on an overerased cell until it is no longer overerased, and a negative voltage is applied to a control gate of a non-selected cell at the time of verifying during this rewriting. The method for erasing a flash type E ² PROM according to claim 1, wherein 5. The method of erasing a flash type E ² PROM according to claim 1, wherein all cells to be erased are divided into blocks and erased or rewritten.