JPH09305559A - Duplex control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently control a duplex system by accelerating the transfer of a lot of data between a storage device and an input/output device by performing control through a direct memory access controller(DMAC) provided at an input/output controller. SOLUTION: One of processor systems 10i of '0' and '1' systems is operated as an active system and the other system is operated as a reserve system. According to the instruction from a controller 11i of the active system, a bus switch 201 of an input/output controller 200 is switched and connected to a system bus 13j of the reserve system and according to the control of a DMAC 202, data are transferred between a storage device 12j of a processor system 10j of the reserve system and an input/output device 301. Thus, only by performing setting in the input/output controller 200 according to a command from the processor system 10i of the active system and the processor system 10j of the reserve system, the DMAC 202 of the input/output controller 200 mainly transfers the data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual control system including a dual processor system, a single input / output device, and an input / output control device.

For example, in the case of configuring an information processing system, in consideration of cost performance, the processor system (consisting of a control device and a storage device) which directly affects the reliability of the system has a duplicated structure, and its failure is I / O devices and I / O controllers that do not significantly affect the reliability of the system often have a single configuration.

In such a configuration, there is a demand for a dual control system capable of efficiently performing a data transfer process when transferring a large amount of data between a storage device and an input / output device of a processor system.

[0004]

2. Description of the Related Art FIG. 10 is a block diagram for explaining a conventional duplex control system. 100 and 101 in the figure are 0
System processor system and system 1 system system, the 0 system processor system comprises a control device 110, a storage device 120, a system bus 130, the 1 system processor system 101 is the same configuration as the 0 system processor system 100, It is composed of a control device 111, a storage device 121, and a system bus 131, and an interprocessor communication bus is provided between the 0-system and 1-system processor systems 100 and 101.
They are connected at 140.

Reference numeral 200 denotes an input / output control device, which includes a bus switch 201, a bus control circuit 203, a floppy disk control circuit (shown as FDC in the figure) 206A, a hard disk control circuit (shown as HDC in the figure) 206B and LA.
An N control circuit (denoted by LANC in the figure) 206C and an internal bus 207, a floppy disk (denoted by FD in the figure) 301A, a hard disk (H in the figure).
(Shown as D) 301B, and is connected to the maintenance console 301C via the communication line 302.

For example, when the above-mentioned duplex control system is adopted as the exchange device, one of the 0-system and 1-system processor systems is operated as the active system, the exchange processing is executed, and the other processor system is used as the standby system. I am trying.

Here, when a large amount of data such as software version upgrade, traffic data, billing data, etc. is input / output, the following processing is performed. Current processor system 10i (i = 0 or 1)
The memory 12i and the input / output device (the floppy disk 301A, the hard disk 3) are controlled under the control of the controller 11i.
01B and maintenance console 301C are collectively referred to as an input / output device).

For example, a one-sided processor system 1
When 0i becomes a failure, the normal processor system 10i issues an instruction to the failed processor system 10j (i = 1 or 0) for failure analysis, and the storage device 1
The contents of 2j are communicated between processors to output data.

[0009]

In the above-mentioned conventional method,
In the case of (1), since the system bus of the active system is occupied for data transfer, the online processing is affected. Therefore, in order to reduce the influence on online processing, it is necessary to provide a high-speed system bus or mount a high-performance processor, which increases the cost of the system.

In the case of the above, in the failure mode in which the failed processor system cannot respond to the processor communication, the data cannot be taken out to the input / output device and the failure analysis becomes difficult.

The present invention intends to realize a duplex control system capable of efficiently transferring a large amount of data between a standby system memory and an input / output device without affecting the processing of an active processor system.

[0012]

FIG. 1 is a block diagram for explaining the principle of the present invention. The figure shows a redundant control system, and 100 in the figure is a control device 110 and a storage device 120.
Is a 0-system processor system, and 101 is
Reference numeral 200 denotes a 1-system processor system including a control device 111 and a storage device 121, and 200 is connected to 0-system and 1-system system buses 130 and 131 via a bus switch 201 that selectively connects a predetermined system bus 13i. ,
It is an input / output control device for connecting to a predetermined input / output device 301.

According to the present invention, the input / output control device 200 is set to 0
Storage device 1 of 1-system and 1-system processor system 10i
Direct memory access controller (hereinafter referred to as DMAC) 202 for controlling direct memory access (hereinafter referred to as DMA) between the 2i and the input / output device 301.
Is provided.

0-system and 1-system processor systems 10
One of i is the active system and the other is the standby system,
In response to an instruction from the active control device 11i, the bus switch 201 of the input / output control device 200 is switched and connected to the standby system bus 13j so as to connect between the storage device 12j of the standby processor system 10j and the input / output device 301. At D
Data transfer is performed under the control of the MAC 202.

Therefore, the DMAC 202 of the input / output control device 200 takes the main role of data transfer only by instructing the processor system 10j of the active system to the processor system 10j of the standby system and setting the input / output control device 200. Therefore, even when inter-processor communication is disabled, high-speed data transfer is possible between the standby storage device 12j and the input / output device 301.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 is a diagram for explaining an embodiment of an interprocessor communication control device. The figure shows a processor system 10i, 11i and 12i are the control device and the storage device described in the principle diagram, and 150 is an inter-processor communication control device (shown as ISC in the figure).

The inter-processor communication control device 150 includes a talker controller (a controller is shown as CNT in the figure) 150A for controlling the transmitting side, a listener controller 150B for controlling the receiving side, and a buffer memory for temporarily storing received data. It is equipped with 150C.

FIG. 3 shows a sequence diagram of inter-processor communication. The figure shows an example in which data is transferred from the 0-system processor system 100 to the 1-system processor system 101. The control device (shown as CPU in the figure) of the 1-processor system 101 on the reception side sets the DMAC 202 and activates the reception order in the listener controller 150B so that a data transfer request may be issued at any time. .

The 0-system control device 11 for which a transmission request has occurred
0 is setting of DMAC202 and talker controller 1
The transmission order to 50A is activated. Transmission request is generated from 0-system ISC150 to 1-system ISC
Notify 151.

From system 0 storage device 120 to system 1 ISC1
51 to the buffer memory 150C, the input / output controller 20
Data transfer is performed under the control of the DMAC 202 of 0. When the data transfer to the buffer memory 150C is completed, the data is transferred from the buffer memory 150C to the storage device (indicated by MM in the figure) 121.

When the data transfer is completed, an interruption notification is sent to the 0-system and 1-system control devices 110 and 111 to notify the completion of the data transfer. In this operation, the control device 111 on the receiving side analyzes the transmission request code in the received data and processes it. For example, in the case of a small amount of data, the data is stored in the storage device 121 according to its address / data length.
When a large amount of data is transferred to, the address / data length of the data to be transferred next is indicated.
A setting is made in accordance with the data to 02, and the data is transferred.

Such a 0-system and 1-system controller 1
Under the control of the DMAC 202 between the 10 and 111, a large amount of data can be transferred at high speed.
The contents of 1 are managed so that they always match.

FIG. 4 shows a data format for interprocessor communication according to the present invention. (A) shows the data format of normal inter-processor communication, and the communication request type (Message
The transfer data is written after the identifier (hereinafter referred to as MID), the transfer destination address of the data, and the transfer data amount.

(B) shows a data format of inter-processor communication at the time of starting the input / output operation of the standby processor 10j. The standby system controller 11j is started by the MID and the input / output controller 200 is It is activated by the IOC command and also instructs switching of the system bus 13i.

FIG. 5 shows an embodiment of the input / output control device of the present invention (1). Reference numeral 200 in the figure denotes an input / output control device, which includes a bus switch 201, a DMAC 202, a bus control circuit 203, a floppy disk control circuit 206A,
Hard disk control circuit 206B, LAN control circuit 20
6C and internal bus 207, and is connected to the floppy disk 301A, hard disk 301B, and maintenance console 301C.

Here, the bus control circuit 203 sets the connection destinations of the 0-system and 1-system system buses 130 and 131, and the bus switch 201 is designated by the bus control circuit 202 to specify the system buses 130 and 131 and the internal buses. 207
Make the connection. The DMAC 202 controls data transfer, and the floppy disk control circuit 206A,
Hard disk control circuit 206B, LAN control circuit 20
6C access control, storage device address read / write timing control.

In such a configuration, for example, when the 0-system processor system 100 is the active system and the 1-system processor system 101 is the standby system and the software is upgraded, the 0-system processor system 1 of the active system is used.
00, the bus switch 201 of the input / output control device 200 is switched to the standby system bus 131 to transfer data between the standby storage device 121 and the hard disk 301B under the control of the DMAC 202. To do. By this processing, it becomes possible to transfer data to and from the input / output device independently of the active control device 110.
There is no adverse effect on the processing capability of the active control device 110.

6 and 7 show embodiments (1) and (2) of the bus control circuit according to the present invention. (A) is the bus control circuit 2
03 shows a basic configuration of AND circuit A1-A4, OR circuits O1 and O2, and a bus command register (BCMDR in the figure).
(Denoted as G) 203A.

Here, the bus command register 203A
Is a register for setting the bus connection mode, which is set by the control device 11i connected to the system bus 13i.

The bus switch 2 is activated by the output of the bus command register 203A and the ACT signal (ACT0 / 1).
An enable signal for controlling 01 is generated, and connection is made to any bus according to the instruction of the enable signal.

For example, the 0-system is the active system and the 1-system is the standby system, and the 0-system control unit 110 is the bus command register 20.
When "1" is set in 3A, ACT1 = "0", so the output of the AND circuit A4 becomes "1", and the OR circuit O
“1” is output as BUS EN1 through 2 and 1
It is connected to the system bus 131. Therefore, the 1-system processor system 101 and the input / output device are connected, for example, the command from the maintenance console 301C is analyzed, and the hard disk 3 is connected to the maintenance console 301C.
Controls input and output of data to and from 01B. And
When the data transfer is completed, the fact that the data transfer is completed is notified to the active system control device 110, and "0" is set in the bus command register 203A to connect the input / output control device 200 to the system bus 130 of the 0 system. And complete the process.

In (B), even if the inter-processor communication cannot be performed due to the failure of the standby system control device 111, the DMAC
It enables data transfer by 202, and AN
The D circuits A2 and A4 are composed of a 3-input AND circuit, and
When performing data transfer by DMA to one input,
The DMAACK signal is connected.

Here, the 0 system processor system 100 is the active system, ACT0 is "1", ACT1 is "0", bus command register 203A is "0", and DMAACK signal is "0" (control device 110 is operating). If, AND
The circuit A1 becomes "1", the BUS EN0 becomes "1", and the input / output control device 200 is connected to the 0-system bus 130.

Next, when outputting the contents of the spare storage device 121 to the hard disk 301B, the active control device 110 sets "1" in the bus command register 203A. In order to write data to the hard disk 301B, a write area, a write sector, etc. are set in the hard disk controller 206B, and the DMAC2
For 02, after setting the transfer source memory area of the spare system, the number of transfer bytes, etc., the command is activated to the hard disk 301B. When the hard disk 301B is activated, the hard disk controller 206B sends a data transfer request to the DMAC 202, and DM
The DMA transfer is started when the AC 202 returns the response signal DMAACK.

Here, when the bus command register 203A is set to "1", the DMAACK is also "1", the AND circuit A4 becomes "1", the BUS EN1 becomes "1", and the input / output control device is set. Reference numeral 200 is connected to the 1-system bus 131, and the storage device 121 of the 1-processor system 101 is accessed under the control of the DMAC.
Data is DMA-transferred to the hard disk 301B.

When the data transfer is completed, a completion interrupt
It goes up to the active control device 110 and completes the data transfer operation. As described above, during the DMA transfer, it is connected to the system bus 131 of the standby system, but the completion interrupt is always connected to the active system control unit 110. Also,
When the bus command register 203A is set to "0" after the transfer is completed, when the DMAACK is "1", the AND circuit A2 becomes "1" and the BUS EN0 becomes "1". It is connected to the system bus 130 and transfers data with the active storage device 120.

FIG. 7C shows a configuration in which the control of the bus control circuit 203 is performed by the channel control device 203B instead of by the bus command register 203A, and a preset DMA channel (hereinafter, the channel is referred to as CH).
The determination is made based on the response signal indicating the operation of.
In the configuration shown in the figure, the DMAC 202 is capable of setting 4CH, CH0 to CH2 of the channel control device 203B are connected to the input / output device of its own system, and CH3 is assigned to the processor system 101 of the other system.

Here, when data is transferred between the 1-system storage device 121 and the input / output device, the 0-system control device 1 is used.
11 enables CH3 of DMAC202,
By issuing a command to the I / O device,
A DMA request is issued to CH3 from the input / output device,
When the response signal DMAACK becomes "1" from C202, the AND circuit A4 becomes "1", and BUS EN1
Becomes "1", the input / output control device 200 is connected to the 1-system bus 131 to transfer data.

FIG. 7D shows that the control of the bus control circuit 203 is based on the address signal from the DMAC 202.
When the other system address is detected by the decoder 203C, the output of the decoder 203C is "1", so that the AND circuit A4 becomes "1" and the BUS EN
Since 1 becomes "1", the input / output control device 200 is connected to the 1-system bus 131 to transfer data.
Therefore, the data transfer from the designated storage device 12i can be controlled by the address set in the DMAC 202.

FIG. 8 shows an embodiment (2) of the input / output control device of the present invention, and the embodiment (1) shown in FIG.
In addition to the above configuration, a timer 204 is further provided. The timer 204 has an abnormality during data transfer between the standby control device 11j and the input / output device, and cannot normally end the data transfer operation.
i is for preventing the I / O device from being uncontrollable, and is used to set the I / O device from the active system and forcibly connect the I / O device to the active system control device 11i when a time-out occurs. It is a thing.

FIG. 9 shows an embodiment (3) of the input / output control device of the present invention, and an AND circuit 203 for inputting a reset signal for resetting the bus control circuit 203.
a and 203b are provided.

This is because an abnormality occurs during data transfer with another system and the I / O controller 200 causes the other system bus 13 to operate.
To keep it connected to 1.
The timer 204 in the input / output control device 200 described in FIG.
Instead of the control by the time-out, a signal line for resetting the bus control circuit 203 is provided from each of the control devices 110 and 111, and the active control device 11i
By sending a reset signal, the AND circuit 203
The outputs of a and 203b are set to "1", and the bus control circuit 203
Is reset to forcibly connect the input / output control device 200 to the active control device 11i.

[0043]

According to the present invention, in an information processing system having a dual processor system and a single input / output device, an input / output device such as a hard disk for upgrading software, collecting log information for failure analysis, etc. When a large amount of data is input / output between the storage device and the storage device, the DMAC provided in the input / output control device controls the transfer of the large amount of data at a high speed between the storage device and the input / output device. It becomes possible to control the duplex system efficiently.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of an interprocessor communication control device.

FIG. 3 is a sequence diagram of inter-processor communication

FIG. 4 Data format for inter-processor communication

FIG. 5 is an embodiment (1) of the input / output control device of the present invention.

FIG. 6 is an embodiment (1) of the bus control circuit of the present invention.

FIG. 7 is an embodiment (2) of the bus control circuit of the present invention.

FIG. 8 is a second embodiment of the input / output control device of the present invention.

FIG. 9 is an embodiment (3) of the input / output control device of the present invention.

FIG. 10 is a block diagram illustrating a duplex control system of a conventional example.

[Explanation of symbols]

 100 0 system processor system 101 1 system processor system 110, 111 Control device 120, 121 Storage device 130, 131 System bus 140 Inter processor communication bus 150 Inter processor communication control device 150A Talker control circuit 150B Listener control circuit 150C Buffer memory 200 Input / output Control device 201 Bus switch 202 DMAC 203 Bus control circuit 203A Bus command register 203B Channel control device 203C Decoder 204 Timer 206 I / O control circuit 206A Floppy disk control circuit 206B Hard disk control circuit 206C LAN control circuit 207 Internal bus 301 I / O device 301A Floppy Disk 301B Hard disk 301C Maintenance console A1 to A4, 203a, 20 b AND circuit O1, O2 OR circuit

Claims (5)

[Claims] 1. A 0-system processor system including a control device and a storage device, a 1-system processor system including a control device and a storage device, and a predetermined system bus connected to the 0-system and 1-system system buses. In a dual control system comprising an input / output control device for connecting to a predetermined input / output device via a bus switch for selectively connecting the input / output control device to the input / output control device, A direct memory access controller for controlling direct memory access is provided between the storage device and the input / output device, and one of the 0-system processor system and the 1-system processor system is used as the active system and the other is operated as the standby system. In accordance with an instruction from the control device, the bus switch of the input / output control device is switched to the standby system bus. A redundant control system characterized in that data is transferred between a storage device and an input / output device of a standby processor system under the control of a direct memory access controller. 2. The redundant control system according to claim 1, wherein the input / output control device is provided with a channel control device for connecting a plurality of channels, and a predetermined number of channels among the plurality of channels of the channel control device are Assigned to the secondary processor system connection, the bus switch of the input / output control device is switched and connected to the standby system bus in response to the channel assignment signal and the response signal to the data transfer request signal, and the storage device of the standby processor system is connected. 2. The duplicated control system according to claim 1, wherein data transfer is performed with the output device under the control of the direct memory access controller. 3. The duplex control system according to claim 1, wherein the input / output control device is provided with a decoder for decoding a data transfer destination address, and the decoder of the input / output control device sets a data transfer destination to another system processor system. 1 is recognized, the bus switch of the input / output control device is switched and connected to the system bus of the standby system, and data is transferred between the storage device and the input / output device of the processor system of the standby system. The redundant control system according to the item. 4. The redundant control system according to claim 1, 2, or 3, wherein the channel control device is provided with a timer for measuring a predetermined time, and data is exchanged between the input / output device and a memory of the standby processor system. When the transfer is started, the timer is started, and if the data transfer is not completed within the predetermined time set by the timer, the data transfer is forcibly terminated and the bus switch of the input / output control device is set to the working system. The redundant control system according to any one of items 1, 2, and 3, characterized in that it is connected to a bus by switching. 5. The redundant control system according to claim 1, 2, or 3, wherein the channel control device is provided with a connection control signal input circuit for forcibly switching a system bus, and the connection control signal input circuit is provided, When a connection control signal is input from the active control device, the data transfer is forcibly terminated, and the bus switch of the input / output control device is switched and connected to the active system bus.
The redundant control system according to the items 2 and 3.