JPH09297189A - Clocking circuit and pulse signal generating method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clocking circuit of high clocking accuracy, low power consumption and a small circuit scale. SOLUTION: A differential inverter ring 11 is constituted by connecting normal rotation output terminals and reverse rotation input terminals, and reverse rotation output terminals and normal rotation input terminals of the odd number of differential inverters of the same constitution, and the transition of signals is circulated by oscillation. A first signal group formed of the odd- numbered stages of normal rotation output signals and the even-numbered stages of reverse rotation output signals inputted to a first holding circuit row 12 rises or falls in order with delay time as time intervals. In the same way, a second signal group inputted to a second holding circuit row 13 also rises or fails in order at fixed time intervals. Clocking therefore becomes constant even with the difference between the rising time and falling time of the output signals of the respective differential inverters constituting the differential inverter ring 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time counting circuit for measuring time such as pulse intervals of pulse signals.

[0002]

2. Description of the Related Art A time counting circuit for measuring a time such as a pulse interval of a pulse signal is expected to be used for digital communication. In recent years, the time counting circuit can be arranged on the same chip as other digital circuits by being composed of CMOS transistors. This significantly reduces the cost of semiconductor devices.

Further, the time counting circuit can be applied to various fields such as FM wave demodulation and LSI bus signal demodulation by further improving the accuracy and stabilizing the operation. Especially,
It is expected that a time counting circuit capable of accurately and stably measuring a minute time will be used to drastically reduce the number of LSI buses.

FIG. 11 is a block diagram showing an example of a conventional time counting circuit. In FIG. 11, 51 is an inverter ring, 52 is a holding circuit array, 53 is a signal converting means, 54 is a time difference calculation circuit, 55a is a counter, and 55b is a counter output holding circuit. A pulse signal to be measured is input from the pulse signal input terminal, and data representing the pulse interval of the input pulse signal is output from the calculation result output terminal.

The time counting circuit shown in FIG. 11 is configured by connecting a plurality of delay circuits each including two inverters and one delay circuit each including three inverters (final stage in FIG. 11) in a ring shape. Inverter ring 51 is used. Since the inverter ring 51 is composed of an odd number of inverters, so-called oscillation occurs, and signal transitions sequentially move over time and circulate in the inverter ring 51. Therefore, the time can be measured by observing the change in the output voltage of each delay circuit.

The output signals of the respective delay circuits forming the inverter ring 51 are flip-flops (F) forming the holding circuit array 52 when the pulse signal to be measured rises.
F) respectively hold and output to the signal conversion means 53. The signal conversion means 53 converts the output signal of the holding circuit array 52 into data and outputs it to the time difference calculation circuit 54. Further, the counter 55a counts the number of times of signal transitions in the inverter ring 51, and outputs the count data to the time difference calculation circuit 54 via the counter output holding circuit 55b (IEICE, IEICE Technical Report, ICD93). −
77 (1993-8), "Time / numerical value conversion LSI").

[0007]

However, the conventional time counting circuit has the following problems.

In order for the inverter ring to oscillate, the number of inverters is an odd number. Further, in order to simplify the configuration of the signal processing circuit, it is preferable that the number of stages of the delay circuit is a power of two. Therefore, in the conventional time counting circuit, as shown in FIG. 11, the inverter ring is composed of delay circuits having different circuit configurations.

However, in this case, it is difficult to equalize the signal delay times in the delay circuits of each stage.
Even if the signal delay times in the delay circuits of each stage are all designed to be equal, if the power supply voltage fluctuates, the delay circuits with different circuit configurations will fluctuate in signal delay time fluctuations. The time will be different.

Here, it can be considered that one inverter is regarded as one delay circuit and time counting is performed. That is, the holding circuits are connected to the output terminals of all the inverters forming the inverter ring, and the time signals are counted using the output signals of the holding circuits.

FIG. 12 (a) is a diagram showing the time change of the output signal of each stage of the inverter which constitutes the inverter ring consisting of an odd number of identical inverters. In FIG. 12A, it is assumed that the output signal of the second-stage inverter falls after a lapse of time t ₁ after the output signal of the first-stage inverter rises. That is, the delay time in the second stage inverter is t ₁ . Similarly, the third stage to the seventh stage
The delay time in each stage inverter is t _{2 to} t
₆

Here, it is assumed that the pulse signal to be measured rises at time T ₁ . At this time, the logical levels of the output signal of the first-stage inverter and the output signal of the second-stage inverter both become the “H” level and are continuous. It is also assumed that the pulse signal to be measured rises again at time T ₂ . At this time, the logic levels of the output signal of the sixth-stage inverter and the output signal of the seventh-stage inverter both become "L" level and are continuous. From this,
It can be seen that the transition of the signal circulating in the inverter ring progressed from the first stage inverter to the sixth stage inverter between time T ₁ and time T ₂ .

The time required for a signal transition to proceed from the first stage inverter to the sixth stage inverter is obtained by the sum of the delay times of the second to sixth inverters, and is (t ₁ + t ₂
+ T ₃ + t ₄ + t ₅ ). Therefore, the time (T ₂ −T ₁ ) representing the pulse width is (t ₁ + t ₂ + t ₃ + t ₄ +
t ₅ ). Assuming that the delay time per stage of each inverter is 1 ns, t ₁ = t ₂
= T ₃ = t ₄ = t ₅ = 1 ns, the time (T ₂ −
T ₁ ) = 5 ns.

Here, at the time T by the inverter ring,
Recognized width of the time as _one is equal to the delay time t ₁ of the second stage inverter. Further, the width of time recognized as time T ₂ is equal to the delay time t ₆ of the seventh stage inverter. Therefore, when the delay time of each inverter is equal, the pulse width can be measured with the delay time as a time step.

However, in practice, it is not always easy to make the delay times of the respective inverters equal. One of the reasons why it is not easy is that the rise time and fall time of the output signal of the inverter are not always equal.

When the inverter is a CMOS inverter, the threshold voltage setting of the PMOS transistor and NM
The process is different from the setting of the threshold voltage of the OS transistor. The rise time of the output voltage of the inverter is mainly determined by the threshold voltage of the PMOS transistor, and the fall time of the output voltage of the inverter is mainly determined by the threshold voltage of the NMOS transistor. Therefore, the rise time and the fall time of the output voltage of the inverter are different from each other due to the manufacturing process, which is a normal phenomenon.

FIG. 12B is a diagram for explaining that when the rising time and the falling time of the output signal of the inverter are different, the delay time in each stage of the inverter is different. In FIG. 12B, the horizontal axis is time,
The vertical axis represents the voltage, the voltage V _DD represents the power supply voltage, and the voltage V
_T represents the threshold voltage of the holding circuit connected to each inverter. The solid line graph shows the change in the output signal of each inverter forming the inverter ring, and the numbers shown at the rising and falling points of the graph show the number of inverter stages. The holding circuit holds the logic level "1" when the input voltage is higher than the threshold voltage V _T , and holds the logic level "0" when the input voltage is lower than the threshold voltage V _T.

As shown in FIG. 12 (b), when the fall time is longer than the rise time of the output signal of the inverter, the delay times t ₁ , t ₃ and t ₅ are longer than 1 ns and t ₂ , T ₄ and t ₆ are shorter than 1 ns.

For example, t ₁ = t ₃ = t ₅ = 1.5 ns,
Assuming that t ₂ = t ₄ = t ₆ = 0.5 ns, the width of time recognized as time T ₁ is 1.5 ns, and the width of time recognized as time T ₂ is 0.5 ns. I will end up. This means that the accuracy of measuring time is not constant.

Even if an inverter ring having the same rise time and fall time can be manufactured,
In practice, the threshold voltage of the holding circuit fluctuates due to power supply voltage fluctuations and temperature changes, so the delay time of the inverters in each stage is not constant. In order to avoid this problem, a means for controlling the inverter ring by detecting a power supply voltage change or a temperature change is required in the time counting circuit, but the circuit scale becomes large and power consumption also increases.

In view of the above problems, it is an object of the present invention to provide a time counting circuit which has high time measurement accuracy, low power consumption, and a small circuit scale.

[0022]

In order to solve the above-mentioned problems, a solution means provided by the invention of claim 1 is a time provided with a delay circuit ring composed of a plurality of delay circuits in which signal transitions are circulated by oscillation. As the counting circuit, the delay circuit ring can output a signal group consisting of a plurality of signals that sequentially rises or falls at fixed time intervals, and the position of the transition of the signal at each time in the delay circuit ring can be output from the signal group. This is for detecting, and thereby highly accurate time data can be obtained even if the rising time and the falling time of the output signal of the circuit forming the delay circuit ring are different.

According to a second aspect of the present invention, there is provided a solving means which embodies the first aspect of the present invention. As a time counting circuit, an odd number of differential inverters are provided, each normal output terminal and the next stage. Is connected to the inverting input terminal of the differential inverter of and each inverting output terminal is connected to the non-inverting input terminal of the differential inverter of the next stage, and is connected in a ring shape. A differential inverter ring in which transitions circulate, a first signal group including a normal output signal of an odd-numbered differential inverter and an inverted output signal of an even-numbered differential inverter in the differential inverter ring, and the differential At least one of the second signal group consisting of the inverted output signal of the odd-numbered differential inverter and the normal output signal of the even-numbered differential inverter in the inverter ring is input, and the first and second Based on at least one of the second signal group, in which and a counting means for determining the position of the transition of one time of the signal in the differential inverter ring.

According to the invention of claim 2, since the differential inverter ring is oscillating, when the normal output signal of the differential inverter at a certain stage rises and the inverted output signal falls,
After the delay time in the differential inverter has passed, the normal output signal of the next stage differential inverter falls and the inverted output signal rises. Since the first signal group consists of the normal output signal of the odd-numbered differential inverter and the inverted output signal of the even-numbered differential inverter, each signal of the first signal group rises or falls sequentially with time. To go. Also, the second
Since the signal group of consists of the inverted output signal of the differential inverter in the odd stages and the normal output signal of the differential inverter in the even stages,
Each signal of the second signal group rises or falls sequentially with time. Here, if each differential inverter has the same configuration and the delay times are equal,
Each signal of the first signal group will rise or fall in order at a constant time interval, and each signal of the second signal group will also rise or fall in order at a constant time interval. Therefore, by detecting the position of the transition of the signal at one time in the differential inverter ring from at least one of the first and second signal groups by the counting means, the rising time and the falling time of the output signal of the differential inverter are detected. It is possible to obtain highly accurate time data even if the time is different.

In the invention of claim 3, the counting means in claim 2 receives the first and second signal groups as input, and raises each signal in order of the first and second signal groups. It is assumed that a signal group is selected and the position of signal transition at one time in the differential inverter ring is obtained based on the selected signal group.

According to the invention of claim 3, the counting means can obtain a signal group which sequentially rises at a constant time interval by selecting a signal group in which each signal sequentially rises from the first and second signal groups. Therefore, highly accurate time data can always be obtained even if the rise time and fall time of the output signal of the differential inverter are different.

In the invention of claim 4, the invention according to claim 2
The counting means in receives the first and second signal groups as input, selects a signal group in which each signal sequentially falls from the first and second signal groups, and selects the signal group based on the selected signal group. It is assumed that the position of signal transition at one time in the differential inverter ring is obtained.

According to the invention of claim 4, the counting means obtains a signal group which sequentially falls at a constant time interval by selecting a signal group in which each signal sequentially falls from the first and second signal groups. Therefore, it is possible to always obtain highly accurate time data even if the rising time and the falling time of the output signal of the differential inverter are different.

Further, in the invention of claim 5, said claim 2
The counting means in the time counting circuit comprises a plurality of holding circuits respectively connected to the normal output terminals of the odd-numbered differential inverters and the inverting output terminals of the even-numbered differential inverters in the differential inverter ring, A first holding circuit string that holds the output signal of the differential inverter to which each holding circuit is connected at the timing of the edge of the pulse signal to be measured, and outputs the held plurality of signals as a first signal string; In the differential inverter ring, a plurality of holding circuits are respectively connected to the inverting output terminals of the odd-numbered differential inverters and the non-inverted output terminals of the even-numbered differential inverters. At a timing, a second protection circuit that holds the output signal of the differential inverter to which each holding circuit is connected and outputs the plurality of held signals as a second signal string. The circuit sequence, the first signal sequence output from the first holding circuit sequence, and the second signal sequence output from the second holding circuit sequence are set to the position of signal transition in the differential inverter ring. And a signal converting means for converting and outputting to the numerical data representing the time counting circuit, based on the numerical data output from the signal converting means, between the edges of the pulse signal of the measurement object. The time shall be calculated.

According to the invention of claim 5, the normal output signal of the odd-numbered differential inverters and the inverted output signal of the even-numbered differential inverters, that is, the first input to the first holding circuit array, are input.
The signal group of 1 rises or falls sequentially at a constant time interval. Similarly, the inverted output signals of the odd-numbered differential inverters and the non-inverted output signals of the even-numbered differential inverters, that is, the second signal group, which are input to the second holding circuit array, are also sequentially arranged at regular time intervals. It rises or falls. The position of the signal transition in the differential inverter ring at the timing of the edge of the pulse signal of the measurement target is the first and second holding circuits held by the first and second holding circuit rows at the timing of the edge of the pulse signal of the measurement target. It is calculated based on the signal sequence of. For this reason,
Even if the rising time and the falling time of the output signal of the differential inverter are different, the time step of measuring the timing of the edge of the pulse signal to be measured is always constant. The first and second signal trains are converted by the signal converting means into numerical data representing the transition position of the signal in the differential inverter ring, and the time between the edges of the pulse signal to be measured is based on this numerical data. Since the calculation is performed, highly accurate time measurement is realized.

Here, in the invention of claim 6, the signal converting means according to claim 5 includes the first signal train and the second signal train.
It is assumed that the position where the signal changes from one logic level to another logic level in the signal train is detected as the position of the signal transition in the differential inverter ring, and the numerical data representing the detected position is obtained and output.

Further, in the invention of claim 7, said claim 5
The signal converting means in receives the first signal sequence output from the first holding circuit sequence as an input, and represents the point at which the signal in the first signal sequence changes from one logic level to another logic level. A first pre-encoder for generating and outputting 1 data and a second signal train output from the second holding circuit train are input, and a signal in the second signal train is set from a logical level of 1 A second pre-encoder that generates and outputs second data that represents a point at which the logic level changes to another logic level, first data output from the first pre-encoder, and output from the second pre-encoder. Second
And an encoder which receives the data of (1) as input and converts the first data and the second data into numerical data representing the transition position of the signal in the differential inverter ring and outputs the numerical data.

Further, according to the invention of claim 8, each holding circuit constituting the first and second holding circuit rows in claim 5 holds the output signal of each differential inverter as an analog signal. It is assumed to be a circuit.

Further, the solution means taken by the invention of claim 9 embodies the invention of claim 1, and is constituted by connecting an odd number of inverters in a ring shape as a time counting circuit, An inverter ring in which signal transitions circulate due to oscillation, and a first signal group including output signals of even-numbered inverters in the inverter ring,
And at least one of the second signal groups consisting of the output signals of the odd-numbered stages of inverters in the inverter ring is input, and the transition position of the signal at one time in the inverter ring is obtained based on the input signal group. And counting means.

According to the ninth aspect of the invention, since the inverter ring is oscillating, when the input signal of a certain inverter rises, the output signal falls after a delay time in the inverter. Since the first signal group is composed of the output signals of the even-numbered stages of inverters, each signal of the first signal group rises or falls sequentially with time. Further, since the second signal group is composed of the output signals of the odd-numbered stages of inverters, each signal of the second signal group rises or falls sequentially with time. Here, assuming that the respective inverters have the same configuration and have the same delay time, the respective signals of the first signal group will rise or fall in order at fixed time intervals, and the respective signals of the second signal group. Will also rise or fall in order at regular time intervals. Therefore, by detecting the position of the signal transition at the one time in the inverter ring from at least one of the first and second signal groups, the accuracy of the output signal of the inverter can be improved even if the rising time and the falling time are different. High time data can be obtained.

According to a tenth aspect of the invention, the counting means in the time counting circuit of the ninth aspect receives the first and second signal groups as an input, and selects each of the first and second signal groups. It is assumed that a signal group in which the signals sequentially rise is selected, and the position of signal transition at one time in the inverter ring is obtained based on the selected signal group.

According to the invention of claim 10, the counting means can obtain a signal group which sequentially rises at a constant time interval by selecting a signal group in which each signal sequentially rises from the first and second signal groups. Therefore, even if the rising time and the falling time of the output signal of the inverter are different, it is possible to always obtain highly accurate time data.

Further, in the invention of claim 11, the counting means in the time counting circuit of claim 9 receives the first and second signal groups as input, and selects each of the first and second signal groups. It is assumed that a signal group in which the signals sequentially fall is selected, and the position of signal transition at one time in the inverter ring is obtained based on the selected signal group.

According to the eleventh aspect of the invention, the counting means obtains a signal group that sequentially falls at a constant time interval by selecting a signal group in which each signal sequentially falls from the first and second signal groups. Therefore, it is possible to always obtain highly accurate time data even when the rise time and the fall time of the output signal of the inverter are different.

According to a twelfth aspect of the invention, the counting means in the time counting circuit of the ninth aspect comprises a plurality of holding circuits respectively connected to the output terminals of the even-numbered stage inverters in the inverter ring, In the inverter ring, a first holding circuit row that holds the output signal of the inverter to which each holding circuit is connected at the timing of the edge of the pulse signal and outputs the plurality of held signals as a first signal row; A plurality of holding circuits each connected to the output terminals of the odd-numbered inverters, each holding circuit holds the output signal of the connected inverter at the timing of the edge of the pulse signal to be measured, A second holding circuit string that outputs a signal as a second signal string, and a first signal string and a first holding circuit string that are output from the first holding circuit string. And a signal converting means for converting the second signal string output from the holding circuit string into numerical data representing the transition position of the signal in the inverter ring and outputting the numerical data. The time between edges of the pulse signal to be measured is calculated based on the numerical data output from the signal conversion means.

According to the twelfth aspect of the invention, the output signals of the even-numbered stages of inverters, that is, the first signal group, which are input to the first holding circuit train, sequentially rise or fall at fixed time intervals. Similarly, the output signal of the odd-numbered stage inverter input to the second holding circuit array, that is, the second output signal
The signal group of 1 also rises or falls sequentially at regular time intervals. The position of the signal transition in the inverter ring at the timing of the edge of the pulse signal to be measured is the first and second signals held by the first and second holding circuit rows at the timing of the edge of the pulse signal to be measured. Calculated based on the column. Therefore, even if the rising time and the falling time of the output signal of the inverter are different, the time step for measuring the edge timing of the pulse signal to be measured is always constant. The first and second signal trains are converted by the signal converting means into numerical data representing the transition position of the signal in the inverter ring, and the time between the edges of the pulse signal to be measured is calculated based on this numerical data. Highly accurate time measurement is realized.

According to a thirteenth aspect of the present invention, the signal converting means according to the thirteenth aspect is characterized in that, in the first signal train and the second signal train, the signal changes from one logic level to another logic level. It shall be detected as the position of the signal transition in the inverter ring, and the numerical data representing the detected position shall be obtained and output.

Here, the means for solving the problems of the fourteenth aspect of the present invention is, as a pulse signal generating method for generating a plurality of pulse signals, a plurality of differential inverters each having a non-inverted output terminal and a differential in the next stage. A differential inverter configured to connect an inverting input terminal of an inverter and each inverting output terminal and a non-inverting input terminal of a differential inverter at the next stage to connect in series, and propagate a signal transition. By using the columns, the normal output signal and the inverted output signal of the differential inverters forming the differential inverter column are alternately taken out in the order of the differential inverters, and the taken-out signals are made into a plurality of pulse signals. .

According to the fourteenth aspect of the present invention, a plurality of pulse signals that rise or fall sequentially are obtained, and when the differential inverters have the same configuration and the delay times are equal,
The time intervals of the rising edges or the falling edges of the plurality of pulse signals are constant.

The means for solving the problems of the fifteenth aspect of the present invention is a pulse signal generating method for generating a plurality of pulse signals, which is constituted by connecting an odd number of inverters in a ring shape, and the signal transition is circulated. The output signal of each of the inverters forming the inverter ring is taken out by every other inverter ring using the inverter ring, and the taken out signals are made into a plurality of pulse signals.

According to the fifteenth aspect of the present invention, when a plurality of pulse signals that rise or fall in order are obtained, and the inverters have the same configuration and the delay times are equal to each other, the time of the rising edge or the falling edge of the pulse signals is increased. The intervals are constant.

Further, the means for solving the problems according to the sixteenth aspect of the present invention is that, as a pulse signal generating method for generating a plurality of pulse signals, an odd number of differential inverters are provided, each normal output terminal and the differential circuit of the next stage. A differential circuit in which signal transitions are circulated by connecting the inverting input terminal of the inverter and each inverting output terminal and the non-inverting input terminal of the differential inverter of the next stage and connecting them in a ring shape. Using an inverter ring, the normal output signal and the inverted output signal of each differential inverter forming the differential inverter ring are alternately taken out in the order of the differential inverter, and the taken signals are made into a plurality of pulse signals. Is.

According to the sixteenth aspect of the present invention, a plurality of pulse signals which rise or fall sequentially are obtained, and when the differential inverters have the same configuration and the delay times are equal to each other,
The time intervals of the rising edges or the falling edges of the plurality of pulse signals are constant.

According to a seventeenth aspect of the present invention, in the pulse signal generating method of the sixteenth aspect, the normal output signal of the odd-numbered differential inverter and the inverted output of the even-numbered differential inverter in the differential inverter ring. At least one of a first signal group of signals and a second signal group of inverted output signals of odd-numbered differential inverters and normal output signals of even-numbered differential inverters in the differential inverter ring. The extracted signal group is used as a plurality of pulse signals.

Further, the solution means taken by the invention of claim 18 is configured by connecting inverters in series, and a pulse signal generation for generating a plurality of pulse signals by using an inverter train through which signal transition propagates. As a method, there is a difference between the rise time and the fall time of the output signals of the inverters forming the inverter train, the degree of substantially adversely affecting the design specifications regarding the edge intervals between the plurality of pulse signals. In this case, the output signals of the inverters forming the inverter train are taken out every other inverter, and the taken out signals are used as a plurality of pulse signals.

According to the eighteenth aspect of the present invention, a plurality of pulse signals that rise or fall in sequence are obtained, and when the inverters have the same configuration and the delay times are equal to each other, the rising time and the falling time of the output signal of the inverter are Even if there is a difference that substantially adversely affects the design specifications regarding the edge intervals between the plurality of pulse signals, the time interval between the rising edges or the falling edges of the plurality of pulse signals becomes constant. .

[0052]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 1 is a configuration diagram of a main part of a time counting circuit according to a first embodiment of the present invention. In FIG. 1, 11 is a differential inverter ring as a delay circuit ring, 12 is a first holding circuit row, 13 is a second holding circuit row, 14a is a counter, 14b is a counter output holding circuit, and 15 is a phase comparator. , 16 is a loop filter, 17 is an oscillator control circuit, 18a is a reference pulse signal input terminal, 1
8b is a pulse signal input terminal to be measured, 18c is circulation number data output terminal, P ₁ to P ₃₃ is the signal output terminal of the first holding circuit array 12, Q ₁ to Q ₃₃ are the second row of holding circuits 13 This is a signal output terminal.

The differential inverter ring 11 is formed by connecting 33 (= 2 ⁵ +1) differential inverters having the same structure in a ring shape. Of the output terminals of each stage differential inverter, the non-inversion output terminal is connected to the inverting input terminal of the next stage differential inverter, and the inverting output terminal is connected to the non-inversion input terminal of the next stage differential inverter. There is. Further, the normal output terminal of the output terminal of the final stage (thirty-third stage) differential inverter is connected to the inverting input terminal of the first stage differential inverter, and the inverting output terminal is connected to the first stage differential inverter. It is connected to the forward input terminal. Therefore, the differential inverter ring 11 oscillates and the signal transition circulates.

The first holding circuit array 12 is composed of 33 holding circuits respectively connected to the normal output terminals of the odd-numbered differential inverters and the inverting output terminals of the even-numbered differential inverters. The second holding circuit array 13 is composed of 33 holding circuits connected to the inverting output terminals of the odd-numbered differential inverters and the normal output terminals of the even-numbered differential inverters, respectively. When the pulse signal to be measured input from the pulse signal input terminal 18b rises, each holding circuit holds the signal at the output terminal of the connected differential inverter, and the signal output terminals P _{1 to} P ₃₃ and Q ₁ to respectively output from Q _33.

The counter 14a is connected to the non-inverted output terminal of the 33rd stage differential inverter, and counts the number of rounds of transition of the signal circulating in the differential inverter ring 11.
The counter output holding circuit 14b has a pulse signal input terminal 1
When the pulse signal to be measured input from 8b rises, the count data of the counter 14a is held and output from the number-of-laps data output terminal 18c.

Further, the phase comparator 15 and the loop filter 1
6 and the oscillator control circuit 17 control the delay time of each differential inverter. The phase comparator 15 detects the phase difference between the reference pulse signal input from the reference pulse signal input terminal 18a and the normal output signal of the 33rd stage differential inverter. The loop filter 16 averages the output signal of the phase comparator 15 output in the form of a pulse waveform, and outputs the obtained voltage. The oscillator control circuit 17 adjusts the delay time of each differential inverter based on the voltage output from the loop filter 16. The delay time of each differential inverter is continuously adjusted until the phases of the reference pulse signal and the normal output signal of the 33rd stage differential inverter become equal.

Therefore, the frequency of the reference pulse signal is equal to the frequency of the output signal of the 33rd stage differential inverter. By using the output pulse signal of the crystal oscillator having a constant frequency as the reference pulse signal, the differential inverter ring 11 can be oscillated at a constant frequency, and the delay time of each differential inverter can be accurately controlled. it can.

FIG. 2 is a graph showing changes in the normal output signal of each differential inverter that constitutes the differential inverter ring 11. In FIG. 2, the horizontal axis represents time, the vertical axis represents voltage, V _DD is the power supply voltage, and V _T is the threshold value of each holding circuit forming the first holding circuit row 12 and the second holding circuit row 13. The voltage and GND are ground potentials. Also, the numbers shown at the rising or falling points of the solid line graph in the figure indicate the number of stages of the differential inverter that outputs the normal output signal.

As shown in FIG. 2, when the non-inverted output signal of the first stage differential inverter rises, the non-inverted output signal of the second stage differential inverter subsequently falls and the second stage differential inverter When the normal output signal of the inverter falls, the third
The transition of the signal progresses such that the non-inverted output signal of the stage differential inverter rises.

However, the rising time and the falling time of the output signal of each differential inverter are not always equal. This is due to the same manufacturing process as that described for the CMOS inverter in the problem section,
There is a cause derived from the circuit configuration of the differential inverter. The latter cause will be described later.

Since the rising time and the falling time of the output signal are different, the delay times t _{1 to} t ₆ of the respective stages are not equal. In addition, the delay times t _{1 to} t ₆ are changed according to the change of the threshold voltage V _T of the holding circuit.

FIG. 3 is a graph showing changes in the inverted output signals of the differential inverters in even stages in addition to the changes in the signals shown in FIG. In FIG. 3, the change of the inverted output signal is indicated by a dashed line, and the number with a bar above the rising edge of the dashed line graph indicates the number of stages of the differential inverter that outputs the inverted output signal. . As shown in FIG. 3, both the normal output signal of the odd-numbered differential inverter and the inverted output signal of the even-numbered differential inverter are rising signals.

Therefore, if the normal output signal of the odd-numbered differential inverter and the inverted output signal of the even-numbered differential inverter are used for time counting, the delay times t _{1 to} t ₆ of the respective stages become equal. Further, the delay times t _{1 to} t ₆ do not change even if the threshold voltage V _T of the holding circuit changes. The time counting circuit according to the present embodiment utilizes this point to improve the accuracy of time counting.

Here, the reason why the rising time and the falling time of the output signal of the differential inverter are not equal due to the circuit configuration of the differential inverter will be described.

FIG. 4 is a circuit diagram showing a typical circuit configuration of the differential inverter. The differential inverter shown in FIG.
It is constituted by three PMOS transistors MP ₁ to MP ₃ and four NMOS transistors MN ₁ to MN _4. 41a is a normal input terminal, 41b is an inverting input terminal, 42a is a normal output terminal, and 42b is an inverting output terminal. When used in the differential inverter ring 11 as shown in FIG. 1, the normal input terminal 41a is used. Is connected to the inverting output terminal 42b of the preceding differential inverter, and the inverting input terminal 4
1b is connected to the non-inverted output terminal 42a of the previous stage differential inverter, the non-inverted output terminal 42a is connected to the inverting input terminal 41b of the next stage differential inverter, and the inverting output terminal 42b is connected to the next stage differential inverter. It is connected to the normal input terminal 41a. Further, the delay time in the differential inverter is adjusted by the voltage applied to the control terminal 43, and when this differential inverter is used in the differential inverter ring 11, the voltage output from the oscillator control circuit 17 is applied to the control terminal 43. Is applied. Further, a constant potential is applied to the terminal 44.

Here, for the sake of explanation, the normal output terminal 42 is used.
It is assumed that a capacitor C ₁ is connected to a, a capacitor C ₂ is connected to the inverting output terminal 42b, and a constant voltage is applied to the control terminal 43.

Now, it is assumed that the rising signal is input to the normal input terminal 41a and the falling signal is input to the inverting input terminal 41b.

When the potential of the non-inverted input terminal 41a is "L" level, the PMOS transistor MP ₂ is in the conductive state, and the potential of the non-inverted output terminal 42a is "H" level.
Further, when the potential of the inverting input terminal 41b is at the "H" level, PMOS transistor MP ₃ is nonconductive,
The potential of the inverting output terminal 42b is "L" level.

When the potential of the non-inverted input terminal 41a becomes "H" level, the PMOS transistor MP ₂ changes to the non-conductive state. At this time, the charge accumulated in the capacitor C ₁ connected to the non-inverted output terminal 42a is stored in the NMOS transistor M
Although it flows out through N ₁ and MN ₃ , the NMOS transistors MN ₁ and MN ₃ act as a non-linear resistance, and the flowing current changes depending on the voltage of the non-inverting output terminal 42a.

The potential of the inverting input terminal 41b is "L".
When it reaches the level, the PMOS transistor MP ₃ changes to the conductive state. At this time, the current from the PMOS transistor MP ₁ which is a constant current source flows into the capacitor C ₂ connected to the inverting output terminal 42b, and the voltage of the inverting output terminal 42b rises at a substantially constant speed.

That is, the voltage at the non-inverted output terminal 42a drops due to the discharge of the capacitance due to the non-linear current, while the voltage at the inverting output terminal 42b rises due to the charge of the capacitance due to the constant current. In this way, the rise time and the fall time of the output signal are determined by different phenomena, so these times are not equal.

FIG. 5 is a graph showing the results of simulation of changes in the output signals of the differential inverters when the differential inverter ring 11 is formed by the differential inverters shown in FIG. The simulation tool used is Spectre (Ver4.3.2.20, CAD
The model of the transistor is BS1M1 by ENCE. Table 1 shows the parameters of each transistor forming the differential inverter.

[0073]

[Table 1] The power supply voltage is 5V and the temperature is 27 ° C. FIG.
, The horizontal axis represents time [ns], the vertical axis represents voltage [V], the numbers in each graph indicate the number of stages of the differential inverter, and the bar above the numbers represents the inverted output signal. Those without a bar indicate a normal output signal.

As can be seen from FIG. 5, the rising time and the falling time of each signal are largely different, but the rising times are almost equal and the falling times are also almost equal. Therefore, the delay times A, B, and C due to only the rising signal are equal, and the delay times D, E, and F due to only the falling signal are also equal.

Therefore, by alternately extracting the normal output signal and the inverted output signal of the differential inverters of each stage, it is possible to obtain a combination of pulse signals that are combined only with the rising signals and have rising timings at equal intervals. It will be possible.

A supplementary explanation will be given on the problem that the rising time and the falling time of the output signal of the inverter are not always equal.

The problem that the rising time and the falling time of the output signal of the inverter are not always equal becomes more prominent as the power supply voltage is lowered (for example, from 5V to 3V).

When the power supply voltage decreases, the number of transistors that can be superimposed between the power supply and the ground decreases. Specifically, four transistors can be superposed when the power supply voltage is 5V, but the maximum number of transistors that can be superposed is three when the power supply voltage is 3V. Since the number of transistors that can be superposed decreases as the power supply voltage decreases to 3V, the following problems occur with respect to the delay time of the inverter ring.

At least two transistors must be superposed in order to realize the function of inverting a signal in the inverter, and further another transistor must be superposed in order to adjust the signal propagation speed. However, only one of the rising speed and the falling speed of the output signal can be adjusted only by superposing one transistor, and in order to adjust both the rising speed and the falling speed of the output signal, It is necessary to superimpose two transistors. That is, in order to be able to adjust the signal propagation speed in the inverter ring, each inverter adjusts both the rising speed and the falling speed of the two transistors that realize the function of inverting the signal and the output signal. It is necessary to superimpose a total of four transistors with two transistors.

However, as described above, the power supply voltage is 3V.
Therefore, the maximum number of transistors that can be superimposed is three, so that only one transistor for adjusting the signal propagation speed can be superimposed in the inverter. This is because the two transistors that realize the function of inverting the signal are essential for the inverter. If one transistor for adjusting the signal propagation speed is used for adjusting the rising speed of the output signal, the rising of the output signal can be stabilized by this transistor, but the falling of the output signal can be stabilized. The speed is not stable as it is determined by the two transistors that implement the function of inverting the signal. This is because one transistor that adjusts the signal propagation speed is in the constant current region, while two transistors that realize the function of inverting the signal are in the variable resistance region. As described above, when the power supply voltage becomes 3 V, only one of the rising speed and the falling speed of the output signal can be adjusted in the inverter, and the natural consequence is that the rising and falling of the output signal are different. The signal propagation times will differ greatly.

The adverse effect of this problem on the time measurement accuracy in the time counting circuit is further increased by shortening the delay time of the inverter, that is, shortening the time step in the time counting circuit.
This is because, for example, in the simulation result shown in FIG. 5, the falling timing of the output signal of the second-stage differential inverter is later than the rising timing of the output signal of the third-stage differential inverter (which is originally the It is also clear that the falling timing of the output signal of the two-stage differential inverter must be earlier than the rising timing of the output signal of the third-stage differential inverter). That is, there is a possibility that the propagation order of signal transitions may be reversed in the inverter ring because the signal propagation times greatly differ between the rising edge and the falling edge of the output signal.

Next, in the signal group consisting of a plurality of pulse signals obtained by alternately extracting the normal output signal and the inverted output signal of each differential inverter in the differential inverter ring, the time intervals between the edges are equal. The reason for becoming will be explained.

In one differential inverter forming the differential inverter ring, the inverted output signal falls when the normal output signal rises, and the normal output signal falls when the inverted output signal rises. That is, in the differential inverter ring, it can be considered that the rising and falling edges of the signal are paired and circulate as the transition of the signal.

If the oscillation frequency of the differential inverter ring is stable and each differential inverter has the same configuration, the transition of the signal circulating in the differential inverter ring, that is, the pair of rising and falling of the signal, is set. The propagation delay time per stage of the differential inverter is equal in each differential inverter. Further, since the time required for the rising of the output signal in each differential inverter is the same because each differential inverter has the same configuration, the rising time of the signal circulating through the differential inverter ring is equal to that of the output signal of the differential inverter. Propagation delay time per differential inverter stage including the time required for rising is also equal in each differential inverter. Similarly, since the time required for the output signal to fall in each differential inverter is the same, the time required for the output signal to fall in the differential inverter should be included when the signal circulating in the differential inverter ring falls. The propagation delay time per stage of the considered differential inverter is also equal in each differential inverter.

Therefore, a signal group consisting of a plurality of pulse signals having the same time interval between edges can be obtained by alternately extracting the signals in the forward and reverse directions in the differential inverter ring.

Next, the signal processing of the time counting circuit using the circuit shown in FIG. 1 will be described.

FIG. 6 is a block diagram of an example of a time counting circuit using the circuit shown in FIG. 6, 10 is the same as in FIG.
, 20 is an encoder as a signal converting means for converting the output data of the main circuit 10 into numerical data, and 21 is a time difference calculation for calculating a pulse interval based on the numerical data output from the encoder 20. Circuit. The first holding circuit row 12 and the second holding circuit row 13 shown in FIG. 1 and the encoder 20 constitute a counting means. The time counting circuit shown in FIG. 6 is characterized in that the output signals P _{1 to} P ₃₃ of the _first holding circuit row 12 and the output signals Q _{1 to} Q ₃₃ of the second holding circuit row 13 are both taken into the encoder 20. To do.

FIG. 7 is a diagram showing the time change of the output signal of each differential inverter forming the differential inverter ring 11 in the main circuit 10. In FIG. 7, the + output represents the time change of the normal output signal, and the − output represents the time change of the inverted output signal.

As shown in FIG. 7, when the normal output signal of the first-stage differential inverter rises, the inverted output signal of the second-stage differential inverter rises after the delay time in the differential inverter, and , The normal output signal of the third-stage differential inverter, the inverted output signal of the fourth-stage differential inverter, and the normal output signal of the fifth-stage differential inverter. When the normal output signal of the 33rd stage differential inverter rises, the inverted output signal of the 1st stage differential inverter rises after the delay time in the differential inverter, and then the positive output signal of the 2nd stage differential inverter. The inverted output signal, the inverted output signal of the third-stage differential inverter, and the normal output signal of the fourth-stage differential inverter rise in this order.

When the non-inverted output signal of the first stage differential inverter falls, the inverted output signal of the second stage differential inverter falls after the delay time in the differential inverter, and then the third stage. The normal output signal of the stage differential inverter, the inverted output signal of the fourth stage differential inverter, and the normal output signal of the fifth stage differential inverter fall in this order. When the non-inverted output signal of the 33rd stage differential inverter falls, the inverted output signal of the 1st stage differential inverter falls after the delay time in the differential inverter, and then the 2nd stage differential inverter. Of the normal output signal, the inverted output signal of the third-stage differential inverter, and the normal output signal of the fourth-stage differential inverter. Thus, the rising and falling edges of the signal circulate through the differential inverter ring.

The time intervals (t1, t2, t3, t4 in FIG. 7) between the edges of the output signals are equal to each other, as already described.

Here, the signal group consisting of the normal output signal of the odd-numbered differential inverter and the inverted output signal of the even-numbered differential inverter is defined as the first signal group, and the inverted output signal of the odd-numbered differential inverter is set. And a signal group consisting of the non-inverted output signals of the even-numbered differential inverters is referred to as a second signal group. As shown in FIG. 7, in time domain A, each signal of the first signal group rises in order and each signal of the second signal group falls in sequence, while in time domain B, the first signal group Of each of the above signals fall in order, and each signal of the second signal group rises in order.

Therefore, for example, by selecting the first signal group in the time domain A and selecting the second signal group in the time domain B, a signal group consisting of signals that sequentially rise at constant time intervals is obtained. be able to. By using such a signal group, highly accurate time measurement can be performed. Similarly, in the time domain A, the second signal group is selected, and in the time domain B, the first signal group is selected to obtain a signal group composed of signals that sequentially fall at a constant time interval. This also enables highly accurate time measurement.

If the measurement time is sufficiently shorter than the time regions A and B, for example, either one of the first and second signal groups may be used.

In this embodiment, as will be described later, the selection of the first and second signal groups is performed at the stage of digital signal processing. Of course, the present invention is not limited to this.

Next, the signal processing of the time counting circuit according to this embodiment will be specifically described with reference to FIG. In FIG. 8, it is assumed that the pulse signal to be measured rises at time T ₁ . At this time, the first holding circuit array 12 holds and outputs the normal output signal of the odd-numbered differential inverters and the inverted output signal of the even-numbered differential inverters, and therefore outputs the signal “111000 ... 00”. Output. On the other hand, the second
Since the holding circuit array 13 holds and outputs the inverted output signal of the odd-numbered differential inverters and the normal output signal of the even-numbered differential inverters, the signal “000111 ... 11” is output.
Is output.

Next, if the pulse signal to be measured rises at time T ₂ , the first holding circuit array 11 outputs the signal “110000 ... 00” while the second holding circuit array 11 outputs the second signal.
The holding circuit array 12 outputs the signal "001111 ... 11".

Table 2 is a table showing the relationship between the output signals of the first holding circuit row 12 and the second holding circuit row 13 and time.

[0099]

[Table 2]

In Table 2, the time step is the delay time per stage of the differential inverter, and if the delay time is 1 ns, the time step is also 1 ns. Since the first holding circuit array 12 holds and outputs the normal output signal of the odd-numbered differential inverters and the inverted output signal of the even-numbered differential inverters, the output signals are "0" and "1". Each will be continuous. Further, since the second holding circuit array 13 holds and outputs the inverted output signal of the odd-numbered differential inverters and the normal output signal of the even-numbered differential inverters, the output signals are also “0” and “0”. 1 ”will be continuous respectively.

Here, in the output signals of the first holding circuit string 12 and the second holding circuit string 13, the portions where "0" is switched to "1" or "1" is switched to "0" are the transitions of the signals. Be in position. However, since the rising time and the falling time of the signal are different as described above, in order to keep the time step constant, here, only the position where the “1” is switched to the “0” is the transition position of the signal. For example, time 4
Then, the position of the signal transition is the inverting output terminal of the fourth stage differential inverter (shown as “/ 4” in Table 2), and the time 3
In No. 5, the transition position of the signal is the non-inverted output terminal of the second stage differential inverter (shown as "2" in Table 2). As a result, two rounds of signal transition, that is, time data of 66 gradations is obtained.

The encoder 20 includes the first holding circuit array 12
And based on the output signal of the second holding circuit array 13,
It outputs 7-bit data of 66 gradations from "0000000" to "1000001".

The counter 14a counts the number of times the normal output signal of the 33rd stage differential inverter has fallen.

The time difference calculation circuit 21 uses the data (count data of the counter 14a) output from the frequency data output terminal 18c as upper bit data, the output data of the encoder 20 as lower bit data, and the 13-bit time data. Ask. Table 3 is a table showing the relationship between time data and time obtained by the time difference calculation circuit 21.

[0105]

[Table 3]

Here, the lower-order bit data is 7-bit data, but since it represents only 66 gradations, if it is simply combined with the upper-order bit data, the continuity of the time data will be lost. Therefore, the data is corrected as follows.

Assuming that the lower bit data is A and the upper bit data is B, A + 2B is first obtained, and the data B is added to this.
Is incremented by 6 digits, and the data "B, 000,000" is added. In Table 3, taking the time 2143 as an example, the lower bit data, that is, the data A is “0,011110”, and the upper bit data, that is, the data B is “1000”.
Since it is "00", A + 2B becomes "1,011110". In addition to this, the data "6" is carried up by 6 digits to obtain the data
The time data "0,100001,011110" is obtained by adding "000000,000,000". With such correction, "0,000,00000000" is obtained.
4 from "0" to "1,000001,111111"
Continuous time data of 224 (= 66 × 2 ⁶ ) gradations will be obtained.

FIG. 8 is a block diagram of another example of the time counting circuit using the circuit shown in FIG. In FIG. 8, 10 is the main circuit shown in FIG. 1, 25 is a first pre-encoder for converting the output signals P _{1 to} P ₃₃ of the first holding circuit array 12 into bit data and outputting the bit data, and 26 is a first pre-encoder. A second pre-encoder that converts the output signals Q _{1 to} Q ₃₃ of the two holding circuit arrays 13 into bit data and outputs the bit data, 27 is the first pre-encoder 2
5, an encoder for converting bit data output from the second pre-encoder 26 into numerical data and outputting the numerical data, 2
Reference numeral 8 is a time difference calculation circuit for calculating the time interval of the pulse signal based on the numerical data output from the encoder 27. The first pre-encoder 25, the second pre-encoder 26 and the encoder 27 constitute a signal converting means, and the signal converting means and the first and second holding circuit arrays 12 and 13 constitute a counting means. There is.

The first pre-encoder 25 outputs 32-bit data by performing a logical operation on the output signals of two adjacent holding circuits in the first holding circuit array 12. This logical operation is set to "1" only when the output signal of the holding circuit in the previous stage is "1" and the output signal of the holding circuit in the next stage is "0", and is set to "0" otherwise. It is a thing. For example, at time 3, Table 2
As shown in (1), up to the inverted output signal of the second stage differential inverter is "1" and after the normal output signal of the third stage differential inverter is "0", the first pre-encoder 25
Only the second bit of the output data of "1" becomes "1", and all other bits become "0".

The second pre-encoder 26 has a second
32-bit data is output by performing a logical operation similar to that of the first pre-encoder 25 on the output signals of the two adjacent holding circuits in the holding circuit array 13.

The encoder 27 takes the logical sum of the output data of the first pre-encoder 25 and the second pre-encoder 26 for each bit, converts the obtained bit data into 6-bit data of 33 gradations, and outputs it. To do.

Table 4 shows output data of the first pre-encoder 25 and the second pre-encoder 26 at each time,
3 is a table showing output data of the encoder 27.

[0113]

[Table 4]

The time difference calculation circuit 28 uses the data (count data of the counter 14a) output from the frequency data output terminal 18c as the upper bit data, the output data of the encoder 27 as the lower bit data, and the 12-bit time data. Ask. Table 5 is a table showing the relationship between time data obtained by the time difference calculation circuit 28 and time. Here, it is assumed that the counter 14a counts both the falling edge and the rising edge of the normal output signal of the 33rd stage differential inverter.

[0115]

[Table 5]

In Table 5, correction is performed to guarantee the continuity of time data.

As described above, according to the time counting circuit of this embodiment, the differential inverter ring composed of the odd number of differential inverters connected in the ring shape is used, and the positive output of each differential inverter is positive. By alternately extracting the force signal and the inverted output signal, the transition position of the signal can always be detected only by the rising edge (or only the falling edge) of the signal at each time. As a result, the time step can be made constant and the accuracy of time data is improved.

The output signal of the differential inverter ring does not necessarily have to be held at the logic level "1" or "0", but may be held as an analog voltage by the sampling circuit.

Since the differential inverter is used in this embodiment, the time interval between the edges of the obtained signal group is larger than that in the case where a non-differential inverter is used as in the second embodiment described later. That is, the effect that the time step of the time counting circuit can be reduced can be obtained.

(Second Embodiment) In the first embodiment,
By using the differential inverter ring, the position of the signal transition can always be detected only by the rising edge (or only the falling edge) of the signal.
The present embodiment realizes the same thing without using a differential inverter.

FIG. 9 is a block diagram of a time counting circuit according to the second embodiment of the present invention. In FIG. 9, 31 is an inverter ring as a delay circuit ring, 32 is a first holding circuit row, 33 is a second holding circuit row, 34 is a signal converting means, 35 is a time difference calculation circuit, 36a is a counter, 36b.
Is a counter output holding circuit. A pulse signal to be measured is input from the pulse signal input terminal, and data representing the pulse interval of the pulse signal to be measured is output from the calculation result output terminal.

The inverter ring 31 is constructed by connecting 33 delay circuits in a ring shape. Each of the delay circuits from the first stage to the 32nd stage consists of two inverters, and the delay circuit of the final stage (the 33rd stage) consists of one inverter. That is, the inverter ring 31 is composed of 65 (= 2 × 32 + 1) inverters, and since the odd number of inverters are connected in a ring shape, the inverter ring 31 oscillates and the signal transition circulates in the inverter ring 31. Here, all the inverters forming the inverter ring 31 have the same structure,
The delay time in each inverter is the same.

Each holding circuit of the first holding circuit array 32 is connected to each of the latter inverters of the two inverters forming the first to 32nd delay circuits. That is, each holding circuit is connected to the output terminals of even-numbered inverters of the inverters that form the inverter ring 31.

Each of the holding circuits of the second holding circuit array 33 includes a preceding inverter of the two inverters forming the delay circuits of the first to 32nd stages and an inverter forming the delay circuit of the 33rd stage. It is connected to each output terminal. That is, each holding circuit is connected to the output terminal of an odd-numbered inverter among the inverters forming the inverter ring 31.

When the pulse signal to be measured input from the pulse signal input terminal rises, the first holding circuit array 32
And each holding circuit of the second holding circuit array 33 holds and outputs the signal of the output terminal of the connected inverter. .

The signal converting means 34 includes the first holding circuit array 3
2 and the output signals of the second holding circuit array 33 are converted into numerical data.

The counter 36a is connected to the output terminal of the final-stage inverter, and counts the change in the signal at this output terminal as the number of turns of the signal transition in the inverter ring 31. The counter output holding circuit 36b is
When the pulse signal to be measured input from the pulse signal input terminal rises, the count data of the counter 36a is held and output.

The time difference calculation circuit 35 includes the signal conversion means 34.
The time data in which the numerical data output from the counter is the lower bit data and the count data output from the counter output holding circuit 36b is the upper bit is obtained, and the pulse interval of the pulse signal to be measured input from the pulse signal input terminal is calculated. Calculate and output from the calculation result output terminal.

Here, the movement of signals in the inverter ring 31 will be described.

First, it is assumed that the input signal of the first-stage delay circuit rises. Then, the output signal of the first-stage delay circuit (that is, the input signal of the second-stage delay circuit) rises after a delay time in the two inverters. Similarly, in the delay circuits other than the 33rd stage, when the input signal rises, the output signal rises after a delay time in the two inverters, so that the rise of the signal propagates through the delay circuits of the 1st to 32nd stages. It will be. In the 33rd stage delay circuit, when the input signal rises, the output signal (that is, the input signal of the 1st stage delay circuit) falls after a delay time in one inverter.

When the input signal of the first-stage delay circuit falls, the delay time in the two inverters elapses and then the first signal is passed.
The output signal of the stage delay circuit falls. Similarly, the 33rd
2 when the input signal falls in delay circuits other than stages
Since the output signal falls after a delay time in each inverter, the signal fall propagates through the delay circuits of the first to 32nd stages. In the delay circuit of the 33rd stage, when the input signal falls, the output signal (that is, the input signal of the delay circuit of the 1st stage) rises after a delay time in one inverter. In this way, the movement in which the rising edge and the falling edge of the signal propagate alternately is repeated.

In the delay circuits other than the 33rd stage, when the input signal falls, the output signal of the preceding inverter rises. Therefore, when the output signal of the inverter in the preceding stage of each delay circuit is focused while the falling edge of the signal is propagating, the rising edge of the signal is propagating. By utilizing this, the characteristic of the present embodiment is that the transition position of the signal is always detected by the rising edge of the signal. Moreover, since the delay time from the change of the input signal of the delay circuit of the 33rd stage to the change of the output signal of the inverter of the previous stage of the delay circuit of the first stage is the delay time in the two inverters, the time step Can always be constant.

When the inverter ring 31 is regarded as an inverter ring composed of 65 stages of inverters, the output signals (first signal group) of the even-numbered stages of the inverter ring 31 are input to the first holding circuit array 32, The output signals (second signal group) of the odd-numbered inverters of the inverter ring 31 are input to the second holding circuit array 33.

Table 6 is a table showing the relationship between the output signals of the first holding circuit row 32 and the second holding circuit row 33 and time.

[0135]

[Table 6]

In Table 6, the time step is the delay time in the two inverters, and the delay time of the inverter is 1
If it is ns, the time step becomes 2 ns. Each holding circuit of the first holding circuit row 32 is connected to the output terminal of the inverter by 2
Since they are connected alternately, "0" and "1" are consecutive in the output signal. Further, each holding circuit of the second holding circuit array 33 is also connected to every other output terminal of the inverter, so that the output signals thereof are also "0" and "1", respectively.

Here, when the output signal of the first holding circuit array 32 and the output signal of the second holding circuit array 33 are regarded as a series of signals, the time at which the signal switches from "1" to "0" You can see that it is progressing with. This point is the position where the rising edge of the signal is propagating, and assuming that this is the position of signal transition, for example, at time 4, it is the output terminal of the inverter at the subsequent stage of the delay circuit at the fourth stage (in Table 6, " 4 ”), at time 35, it is the output terminal of the inverter in the preceding stage of the delay circuit in the third stage (indicated as“ / 3 ”in Table 6).

By recognizing the position of the transition of this signal, time data of 65 gradations whose time step is twice the delay time of the inverter while the signal transition circulates twice in the inverter ring 31 is obtained. Obtainable.

The signal converting means 34 includes the first holding circuit array 3
2 and the position of the transition of the signal is detected from the output signals of the second holding circuit array 33, and from “000000” to “1.00
It outputs 7-bit numerical data representing 65 gradations up to 0000 ".

Further, the counter 36a counts the number of times the output signal of the delay circuit of the 33rd stage rises.

The time difference calculation circuit 35 uses the count data of the counter 36a as the upper bit data, and the signal conversion means 34.
The 13-bit time data is obtained by using the output data of the above as the lower bit data. Table 7 is a table showing the relationship between time data obtained by the time difference calculation circuit 35 and time.

[0142]

[Table 7]

Here, the lower bit data is 7-bit data, but since it represents only 65 gradations, the continuity of the time data is lost if it is simply combined with the upper bit data. Therefore, the data is corrected as follows.

Assuming that the lower bit data is A and the upper bit data is B, A + B is first obtained, and data "B, 000000" obtained by shifting data B by 6 bits is added to this. In Table 7, taking the time 2111 as an example, the lower bit data, that is, the data A is “0,011111”.
Therefore, the upper bit data, that is, the data B is “1000
Since it is "00", A + B becomes "0,111111". Data "6" is obtained by shifting data B by 6 bits.
The time data “0,100,000,111111” is obtained by adding “000000,000,000”. With such correction, “000000,000,000” is obtained.
4 from 0 "to" 1000000,111111 "
It is possible to obtain continuous time data of 160 (= 65 × 2 ⁶ ) gradations.

As described above, according to the time counting circuit of the present embodiment, the inverter ring composed of the odd number of inverters connected in the ring shape is used, and the output signals of the respective inverters are taken out alternately. The position of the transition of the signal at each time can always be detected by only the rising edge (or only the falling edge) of the signal. As a result, the time step can be made constant, so that the accuracy of time data is improved.

Incidentally, as described in the first embodiment,
A plurality of pulse signals in which the time intervals of the edges are equal and extremely short by alternately extracting the normal output signal and the inverted output signal of each differential inverter that constitutes the differential inverter ring in which the signal transition circulates. By taking out every other output signal of each inverter constituting the inverter ring in which the signal transition circulates as described in the second embodiment, and the time intervals of the edges are equal to each other. The method of generating a plurality of extremely short pulse signals is not used only for the time counting circuit, and can be regarded as one invention from a viewpoint different from that of the time counting circuit.

Such a pulse signal generation method is extremely important for future communication technology, signal processing technology, etc., and can be applied to various fields. A supplementary explanation will be given on this point.

Data communication, especially data transmission between LSIs, has been increasing year by year, but the current data transmission speed is not sufficient to further enhance the image processing function.
The development of technology for realizing higher speed data transmission is awaited. As one of the techniques for realizing higher-speed data transmission, there is a pulse generation circuit that can output a plurality of pulse signals that have even edge time intervals and that are extremely short.

For example, in the pulse width modulation technique, the time from the rising edge to the falling edge of the pulse is measured in order to obtain the information of the pulse width. For this measurement, the signal group generated by the pulse signal generation method is used. It can be used, and the shorter the time interval between the edges of the pulse signals of the signal group can be, the more information can be transmitted. Further, in the case of holding data transmitted at high speed, a signal group generated by the pulse signal generation method can be used as a data holding instruction signal, and the time interval between the mutual edges of the pulse signals of the signal group can be used. The shorter is possible, the faster the data transmission can be.

Further, the time intervals of the edges of each pulse signal are not sufficient if they are simply short, and it is necessary that they are short and uniform without causing variations. If there are variations in the time intervals of the edges, the pulse width modulation technique causes erroneous recognition of information, and the high speed data transmission causes erroneous retention of data. Therefore, in order to realize high-speed data transmission, a pulse signal generation method that is capable of generating a signal group composed of a plurality of pulse signals having even time intervals between edges and being extremely short is indispensable.

In order to reduce the time interval of edges to a short time of 1 ns or less, an inverter ring is used, and not all terminals between the inverters of the inverter ring are used as output terminals, but all terminals are output signal terminals. The adoption of the pulse signal generation method is considered. In such a pulse signal generation method, the time interval between edges of each pulse signal is a delay time per inverter stage, and therefore the time interval between edges can be shortened to 1 ns or less.

Therefore, as can be seen from such a background, the pulse signal generating method according to the present invention which uses the inverter ring to generate a plurality of pulse signals in which the time intervals of the edges are equal to each other and which are extremely short , Will play an important role in future communication technology and signal processing technology.

In the pulse signal generating method according to the present invention, it is not always necessary that the inverters are connected in a ring shape, and the same can be realized by using an inverter train in which the inverters are connected in series and the signal transition propagates. be able to.

[0154]

As described above, according to the time counting circuit of the present invention, the time between the edges of the pulse signal can be measured by using the signal group which sequentially rises or falls at constant time intervals. Since the interval becomes constant, highly accurate time data can be obtained. Further, since a complicated structure is not required, it is possible to realize a time counting circuit with high accuracy, low power consumption and a small circuit area.

Further, according to the pulse signal generating method of the present invention, it is possible to generate a plurality of pulse signals which sequentially rise or fall at constant time intervals.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a main part circuit 10 in a time counting circuit according to a first embodiment of the present invention.

FIG. 2 is a graph showing changes in a normal output signal of each differential inverter in the differential inverter ring 11 shown in FIG.

3 is a graph showing changes in a normal output signal of each differential inverter and an inverted output signal of an even number of differential inverters in the differential inverter ring 11 shown in FIG.

FIG. 4 is a circuit diagram showing a configuration example of a differential inverter.

5 is a graph showing a result of simulation of changes in output signals of each differential inverter when the differential inverter ring 11 is configured by the differential inverter shown in FIG.

FIG. 6 is a configuration diagram showing an example of a time counting circuit according to the first embodiment of the present invention.

FIG. 7 is a diagram showing changes in output signals of the differential inverters in the differential inverter ring 11 shown in FIG. 1, regarding a first signal group and a second signal group, and first and second signals. It is a figure for explaining selection of a group.

FIG. 8 is a diagram for explaining the signal processing of the time counting circuit according to the first embodiment of the present invention, and a diagram showing changes in the output signal of each differential inverter.

FIG. 9 is a configuration diagram showing another example of the time counting circuit according to the first embodiment of the present invention.

FIG. 10 is a configuration diagram of a time counting circuit according to a second embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of a conventional time counting circuit.

FIG. 12 (a) is a graph showing a time change of an output signal of each inverter forming an inverter ring composed of an odd number of identical inverters, and FIG. 12 (b) is a rise time and a fall time of the output signal of the inverter. 6 is a graph showing that the delay time in each inverter is different when and are different.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Main part circuit 11 Differential inverter ring (delay circuit ring) 12 1st holding circuit row 13 2nd holding circuit row 20 Encoder (signal conversion means) 25 1st pre-encoder 26 2nd pre-encoder 27 Encoder 31 Inverter ring (delay circuit ring) 32 First holding circuit row 33 Second holding circuit row 34 Signal conversion means

Claims (18)

[Claims] 1. A time counting circuit comprising a delay circuit ring, which comprises a plurality of delay circuits and in which signal transitions are circulated by oscillation, wherein the delay circuit ring comprises a signal that rises or falls in sequence at regular time intervals. It is possible to output a signal group
A time counting circuit, which detects a transition position of a signal at one time in the delay circuit ring from the signal group. 2. An odd number of differential inverters are connected to their respective non-inverted output terminals and the inverting input terminals of the next-stage differential inverters, and each inversion output terminal is connected to the next-stage differential inverter in the non-inverted manner. A differential inverter ring, which is configured by connecting to an input terminal and is connected in a ring shape, in which signal transition is circulated by oscillation, and a normal output signal of an odd-numbered differential inverter in the differential inverter ring, and A first signal group including the inverted output signals of the even-numbered differential inverters, and a first signal group including the inverted output signals of the odd-numbered differential inverters and the normal output signals of the even-numbered differential inverters in the differential inverter ring. At least one of the two signal groups is input, and based on at least one of the first and second signal groups, the signal at one time in the differential inverter ring is input. Time counting circuit, characterized in that it comprises a counting means for determining the position of transfer. 3. The time counting circuit according to claim 2, wherein said counting means receives said first and second signal groups as an input and raises each signal in order from said first and second signal groups. A time counting circuit for selecting a group and determining a transition position of a signal at one time in the differential inverter ring based on the selected signal group. 4. The time counting circuit according to claim 2, wherein the counting means receives the first and second signal groups as input, and each signal of the first and second signal groups falls in order. A time counting circuit for selecting a signal group and determining a transition position of a signal at one time in the differential inverter ring based on the selected signal group. 5. The time counting circuit according to claim 2, wherein the counting means is provided at a normal output terminal of an odd stage differential inverter and an inverting output terminal of an even stage differential inverter in the differential inverter ring. Each holding circuit holds the output signal of the differential inverter connected to each holding circuit at the timing of the edge of the pulse signal to be measured. From a plurality of holding circuits connected to the inverting output terminals of the odd-numbered differential inverters and the normal output terminals of the even-numbered differential inverters in the differential inverter ring, respectively. Holds the output signal of the differential inverter to which each holding circuit is connected at the timing of the edge of the pulse signal to be measured, and A second holding circuit string output as a second signal string; a first signal string output from the first holding circuit string; and a second signal string output from the second holding circuit string;
Signal conversion means for converting and outputting the numerical data representing the transition position of the signal in the differential inverter ring, wherein the time counting circuit is based on the numerical data output from the signal conversion means. Then, the time counting circuit is characterized in that the time between edges of the pulse signal to be measured is obtained. 6. The time counting circuit according to claim 5, wherein the signal converting means includes a portion of the first and second signal trains where the signal changes from one logic level to another logic level. A time counting circuit characterized by detecting as a transition position of a signal in a ring, obtaining and outputting numerical data representing the detected position. 7. The time counting circuit according to claim 5, wherein the signal conversion means receives the first signal train output from the first holding circuit train as an input, and the signal in the first signal train is A first pre-encoder for generating and outputting first data indicating a portion where one logic level changes to another logic level, and a second signal train output from the second holding circuit train as an input A second pre-encoder that generates and outputs second data indicating a point where a signal changes from one logic level to another logic level in the second signal sequence; and a second pre-encoder that outputs the second data. The first data and the second data output from the second pre-encoder are used as inputs, and the first data and the second data are numerical data representing the transition position of the signal in the differential inverter ring. Time counting circuit, characterized in that an encoder that converts the data. 8. The holding circuit constituting each of the first and second holding circuit trains is a sampling circuit for holding an output signal of each differential inverter as an analog signal. Time counting circuit. 9. A first signal group composed of an inverter ring configured by connecting an odd number of inverters in a ring shape, in which signal transitions are circulated by oscillation, and an output signal of an even-stage inverter in the inverter ring. And a second output signal of an odd number of inverters in the inverter ring
A time counting circuit which receives at least one of the signal groups of 1) and calculates the position of the transition of the signal at one time in the inverter ring based on the input signal group. 10. The time counting circuit according to claim 9, wherein the counting means receives the first and second signal groups as input, and each signal of the first and second signal groups rises in order. A time counting circuit for selecting a group and determining a transition position of a signal at one time in the inverter ring based on the selected signal group. 11. The time counting circuit according to claim 9, wherein the counting means receives the first and second signal groups as input, and each signal of the first and second signal groups falls in order. A time counting circuit for selecting a signal group and determining a transition position of a signal at one time in the inverter ring based on the selected signal group. 12. The time counting circuit according to claim 9, wherein the counting means includes a plurality of holding circuits respectively connected to output terminals of even-numbered stages of inverters in the inverter ring,
A first holding circuit row that holds the output signal of the inverter to which each holding circuit is connected at the timing of the edge of the pulse signal to be measured, and outputs the plurality of held signals as a first signal row; Consisting of a plurality of holding circuits each connected to the output terminals of the odd-numbered inverters in the ring,
At the timing of the edge of the pulse signal to be measured, each holding circuit holds the output signal of the connected inverter,
A second output that outputs the plurality of held signals as a second signal sequence
Of the holding circuit sequence, the first signal sequence output from the first holding circuit sequence, and the second signal sequence output from the second holding circuit sequence, and the transition position of the signal in the inverter ring. And a signal converting means for converting the numerical data to output and outputting the numerical data, wherein the time counting circuit is based on the numerical data output from the signal converting means, A time counting circuit characterized by obtaining the time of. 13. The time counting circuit according to claim 12, wherein the signal converting means includes a portion of the first and second signal trains where the signal changes from one logic level to another logic level. The time counting circuit is characterized in that it is detected as the position of the transition of the signal in, and numerical data representing the detected position is obtained and output. 14. A pulse signal generation method for generating a plurality of pulse signals, comprising: connecting a plurality of differential inverters to respective non-inverted output terminals and an inverting input terminal of a differential inverter at the next stage; Of the differential inverter train using a differential inverter train in which a signal transition propagates, which is configured by connecting the inverting output terminal of the A method for generating a pulse signal, characterized in that the normal output signal and the inverted output signal of the constituent differential inverter are alternately taken out in the order of the differential inverter, and the taken out signals are made into a plurality of pulse signals. 15. A pulse signal generation method for generating a plurality of pulse signals, comprising an inverter ring configured by connecting an odd number of inverters in a ring shape, wherein the transition of signals circulates, the inverter ring The output signal of each of the inverters constituting the above is taken out every other inverter, and the taken out signals are made into a plurality of pulse signals. 16. A pulse signal generation method for generating a plurality of pulse signals, wherein an odd number of differential inverters are connected to respective non-inverted output terminals and an inverting input terminal of a differential inverter at the next stage. A differential inverter ring, which is configured by connecting each inverting output terminal and a non-inverting input terminal of a differential inverter at the next stage and connecting them in a ring shape, using a differential inverter ring in which signal transitions circulate, A pulse signal generation method characterized in that the normal output signal and the inverted output signal of each differential inverter forming a ring are alternately taken out in the order of the differential inverter, and the taken out signals are made into a plurality of pulse signals. 17. The pulse signal generation method according to claim 16, wherein the first signal is composed of a normal output signal of the odd-numbered differential inverters and an inverted output signal of the even-numbered differential inverters in the differential inverter ring. And at least one of the second signal group consisting of the inverted output signal of the odd-numbered differential inverters and the normal output signal of the even-numbered differential inverters in the differential inverter ring, and the extracted signal group A method for generating a pulse signal, which comprises using a plurality of pulse signals. 18. A pulse signal generation method for generating a plurality of pulse signals by using an inverter train configured by connecting inverters in series and in which signal transition propagates, the inverter constituting the inverter train. When there is a difference between the rise time and the fall time of the output signal of the above-mentioned output signal, which has a substantial adverse effect on the design specifications regarding the edge interval between the plurality of pulse signals, the inverter train is configured. A method for generating a pulse signal, wherein the output signal of the inverter is taken out every other inverter, and the taken out signals are made into a plurality of pulse signals.