JPH09293987A - Hybrid integrated circuit package - Google Patents

Hybrid integrated circuit package

Info

Publication number
JPH09293987A
JPH09293987A JP8105495A JP10549596A JPH09293987A JP H09293987 A JPH09293987 A JP H09293987A JP 8105495 A JP8105495 A JP 8105495A JP 10549596 A JP10549596 A JP 10549596A JP H09293987 A JPH09293987 A JP H09293987A
Authority
JP
Japan
Prior art keywords
integrated circuit
hybrid integrated
circuit package
signal line
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8105495A
Other languages
Japanese (ja)
Inventor
Fumiaki Tsuji
文明 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8105495A priority Critical patent/JPH09293987A/en
Publication of JPH09293987A publication Critical patent/JPH09293987A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15192—Resurf arrangement of the internal vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components

Landscapes

  • Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve a hybrid integrated circuit package in noise.cross talk characteristics by a method wherein a signal line required to be protected against noise.cross talk is provided in three dimensions separate and isolated from other lines. SOLUTION: A signal line required to be protected against noise.cross talk is so laid as to be connected to a signal line outer connection terminal 4 provided in the upside of a package where a semiconductor IC chip 3 mounted on a wiring board 2 is housed, and other lines which are not required to be protected against noise.cross talk are laid so as to be connected to an outer connection terminal 5 provided in the base of the package. By this setup, the signal line can be laid in three dimensions, so that a hybrid integrated circuit package of this constitution can be improved in noise.cross talk characteristics.

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】本発明は混成集積回路パッケ
ージに関し、特にＥＭＩ（Ｅｌｅｃｔｒｏ ｍａｇｎｅ
ｔｉｃ ｉｎｔｅｒｆｅｒｆｅｒｅｃｅ）対策ＬＣＣ
（Ｌｅａｄｌｅｓｓｃｈｉｐ ｃａｒｒｉｅｒ）パッケ
ージの端子設置構造を有する混成集積回路パッケージに
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a hybrid integrated circuit package, and more particularly to an EMI (Electro magne
tic interface) Countermeasure LCC
The present invention relates to a hybrid integrated circuit package having a terminal installation structure of a (Leadless chip carrier) package.

【０００２】[0002]

【従来の技術】従来のＥＭＩ対策ＬＣＣパッケージの端
子設置構造を有する混成集積回路パッケージ（以下、混
成集積回路パッケージと記す）は図２に示すように、シ
ールド膜１の内部の配線基板２の上に搭載された半導体
ＩＣチップ３の電極は、信号ラインを含め全てがパッケ
ージ底面の同一面に設けられた外部接続用端子５に配線
接続された構造を有している。2. Description of the Related Art As shown in FIG. 2, a hybrid integrated circuit package (hereinafter referred to as a hybrid integrated circuit package) having a terminal installation structure of a conventional EMI countermeasure LCC package is provided on a wiring substrate 2 inside a shield film 1. All of the electrodes of the semiconductor IC chip 3 mounted on the board are connected to the external connection terminals 5 provided on the same surface of the package bottom surface by wiring.

【０００３】[0003]

【発明が解決しようとする課題】この従来の混成集積回
路パッケージでは、マザーボード上の配線パターンは同
一面上に形成しなければならないため、信号ラインが他
のラインからの影響を受け易く、ノイズ・クロストーク
特性が悪化するという問題点があった。In this conventional hybrid integrated circuit package, since the wiring patterns on the mother board must be formed on the same plane, the signal line is easily affected by other lines, and noise and noise There is a problem that the crosstalk characteristic is deteriorated.

【０００４】一般に、混成集積回路の端子や配線は、同
一平面上に形成されるため配線間の信号干渉を生じやす
い。また、混成集積回路の端子に接続される外部配線に
おいても同様に同一平面上で、かつ長い配線が必要とな
るため、配線間での信号干渉が大きな問題となってい
る。Generally, since terminals and wirings of a hybrid integrated circuit are formed on the same plane, signal interference between wirings is likely to occur. Also, external wirings connected to the terminals of the hybrid integrated circuit also require long wirings on the same plane and on the same plane, so that signal interference between the wirings becomes a serious problem.

【０００５】さらに、このような混成集積回路の外部配
線と端子部を単独で完全シールドすることは困難である
ため、配線間干渉だけではなく外部電磁ノイズも受けや
すいという欠点も有している。Further, since it is difficult to completely shield the external wiring and the terminal portion of such a hybrid integrated circuit independently, there is a drawback that not only interference between wirings but also external electromagnetic noise is easily received.

【０００６】本発明は、配線や端子の中でも、特に重要
な信号ラインを混成集積回路の内部配線だけではなく、
外部電極（端子）部も含めてほぼ完全に独立シールドす
る目的でなされたものである。また、この外部電極から
引き出される配線にシールド線を用いることで、混成集
積回路外部配線についても良好なシールド効果を得るこ
とを目的とする。According to the present invention, among wirings and terminals, particularly important signal lines are not limited to internal wirings of a hybrid integrated circuit,
The purpose of this is to shield almost completely, including the external electrodes (terminals). Further, it is an object of the present invention to obtain a good shielding effect also on the external wiring of the hybrid integrated circuit by using a shield wire for the wiring drawn from the external electrode.

【０００７】[0007]

【課題を解決するための手段】本発明の混成集積回路パ
ッケージは、所定の信号ライン外部接続用端子を他のラ
インの外部接続用端子とは別に独立形成したことを特徴
とする。A hybrid integrated circuit package according to the present invention is characterized in that a predetermined signal line external connection terminal is formed independently of other line external connection terminals.

【０００８】[0008]

【発明の実施の形態】次に本発明の実施の形態について
図面を参照して説明する。Embodiments of the present invention will now be described with reference to the drawings.

【０００９】図１は本発明の一実施の形態の混成集積回
路パッケージの断面図である。本発明の第１の実施の形
態の混成集積回路パッケージの構造は、図１に示すよう
に、パッケージ外面全体に導体からなるシールド膜１を
有し、その内部の配線基板２の上に半導体ＩＣチップ３
が搭載されている。この半導体ＩＣチップ３の電極の
内、ノイズ・クロストーク対策が必要な信号ラインにつ
いては、パッケージ上面に設けられた信号ライン外部接
続用端子４に配線接続し、特にノイズ・クロストーク対
策が必要でない他のラインは、パッケージ底面に設けら
れた一般の外部接続用端子５に配線接続されている。こ
れにより立体配線が可能となり、重要な信号ラインのノ
イズ・クロストーク特性を向上させる効果が得られる。FIG. 1 is a sectional view of a hybrid integrated circuit package according to an embodiment of the present invention. As shown in FIG. 1, the structure of the hybrid integrated circuit package of the first embodiment of the present invention has a shield film 1 made of a conductor on the entire outer surface of the package, and a semiconductor IC on the wiring board 2 inside thereof. Chip 3
Is installed. Of the electrodes of the semiconductor IC chip 3, the signal lines that require noise / crosstalk countermeasures are connected to the signal line external connection terminals 4 provided on the package upper surface, and noise / crosstalk countermeasures are not particularly required. The other lines are wire-connected to general external connection terminals 5 provided on the bottom surface of the package. As a result, three-dimensional wiring is possible, and the effect of improving noise / crosstalk characteristics of important signal lines can be obtained.

【００１０】この構造の混成集積回路パッケージは、多
層プリント配線板の一部をざぐり、半導体ＩＣチップ３
を搭載するキャビティを形成し、このキャビティ内に半
導体ＩＣチップ３を搭載し電気的接続完了後、エポキシ
等の封止樹脂６で密封封入したものである。ここで、信
号ライン外部接続用端子４は、プリント基板形成時にス
ルーホールにて形成されたもので、半導体ＩＣチップ３
搭載部分のざぐり時にこの部位を避けて削ったために形
成されたものである。混成集積回路内部配線で、信号ラ
イン外部接続用端子４は、任意の位置に形成することが
できるため、外の信号ラインと同一平面上に形成される
パターン部が極めて少くでき、また、そのパターン部の
シールドも容易に形成できることになる。さらに、信号
ライン外部接続用端子４の立体的に形成されたスルーホ
ール部分についてもキャビティの側面にめっきを施すこ
とによって、シールド効果を高めることができる。In the hybrid integrated circuit package having this structure, a part of the multilayer printed wiring board is countersunk, and the semiconductor IC chip 3 is formed.
Is formed, the semiconductor IC chip 3 is mounted in the cavity, and after electrical connection is completed, the semiconductor IC chip 3 is hermetically sealed with a sealing resin 6 such as epoxy. Here, the signal line external connection terminal 4 is formed by a through hole when the printed circuit board is formed, and the semiconductor IC chip 3
It is formed by avoiding this part when the mounting part was spotted. In the internal wiring of the hybrid integrated circuit, the signal line external connection terminal 4 can be formed at an arbitrary position, so that the pattern portion formed on the same plane as the external signal line can be extremely reduced, and the pattern thereof can be reduced. The shield of the part can be easily formed. Further, the shield effect can be enhanced also by plating the side surface of the cavity with respect to the three-dimensionally formed through hole portion of the signal line external connection terminal 4.

【００１１】配線間の信号干渉は、その配線間に形成さ
れる静電容量に比例して大きくなる。従って、配線を接
近させる程、平行配線部位を長くする程信号干渉が大き
くなる。図１の構成では、この平行配線部位を極力少く
することと、配線間を近接させないようにしたものであ
る。Signal interference between wirings increases in proportion to the electrostatic capacitance formed between the wirings. Therefore, the closer the wirings are and the longer the parallel wiring portions are, the larger the signal interference becomes. In the configuration of FIG. 1, the number of parallel wiring portions is reduced as much as possible and the wirings are not brought close to each other.

【００１２】前述のように、従来の混成集積回路の端子
や配線は同一平面上に形成されるため配線間の信号干渉
を生じやすい。また、外部接続用端子５に接続されてい
る外部配線においても同様に、同一平面上で、かつ長い
配線が必要となり、配線間の信号干渉を生じやすい。こ
のような問題に対し本発明は、信号干渉をできるだけ小
さくするため、配線や端子を分離配置することで混成集
積回路パッケージの内部配線や外部電極をほぼ完全にシ
ールドできる効果を有することになる。As described above, since the terminals and wirings of the conventional hybrid integrated circuit are formed on the same plane, signal interference between the wirings is likely to occur. Similarly, the external wiring connected to the external connection terminal 5 also requires a long wiring on the same plane, which easily causes signal interference between the wirings. In order to reduce the signal interference as much as possible, the present invention has the effect of almost completely shielding the internal wiring and the external electrodes of the hybrid integrated circuit package by separately arranging the wiring and terminals in order to minimize signal interference.

【００１３】[0013]

【発明の効果】以上説明したように本発明は、ノイズ・
クロストーク対策が必要な半導体ＩＣチップの信号ライ
ンを、他のラインとほぼ完全に分離配線できるようにパ
ッケージ上面と底面にそれぞれの外部接続用端子を設け
たことにより、立体配線が可能になり、重要な信号ライ
ンのノイズ・クロストーク特性を向上させることができ
るという効果を有する。As described above, the present invention is
By providing external connection terminals on the top and bottom of the package so that the signal line of the semiconductor IC chip that requires measures against crosstalk can be almost completely separated from other lines, three-dimensional wiring is possible. This has the effect of improving the noise / crosstalk characteristics of important signal lines.

【図面の簡単な説明】[Brief description of drawings]

【図１】本発明の一実施の形態の混成集積回路パッケー
ジの断面図である。FIG. 1 is a cross-sectional view of a hybrid integrated circuit package according to an embodiment of the present invention.

【図２】従来の混成集積回路パッケージの一例の断面図
である。FIG. 2 is a cross-sectional view of an example of a conventional hybrid integrated circuit package.

【符号の説明】[Explanation of symbols]

１ シールド膜 ２ 配線基板 ３ 半導体ＩＣチップ ４ 信号ライン外部接続用端子 ５ 外部接続用端子 ６ 封止樹脂 1 Shield Film 2 Wiring Board 3 Semiconductor IC Chip 4 Signal Line External Connection Terminal 5 External Connection Terminal 6 Sealing Resin

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】 所定の信号ライン外部接続用端子を他の
ラインの外部接続用端子とは別に独立形成したことを特
徴とする混成集積回路パッケージ。1. A hybrid integrated circuit package, wherein a predetermined signal line external connection terminal is formed separately from an external connection terminal of another line.
JP8105495A 1996-04-25 1996-04-25 Hybrid integrated circuit package Pending JPH09293987A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8105495A JPH09293987A (en) 1996-04-25 1996-04-25 Hybrid integrated circuit package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8105495A JPH09293987A (en) 1996-04-25 1996-04-25 Hybrid integrated circuit package

Publications (1)

Publication Number Publication Date
JPH09293987A true JPH09293987A (en) 1997-11-11

Family

ID=14409187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8105495A Pending JPH09293987A (en) 1996-04-25 1996-04-25 Hybrid integrated circuit package

Country Status (1)

Country Link
JP (1) JPH09293987A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006179732A (en) * 2004-12-24 2006-07-06 Hitachi Ltd Semiconductor power module
US9001486B2 (en) 2005-03-01 2015-04-07 X2Y Attenuators, Llc Internally overlapped conditioners
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
CN111613614A (en) * 2020-06-29 2020-09-01 青岛歌尔智能传感器有限公司 System-in-package structure and electronic device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9019679B2 (en) 1997-04-08 2015-04-28 X2Y Attenuators, Llc Arrangement for energy conditioning
US9036319B2 (en) 1997-04-08 2015-05-19 X2Y Attenuators, Llc Arrangement for energy conditioning
US9054094B2 (en) 1997-04-08 2015-06-09 X2Y Attenuators, Llc Energy conditioning circuit arrangement for integrated circuit
US9373592B2 (en) 1997-04-08 2016-06-21 X2Y Attenuators, Llc Arrangement for energy conditioning
JP2006179732A (en) * 2004-12-24 2006-07-06 Hitachi Ltd Semiconductor power module
US9001486B2 (en) 2005-03-01 2015-04-07 X2Y Attenuators, Llc Internally overlapped conditioners
CN111613614A (en) * 2020-06-29 2020-09-01 青岛歌尔智能传感器有限公司 System-in-package structure and electronic device

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