JPH09293721A - Method for improving pattern design for integrated circuit structure processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the pattern design used for processing an integrated circuit by a method wherein the additional lines and the working lines to be formed on a semiconductor wafer have the equal surface region of conductive material with each other. SOLUTION: The distance in horizontal direction between the operating lines 2 and 3 exceeds the threshold distance X, and the distance in horizontal direction between operating lines 5, 6 and 7 and operating lines 8, 9 and 10 exceeds the threshold distance Y. As a result, dummy lines 11 to 16 are printed in a region 17 in order to guarantee the uniform printing of all operation lines. In order to guarantee the desired uniformity in the load for the patterning conducted for formation of both operation lines and dummy lines, a patterning operation is conducted on the single layer, consisting of conductive material, where both operating lines and dummy lines are formed, and the operation lines and the dummy lines are formed with the same material.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in the pattern configuration used in the processing of integrated circuits on semiconductor wafers to form lines and contact holes and / or vias. More particularly, the present invention is a method for adjusting the distribution or density of lines and contact holes and / or vias in a layer, wherein the layer provides a more uniform distribution throughout the layer. The method has a part of.

[0002]

BACKGROUND OF THE INVENTION In forming integrated circuit structures, active devices such as transistors and diodes are formed in and on semiconductor wafers such as single crystal silicon wafers. Passive elements such as resistive and capacitive structures are also formed at this location. Such electrical connections or "wirings" have traditionally been referred to as metallization in the field of integrated circuits.
is called. However, at least some of the wiring can be made using conductive materials other than metals, such as doped polysilicon, metal silicide, metal nitride, and the like. The metallization includes the formation of contact holes (filled with a conductive material) that extend through one or more first insulating layers to electrodes such as the source, drain and gate electrodes of the underlying MOS transistor. I'm out. The metallization also includes a patterned conductive layer on such an insulating layer. The conductive layer is formed by masking and selectively etching a layer of conductive material, such as a metal layer, to make electrical contact with an underlying filled contact hole or filled via, such first patterning. Through the insulating layer to electrically contact the next patterned layer of conductive material with the filled via, thereby vertically extending between the plurality of patterned layers of conductive material. Giving electrical contact.

Contact holes are formed underneath one or more insulating layers down to the active device, and (in at least some instances) such contact holes are made of, for example, one or more metals, doped. After filling with a conductive material such as polysilicon, metal silicide, etc., a thin layer of conductive material (typically a metal) is formed over the wafer by sputtering, CVD techniques or vacuum deposition. Undesired parts of this layer are removed by patterning (ie a photomask and etching process leaving the surface of one or more insulating layers covered by thin lines of conductors). Typically, one or more intermediate layers are formed on the first patterned layer of electrically conductive material, and at least one subsequent patterned metal layer is formed on the one or more intermediate layers. Is formed. Metal-filled holes or vias are then formed on the intermediate layer to provide vertical electrical interconnections between the individual patterned layers of conductive material.

As described above, when forming lines and contact holes and / or vias on an integrated circuit, a photomask and an etching method which form the entire patterning of the lines, contact holes and vias are important.
Patterning errors can result in warp or misalignment that can eventually lead to unwanted electrical properties.
ent). Therefore, the patterning process
It is crucial to guarantee a satisfactory product. Alignment and exposure continue to be centered on the photomask portion of the patterning.

During the photomask process, an optical phenomenon, diffraction, occurs that causes printing to change from one part of the circuit to another. Diffraction results from the bending of the energy wave as it passes through the opaque edge of the mask. Align (a
Improvements in the ligner) have been achieved by using short wavelengths that reduce diffraction effects. However, even with short wavelengths, undesired resolution and alignment accuracy still occur.

For example, if a circuit is confined to the core (ie, has many gates connected to metal lines), the printing of the lines in the circuit remains homogeneous. However, if the circuit has one portion where the lines are provided with high density and the other portion where the lines are provided with not so high density (hereinafter referred to as “Lonely line”), the line concerned And the roughness of the edges of the lines vary between the one part and the other part due to this diffraction phenomenon. As the circuits get smaller, the undesirable degree of line size change increases significantly. For example, in the case of a diffraction on a line with a size of 1.0 micron, perhaps about 0.05 micron (which is about 5% of the size of the diffraction), but with a size of 0.5 micron. In the case of diffraction on the line, the magnitude of the effect is about the same, but the unacceptable degree of acceptance is about 10% of the magnitude of the diffraction.

The optical resolution and alignment accuracy are
The lack of planarity in the photoresist in which the image of the mask is optically projected by irradiation can be affected. Chemical / mechanical polish (hereinafter referred to as “CMP”)
various flattening techniques have been proposed, including ng procedures). However, some types of materials (eg,
Such a method involving the simultaneous chemical etching and mechanical polishing of metals, oxides and organic resist materials, etc.) and the density of non-homogeneous lines on integrated circuits affects the ability of such CMP, It produces the desired planarity of the structure.

Etching in semiconductor processing can require inherent limitations due to the physical layout of the circuit. The ideal anisotropic etch leaves vertical walls in the resist and metal layers. However, since the etchant will dissolve the top of the wall for a longer time than the bottom,
The resulting holes are wider at the top than at the bottom. Therefore, the etching is isotropic. This etching undesirably undercuts the metal layer under the resist, causing resist lifting and narrow lines between lines. Dry etching, such as reactive ion etching, reduces undercuts, but does not completely solve this problem.

Dry etching techniques rely, in part, on the material of the mask layer (usually photoresist) to achieve anisotropic contours. This has a side effect that makes the etching anisotropically sensitive to mask pattern density. Therefore, lonely lines in the isolated pattern will have a higher anisotropic etch than patterns made in higher densities (because less photoresist is in the areas with lonely lines). Both patterns can be on the same chip configuration.

Another problem that should be effectively referred to above is the problem of microloading, where the etching rate of the material depends on the amount of material to be etched.

Similar problems occur in etching through the insulating layer of vias and / or contact holes when the density of the vias and / or contact holes is not uniform across the semiconductor wafer.

In US patent application Ser. No. 07 / 732,843 and in US patent application Ser. No. 08 / 362,839, referred to as "dummy line" in the area where the "Lonely line" is provided. The problem of irregular line spacing or density provided by the provision of additional lines is incorporated herein.

Another factor to consider during patterning is electron migration. Typically,
In designing a circuit layout, lines are constructed with a predetermined width, regardless of future use. This layout design may create electron transfer problems, especially in lines that must support heavy loads. Long, very thin metal lines (typically made of aluminum) that carry high currents are especially prone to electron transfer. The high currents create an electric field in the leads, generating heat. As current and frequency increase, electron transfer resistance decreases. During electron transfer, the aluminum in the lead becomes mobile and begins to diffuse to both ends of the lead. Under extreme conditions, the leads themselves are cut. In the past, at worst, current densities sufficient to support such currents were estimated and all metal lines were made wide.
This is not preferable because the line width becomes smaller and more functions can be mounted on one chip.

Another phenomenon that occurs during patterning is the inherent stress of the layered structure. Since multiple layers of different materials are printed on the circuit, different expansion / contraction rates, hardnesses and intrinsic stresses are established in each layer. This stress, which nullifies the metal in the absence of voltage, is due to the linear expansion of the soft material (ie, generally metal). Therefore, the stresses of layering can produce electrical cuts. Such stress also causes the lower metal layer, such as aluminum, to expand into the via in the insulating layer above the metal layer. When the density of vias on stressed aluminium is not homogeneous, the amount of expansion to less dense vias may be more pronounced, with volcano-like vertical aluminum vias or vias Causes piercing expansion.

Therefore, it is an object of the present invention to improve the pattern configuration used in the processing of integrated circuit structures.

[0016]

A circuit chip according to a first aspect of the present invention is (a) a semiconductor wafer, and (b) a semiconductor chip on the semiconductor wafer for electrically connecting circuit elements on the semiconductor wafer. An operating line made of a conductive material formed on the semiconductor wafer, and (c) one or more additional lines formed on the semiconductor wafer and adjacent to the operating line. A circuit chip consisting of a wire consisting of: one or more additional wires and an operating wire working together having a surface area of the electrically conductive material that is at least equal to a predetermined amount. There is.

It is preferable that the semiconductor device further comprises a plurality of operating lines formed on the semiconductor chip.

At least one of the plurality of operation lines is preferably a Lonely line.

It is preferable that the one or more additional lines are provided within a predetermined range from the Lonely line.

An integrated circuit structure according to a second aspect of the present invention is an integrated circuit structure formed on a semiconductor wafer, wherein the integrated circuit structure comprises (a) electrical connection of circuit elements of the integrated circuit structure. A plurality of operating lines made of a conductive material for connecting to, and (b) one or more additional lines on the semiconductor wafer formed from the conductive material,
The plurality of lines of motion and one or more additional lines,
At least a surface area of the conductive material equal to a predetermined amount is provided.

A third aspect of the invention is a circuit layout method, the method comprising: (a) determining a surface area of a layer of conductive material used in the circuit layout; ) In the step (a), comparing the determined surface area with a first predetermined value; and (c) determining a distance between the first motion line and the second motion line, Determining whether the motion line or the second motion line is a Lonely line; (d) comparing the distance with a second predetermined value; and (e) the distance being a second predetermined value. When it is larger than the value, it is characterized in that a dummy line is provided at a predetermined distance from the Lonely line.

A fourth aspect of the present invention is a method for forming contact holes and / or vias in an insulating layer of an integrated circuit structure, the method comprising: (a) insulating on the integrated circuit structure. Forming a layer, (b) forming an etching mask on the insulating layer, the contact layer and / or the via being formed in the insulating layer by etching the insulating layer through the opening of the mask. Forming a mask including a plurality of openings to: (c) evaluating a distribution of respective amounts of regions of the insulating layer exposed by the mask to be etched; and (d) in the insulating layer. And forming a dummy via to further uniformly etch the exposed region of the insulating layer, and to add another opening in the mask.

[0023]

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises a conductive line pattern configuration, a via pattern configuration and / or a contact hole pattern configuration for a variety of reasons. The reasons include improved load uniformity in chemical / mechanical polishing of patterns of conductive material. The improvement is made to balance the load while etching the lines, vias and / or contact holes, and to relieve stress in the metal under regions or areas of low via density. . The operating grid can be used in integrated circuit structures to analyze the spacing of lines or vias provided for optical and non-optical proximity effects.

First Embodiment In the first embodiment, a dummy line is printed on the circuit in order to guarantee the standardization of the size of all operating lines. The number and position of the dummy lines depends on the spacing between the Lonely lines in both the horizontal and vertical directions. In other words, when the spacing exceeds a predetermined threshold distance in both horizontal and vertical directions,
A dummy line is inserted. In the first embodiment,
The effect of lithography that the threshold distance in the horizontal and vertical directions is about 2 μm or less is emphasized. The value of this threshold distance changes when individually considering the undercut problem. For example, the proportion of photoresist in the surface area of the chip is 100μ.
When increasing to more than m. Clearly, the threshold distances in the horizontal and vertical directions are different.

In order to ensure the desired uniformity in the loading for the patterning performed to form both the operating lines and the dummy lines, a single layer of conductive material forming both the operating lines and the dummy lines is ensured. By simultaneously patterning the layers of, the operating line and the dummy line are formed of the same material. Typically, the fixed part (wi) of the wiring of the operating line (and dummy line)
The ring harness) is formed by patterning a layer of aluminum. Due to the conductive layer patterned to form the operation lines and the dummy lines, not only non-metal conductive material but also other materials are used. It is within the scope of the invention to use Such other metallic and conductive non-metallic materials include gold, tungsten,
There are titanium, tantalum, niobium, alloys, doped polysilicon and conductive compounds. An example of the alloy is an alloy of titanium and tungsten. Further, examples of the conductive compound include metal silicide and metal nitride, such as tungsten silicide, titanium silicide, and titanium nitride. Therefore, the use of the terms "metal" and "metallization" herein is intended to be illustrated, and "metal"
It will be appreciated that there are no restrictions on other conductive materials used in place of the.

According to FIG. 1, the movement line 2 in the horizontal direction
The distance between the line and the motion line 3 is the threshold distance X
(THRESH-X) is exceeded. Further, the distance between the operation lines 5, 6, 7 and the operation lines 8, 9, 10 in the horizontal direction exceeds the threshold distance Y (THRESH-Y). Therefore, in order to ensure a uniform printing of all operating lines, the dummy lines 11-16 are printed in the area defined by the dashed area 17.

These dummy lines may be left floating. That is, these dummy lines are not connected to the operating lines to avoid short circuits. Alternatively, if desired, the dummy line simply has an unused portion of all the pattern of the line and is electrically isolated (floating) from the rest of the fixed portion of the wiring.
You can choose not to be done. Usually, the dummy lines 11, 12, 13, 14, 15, 16 have the same size. Therefore, the larger the area between the operation lines is defined, the more dummy lines need to be inserted.

To facilitate identification, dummy lines should be formed separately from the operating lines. FIG. 6 shows two possible methods. In FIG. 6, the operating line 70 is adjacent to the two dummy lines 71 and 72. Typically, dummy line 71 is used to nullify the lithographic effect and dummy line 72 is used to solve the problem of undercutting. Lithographic effect resolution involves very small tolerances on distance. Therefore, having one smooth surface on the dummy line 71 is important for solving the above problem. However, the dummy line has various shapes, and forming the dummy line in the closed loop causes an unwanted antenna effect.

The interactive feedback measuring the amount of photoresist on the metal layer significantly reduces the problems associated with undercutting during etching. The photoresist comprises a polymer that is especially light-sensitive, ie energy-sensitive. Polymers are macromolecules containing carbon, hydrogen and oxygen that are formed in a particular repeating pattern. When multiple lines are etched adjacent to each other, ie, within the threshold distance above, this process provides carbon molecules from the polymer that forms a coating on the sidewalls to prevent undercuts. . Therefore, the etching becomes substantially anisotropic.

However, less carbon is utilized to form the required coat when the line being etched is not adjacent to other lines. for that reason,
The etching becomes imperfect, ie, more isotropic, causing dielectric breakdown due to undercuts in the circuit.

According to the present embodiment 1 and the current manufacturing technology, in order to supply a sufficient amount of carbon to form the coating which later guarantees anisotropic etching,
At least about 17% of the chips should be covered with photoresist. It should be noted that, in effect, the amount of photoresist is the amount of metallization on the chip. When the amount of the photoresist (metallization) is 17%, the placement of the dummy lines is not considered important even though the placement area is small. for that reason,
Determining the extent of photoresist affects the printing of dummy lines.

In order to solve the problem of electron transfer, the current carried by each line now comes to be determined from the electrical design before processing. According to the invention, the width of the lines depends largely on the utilization and current density of each line. In one embodiment of the present invention, the line through which a large current flows is wider than 2 μm, and the line through which a small current flows is narrower than 2 μm. The second or last method can arrange parallel lines (line (s)) for high current flow, or reduce the current density through any metal line.

Since the stress in layering is a function of the amount of metal and the hardness of the material, in other words the insulating properties, the user has a very long line along the tip to exert the influence of the metal. By running it, the probability of electrical disconnection is increased. According to the invention, the metal line comprises a stress relief. In one embodiment, the stress relievers are 90 on line 20 as shown in FIG.
There is a step (jog). The 90-degree step is used because it is easy to represent by numbers. An angle of 45 degrees or 60 degrees only requires a minor deformation, even though solving the stress problem of overlaying it, thus making the output longer to be numerically represented. Relief of stress may also be achieved by a vertical step extending from one metal layer to another.

In an embodiment of the present invention, the above idea is based on a router system using a computer programmed with the software shown in Appendix A of US Pat. No. 5,379,233. (Router system), which was included here for reference. The definitions of the options used in the software program and in the various parts described in detail below are set forth in Table 1 below. In this table, the letters "OB" represent obscure parts, and the letters "#" represent micron times 1000 unless specified otherwise. For example, # = 2
0000 => 200μ.

[0035]

[Table 1]

FIG. 3 shows a flow chart showing the process steps performed by the computer to determine the placement of the dummy lines and to ensure the available carbon molecules for anisotropic etching. Loops of the flow chart can sometimes be traversed to ensure that there is a certain amount of photoresist on the wafer during etching. In the first pass through the loop, the numerical use of the metal is based on the metallization used in implementing the electrical circuit. As will be explained in more detail below, the area of the metallization measured in the first step of the subsequent pass comprises dummy lines added during processing.

In step 40, the computer measures the utilization of the metal on the chip. The use of the metal is
Functionally equivalent to the area of photoresist on the chip surface. After this measurement is made, the computer will proceed to step 4.
Head to 1.

Step 41 asks if the metal utilization is below the minimum requirements. In this embodiment, the software defines at least about 17% of the surface area of the chip as the minimum requirement.

When metal utilization is below the minimum requirements, the computer proceeds to step 42 of initializing the mesh. In step 42, initialization includes forming a mesh of dummy lines, also called local wires, in a particular pattern. According to FIG. 4, the mesh M in this embodiment is composed of the local wires 100 to 180. The local wires are provided in parallel with each other. Although not shown in this embodiment, the local wire is generally positioned in an advantageous direction with respect to the line of motion. The motion line is a physical wire (phys).
Also called ical wires), used as the metallic layer to be inspected. The mesh M has reference numerals 101, 102, and 10.
3 and 104 over the already formed actual wire shown in FIG. In one embodiment, the distance between adjacent ends of the local wire is about 8-9 μm while the local wire 100-
180 has a width of about 8 μm. As can be seen from FIG. 4, FIG. 4, like the other drawings, need not be sized.

In pass 1, shown in step 43, all overlap between the actual wire and the local wire is removed. Such removal ensures that there is no short circuit between the local wire and the actual wire. At this time, the distance between the local wire and the actual wire must be at least 37 "bloat.
1 ”. "Bloat 1" is the narrowest point between the physical wire and the local wire. In one embodiment, "bloat 1" is about 15 μm. For example, the dashed block 50
The blackened portions of the local lines 160-180 are removed from the mesh, as shown at. Furthermore, if the length of the local wire becomes shorter than a predetermined threshold distance, which is 100 μm in one embodiment, the local wire portion is removed.

During pass 2 seen in step 44, if the local wire is redundant, the local wire is removed. Excess removal is performed as follows. That is, when those distances are shorter than the predetermined distance D,
The local wire is formed from the left and right of the actual wire. The distance D is usually defined as the threshold distance subtracted ("bloat 1", the shortest distance between the actual wire and the local wire, plus the width of the local wire). Distance D is approximately slightly longer than one half of the threshold distance. For example, as shown in FIG. 5, a portion 5 of the local wire 59.
If 8 is formed from the left and right sides of the actual wires 60 and 61, keeping the distance D, then a portion 58 of the local wire 59 is removed, respectively. If the local wire portion to be removed is smaller than the threshold value, it is removed again. As shown in FIG. 5, the portion 63 extended to above the broken line 62 is smaller than the threshold value and is therefore removed.

During pass 3 seen in step 45, the local wire portion inside the predetermined outer edge of the actual wire is marked and left. At this time, the part that is not marked is removed. For example, as seen in FIG. 4, dummy lines or dummy line portions outside the predetermined outer edge of each actual line (100-103) (indicated by dashed areas 50-53) are added on the chip. Removed to minimize the amount of dummy line metallization performed. If the boundary touches a local line, the local line is not removed, as is the area 50 with the line 150. Therefore, the hatched portions of the dummy lines 10 to 18 are removed. The remaining dummy lines are indicated by double-width hatching.

During the final step 46, all remaining portions of the local lines are formed in a distinguishable pattern to facilitate identification of those local line portions.
After step 46 is completed, the computer first performs step 4 to determine the metal utilization which is the current sum of the actual wire and the remaining portion of the local line.
Return to 0. If the metal usage has not yet reached the minimum requirements, the computer repeats steps 42-46 until the metal usage reaches the minimum requirements. Step 4 in the second crossing through these steps
Before repeating steps 2-46, the local line section formed during the first cross-section of steps 42-46 is performed while the second cross-section is performed in a similar manner as previously performed. Treated as the actual wire and the formation of the mesh. Local lines formed on the second crossing and all subsequent crossings are treated similarly. When the requirements are reached, the computer causes the step 47.
The program ends with. The final placement is then ready for manufacturing.

The present embodiment is merely an example and is not limited to this. Next, the problem related to metal undercut will be described. In lithographic, electron transfer, and stress issues in forming layers, the methods are similar, if not identical.

Embodiment 2 Chemical / mechanical polishing (hereinafter referred to as "CMP") is an effective means for planarizing an integrated circuit structure.
The effective means results in the required degree of desired flat surface required for accurate subsequent lithography. For example, if the material being planarized (eg, photoresist) has an etch rate that is close to that of the material being planarized (eg, silicon oxide), a dry etch may be used to planarize the structure. Can be used, but if the material is present at the same rate that does not respond to dry etching, CM
P technology is used and is sometimes preferred.

However, the material to be planarized is C
If they do not react at the same rate to the MP process and the ratio of such metals is different in one area and another in the surface to be planarized, the density of the material that can be removed at a higher rate The high areas are ground more quickly, resulting in recesses rather than the desired flat surface. Conversely, areas free of, or less densely present, such material that can be removed at a higher rate will be polished at a lower rate, resulting in a higher portion of the surface. This can happen, for example, if the electrically conductive lines are separated by an insulating material formed between the lines. And, the lines do not become uniformly spaced portions, that is, the lines do not have a uniform density in the integrated circuit structure. The line may be, for example, aluminum, gold, tungsten, titanium, a titanium / tungsten alloy, or the like, or other electrically conductive material, such as an impurity-doped semiconductor, such as impurity-doped polysilicon. Made of material. The insulating material is silicon oxide (C
The reaction to the MP process is slow). C
The same effect occurs for vias and / or contact holes formed in the oxide layer and filled with electrically conductive material prior to the planarization step using the MP process.

On the other hand, in the conventional case, as shown in A of FIG. 7 and B of FIG.
02, 204, 206, 210 and 212 are formed on the integrated circuit structure, and a silicon oxide layer 220 is added to the lines 202, 204, 206, as shown in FIG.
When formed between and on 210 and 212, the structure is not uniformly responsive to the CMP process because the tungsten is more easily polished than the silicon oxide. Therefore, the tungsten lines 202, 20
In the areas where 4,206 are shown in close proximity to each other, there is less silicon oxide surface between the lines being polished and the polishing is done at a faster rate. At this time, the region in which the tungsten is widely arranged includes the region in which more silicon oxide is exposed to the CMP process, and further, the entire structure is polished at a low rate. As a result, as shown in FIG.
A low area indicated at 30 results. In the lower area,
The remaining portions 202a, 204a, 206a of the first tungsten lines 202, 204, 206 are closely placed between the remaining silicon oxide layers 220a. At that time, the high area indicated by the arrow 232 indicates the portion where the tungsten lines 210 and 212 are more arranged, that is, the area where more silicon oxide is to be polished.

According to the present embodiment, as shown in FIG. 8, in order to achieve a more uniform loading of the structure for performing CMP, preferably the same material as lines 210 and 212. Formed dummy lines 214,
216 and 218 are formed adjacent to lines 210 and 212. This in turn resulted in a more equal line density with the remaining silicon oxide layer 220b, showing that the CMP polishing step was performed with a more uniform value over the entire area and the desired planarization. The surface is obtained. With respect to the wire fixing part made of a layer formed by patterning an electrically conductive material, the additional lines 214 and 216, which are referred to herein as “dummy lines”, are referred to.
It should be noted that and 218 need not be electrically floating. That is, the additional dummy line is electrically connected to the remaining wire fixing portion. However, it is sometimes preferred that the additional dummy line not be connected to the rest of the wire securing part to prevent possible short circuits.

Determining where to form the dummy lines to balance the load during the CMP process can be accomplished, for example, by examining the structure for lower areas after CMP planarization, or by using wire clamps. It is actually empirical by using the method as described above for balancing the load during the patterning of the electrically conductive layer of the constituent material.

Embodiment 3 Problems similar to those discussed above that occur during the formation of lines (eg, wire anchors) by etching during patterning of an electrically conductive layer include: , Or one of the underlying active or passive devices in the semiconductor wafer to form contact holes, such as etching of an insulating layer of, for example, silicon oxide or silicon nitride. Or during etching of two or more insulating layers, or through an intermediate insulating layer where a via is formed between two electrically conductive layers, such as between two patterned metal layers. Also face.

That is, providing a via or a contact hole on an insulating layer or a contact hole or a layer having a low density of vias results in the formation of an oversized contact hole or via. The cause is the lack of etchant depletion that typically occurs where the insulating layer or via density is high. Therefore, such a problem is due to the etching of the first insulative layer, or the layer in which the contact holes to the underlying semiconductor substrate are formed, and the formation of vias between the layers of electrically conductive material. Common to the subsequent etching of the insulating layer. Hereinafter, the term "via" will be used for both vias and contact holes in the insulating layer. Also, such vias, which are subject to such one-side etching in order to be arranged at low density and at regular intervals, are hereinafter referred to as "lonely vias".

A "lonely via" is defined as a via having a diameter that is larger than the average diameter of the vias in the same insulating layer. The difference between the diameter of the Lonely via and the average diameter is up to about 10% of the average diameter. For example, if the average diameter of the vias in the insulating layer is about 0.5 micron (μm), a Lonely via may have a difference between the diameter and the average diameter of at least 0.
Defined as a via up to 05 μm. For example, 0.
Since the permissible error in the technique of forming a via having a diameter of 5 μm is ± 0.07 μm, it is 0.05 μm for etching the one surface due to insufficient consumption of the etching solution.
All vias that already have an overdimension of are likely to eventually be out-of-specification due to the additional effects of other patterning tolerances such as photolithographic inaccuracy.

Therefore, in the present invention, it is important that the “Lonely via” is consistent with the design, and the etching solution is used when the hole or via is etched through the insulating layer. It is important to form dummy vias adjacent to the lonely vias so that the consumption is more uniform across the insulating layer.

After being filled with the electrically conductive material to some extent (at this time, the active via is also filled),
The dummy via is not electrically connected to any part of the wire fixing portion (the patterned layer made of the electrically conductive material formed on the insulating layer) on the dummy via. It should be noted that for other layers below the insulating layer, the placement of the dummy vias is not important. However, a problem arises when the blocked dummy via is electrically insulated from the wire fixing portion above. This can be easily solved by forming the dummy via on the insulating region below the insulating layer. For example, it can be solved by forming the dummy via or the via of a part of the insulating layer that over-treats the oxide region of the substrate.

As will be described below, the need for the dummy vias and the subsequent placement of the dummy vias on the integrated circuit structure is, for example, using a grid superimposed on the surface of the structure, eg, It is in fact empirically determined by inspection and measurement, either view or some other means, of the diameter of the via, which is considered to be a "lonely via" by its position on said insulating layer. The identification of lonely vias and the corresponding placement of dummy vias to assure lonely vias is described in US patent application Ser.
/ 362,839 and No. 07 / 732,84
A variation of the computer controlled routine system disclosed and discussed in U.S. Pat.

As shown in the flow chart of FIG. 12, the layout of the dummy vias required on the integrated circuit is performed according to the steps described later. In the first step,
Optional grids are formed on the surface of the insulative layer masked for etching. In a second step, the relative area placement of the regions of the insulating layer that are exposed using a mask for etching is evaluated using the grid. In the third step, additional holes are provided to position the exposed areas of the insulating layer to be more uniformly etched by the dummy vias formed in the insulating layer. , Added to the mask.
Further, in a fourth step, the size and density of the dummy vias to which the insulating layer is added is determined based on a predetermined limit of tolerance in the area of the etched region.

Further, as shown in FIG. 10, the densely existing discrete vias 250 are formed in the insulating layer 24.
When formed in one area of the 0, the lonely via 260 is formed elsewhere, and the lack of etchant depletion in the area around the via 260 results in the formation of a larger diameter via 260. However, the provision of dummy vias 270 (shown in black in FIG. 10) makes the loading effect more uniform and more even the consumption of etchant, resulting in a more uniform diameter for all vias.

Control of etching uniformity of one or more insulating layers to form vias or contact holes is to form used vias of more uniform diameter, regardless of via density. Similarly, similar techniques are used to improve the identification of other structures formed by etching one or more insulating layers. Note that, as an example of the above-mentioned other structure, for example, there is a configuration of an oxide spacer to a sidewall such as a gate electrode by the arrangement and configuration of a dummy spacer.

Fourth Embodiment A dummy via is arranged in a region where a lonely via exists.
When supplying a load that evenly consumes the etching solution,
If placed correctly, there will be little variation in via diameter dimension, ie, variation in dimension approaching 1: 1 (theoretical goal) will fulfill another important role.

In a typical multilayer interconnect system, insulating (non-conducting) layers and electrically conductive materials are successively deposited and patterned. Typically, a patterned layer of electrically conductive material, such as a line, comprises a major metal portion comprising aluminum or an alloy of aluminum such as an Al-Cu alloy or an Al-Cu-Si alloy. . Usually, the main metal portion is sandwiched between a thin lower layer of titanium and a thin upper layer of titanium and a thin upper layer of titanium nitride. The thin layer is relatively stiff and effective in preventing hillrock and in other deformations of the aluminum line during heat treatment.

However, it is not taken into account that the stresses that occur in the aluminum lines are sufficient to cause the aluminum to flow upwards through the vias (such as oxides that are overlying insulating Areas where material is not suppressed). Due to the spread of the outflow of aluminum, this causes the formation of volcano and hillock and is also dependent on the increasing amount of stress. On the other hand, the amount of stress increase is related to the density of the vias, since a small extension to many vias can reduce the stress increase without overly affecting the top surface of the structure. However, on the contrary, in the region where the lonely vias are arranged, the region where the density of the vias is low causes the aluminum to more destructively flow out through the lonely vias to the upper surface of the insulating layer, resulting in the above-mentioned undesirable Volcano and hill rock occur.

According to the invention, in order to relieve the stress and prevent or suppress the formation of the volcano or hillock, the dummy vias are deliberately, ie at any given time, the distance between the actual vias or the operating vias is predetermined. It is placed near Lonely Via so that it becomes the range. In order to be aware of the presence of the undesired volcanoes and hillocks, the predetermined range is practically empirically determined by optical inspection of the final structure using microscopy means such as a scanning electron microscope.

The need for the dummy vias and the subsequent placement of the dummy vias on the integrated circuit is in addition to that of the structure, as described below, for example, in addition to the grid overlying the contours of the metal layers. It can be determined proactively by predicting the contour of the lower metal layer above the surface. In addition, the contours and lattice of the metal layer are then analyzed to predict where dummy vias are needed, ie Lonely vias, which are likely to cause the hillocks and / or volcanoes.

It should be noted, however, that the dummy vias, which are not similar to the above-described embodiment, and which are effective in removing stress in the lower metal layer, pass through the insulating layer and reach the metal layer. . That is, the dummy via does not end on the underlying insulating portion such as the field oxide portion in the previous embodiments. This is shown in FIG.
It is shown in FIG. FIG. 11 shows an integrated circuit structure 300.
Have a region oxide portion 302 and a first oxide layer 304. Region oxide 302 and first oxide layer 304 are formed on integrated circuit structure 300 with metal layer 306. The metal layer 306 is formed on the first oxide layer 304. The second oxide layer is formed on the metal layer 306 and the region oxide 302. Closely spaced motion vias 310, 312, and 314
Is shown on the left side of the figure, with the lonely via 316 being shown on the right side. The stresses that occur in the lower metal layer 306 are distributed between the working vias 310, 312 and 314. However, the stress in the metal layer 306 adjacent to the lonely via 316 is such that it is relieved via only one via. Since the dummy via 320 such as the lonely via 316 reaches the metal layer 306, the placement of the dummy via 320 adjacent to the lonely via 316 can relieve the stress. However, the metal layer 306
The placement of the dummy vias 322 in the oxide layer 308, down to region oxide 302 instead of, does not provide stress relief. With reference to the above description, the placement of the dummy vias on the metal layer, but not on the underlying insulative region, is determined by prediction of the outer structure of the lower metal layer.

In another embodiment of the present invention, the occurrence of the aforementioned undesired volcanoes and hillocks is suppressed or prevented by forming one or more dummy vias adjacent to each operating via. The density of the structure does not allow 100% guarantee of the working via with dummy vias. However, due to the high density of the adjacent operation vias, the operation vias that cannot supply the adjacent dummy vias are not “lonely vias”, that is, they are not the vias considering the above-mentioned problems regarding the formation of hillrock and volcano. So this is not a problem.

As shown in the flow chart of FIG. 13, the placement of the dummy vias required on the integrated circuit for stress relief in the underlying metal layer is performed by the following steps. In the first step, an optional grid is formed on the surface of the insulating layer that is masked for etching. In the second step, the outer shape of the lower metal layer is overlaid on the lattice. In a third step, the placement and location of the additional dummy vias in the insulative layer is predetermined with respect to the location of the metal layer below the via in the insulative layer and the stress relief of the metal layer. It is decided based on the necessity of. Further, in a fourth step, dummy holes are added to the mask needed to form dummy vias in the insulating layer up to the lower metal layer.

Embodiment 5 In the arrangement of the dummy lines and / or the dummy vias, in order to assist both the examination of the structure and the confirmation of the accurate position, the arrangement of the dummy lines and the contact holes and / or the vias for all the purposes described above are provided. Contact can be facilitated by the use of a grid overlaid on an image of the integrated circuit structure, such as is implemented in software and displayed on a CRT screen with the integrated circuit. Any of the above-mentioned purposes is to provide a more uniform etching of said lines, the purpose of patterning and the contact of contact holes and / or vias to facilitate planarization of the integrated circuit structure by chemical / mechanical polishing, Or a more uniform supply of stress relief for the underlying metal layer under stress. The general procedure used is shown in the flow chart of FIG.

The configuration of the grating overlaid on the surface of the integrated circuit structure is, for example, that of a photoresist layer on an electrically conductive layer to form two lines, two adjacent lines or two intersecting lines. It has been used previously to study and adjust for optical proximity problems in patterning, and enhances the image projected onto the photoresist, so that (using a positive resist system or a negative resist system). The metal lines are equal either horizontally or vertically. The use of finely spaced grid images makes it possible to ascertain the exact location on the integrated circuit where potential problems exist, and
It makes it possible to provide a correction means for the arrangement of non-printed lines (known as mechanical correction) adjacent to the regular lines on the master mask. The master mask is a mask in which the image projected on the photoresist results in a very wide line structure. Also,
The guaranteeing means are for example wider patterns in areas where the lines are very thin or narrow. Another example of a potential problem and its correction means is the extension of the line end on the master mask, where the image projected onto the photoresist is a very short line structure, resulting in the projected image being The addition of serifs to the corners outside the "rounded corner" feature structure area and the projected image results in a reduction of serifs in the corners inside the feature structure area. To be achieved.

According to the invention, the finely-spaced gratings are used in the investigation and adjustment of the non-optical proximity problem as described above. Either an operating line or an operating via (or contact hole) during the etching of the electrically conductive material (for forming the line) or the etching of the insulating layer (for forming the via or contact hole). In order to balance the load on the wafer, to help identify the exact location where the dummy line and via and / or contact hole should be located for compensation for etchant depletion and high etchant concentration. In addition, the overlapping grids can help identify areas where problems may occur.

Similarly, the finely-spaced grids, as described above, assist in identifying where the adjacent materials have high densities of different polishing rates, thereby facilitating the CMP procedure. Assists in examining the integrated circuit structure for potential proximity problems when using, and in addition, correct addresses for correcting dummy lines.
The confirmation aid is provided to allow the polishing process to be performed uniformly.

Finally, in the provision of precise positioning of these positions, which compensates for dummy vias which extend through the insulating layer down to the area below the insulating layer in which the metal layer is located, in relation to said lower metal layer. Due to the lack of vias or the reduced density of vias that can provide stress relief in different directions, the finely-spaced grid identifies the metal layer under the insulating layer where increased stress will occur. Used in combination with an image of the contour of the lower metal layer to be used in the area.

[0072]

Therefore, in accordance with the present invention, the use of dummy lines and contact holes and / or vias to compensate for various effects that affect the quality of the integrated circuit structure results in etching. A metal layer used in the construction of the operating line for liquid depletion effects, chemical / mechanical polishing planarization effects, and electrical interconnection of various parts of the integrated circuit structure. The effect of increasing the stress at is significantly improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing dummy lines interposed between operation lines of the present invention.

FIG. 2 is an explanatory diagram showing an example of stress relief points on a metal wire of the present invention.

FIG. 3 is a flowchart of a computer processing process to be performed by the present invention.

FIG. 4 is an explanatory diagram showing an example of wiring of a dummy line after removing a part of a mesh of a local line of the present invention.

FIG. 5 is an explanatory diagram showing a method of removing an extra local line executed in the lotus 2 of the computer program of the present invention.

FIG. 6 is an explanatory diagram of two forms of dummy lines.

FIG. 7 is an explanatory cross-sectional view showing an example of a conventional integrated circuit structure.

FIG. 8 is a cross-sectional explanatory view of an integrated circuit structure showing a dummy line added in the vicinity of the Lonely line of the present invention.

FIG. 9 is a flow chart showing the process of using an image of a superposed grating on an image of an integrated circuit structure for analyzing optical and non-optical proximity effects of the present invention.

FIG. 10 is a top view of an integrated circuit structure showing the formation of dummy vias or contact holes in the insulating layer of the present invention.

FIG. 11 is a cross-sectional explanatory diagram of an integrated circuit structure showing an insulating layer formed on a metal layer of the present invention.

FIG. 12 is a flow chart illustrating a method of adjusting the distribution of contact holes and / or vias in the integrated circuit structure of the present invention.

FIG. 13 is a flow chart illustrating a method for adjusting via distribution in an integrated circuit structure of the present invention.

[Explanation of symbols]

 2, 3, 5, 6, 7, 8, 9, 10, 70 Operating line 11, 12, 13, 14, 15, 16, 71, 72 Dummy line 250 Via 260 Lonely via 270 Dummy via 300 Integrated circuit structure 316 Lonely via 320, 322 dummy via

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Keith Chao, United States, 95129 Sanhouze, California, Broadmoor Drive 719 (72) Inventor Rattan Cay Chowdry United States, 95129 Milpitas, Serpa 1646 (72) Invention Gauri Cidas United States, 95121 California, Sanhousey, Force Plain Coat 2783 (72) Inventor Nicholas Cay Ave United States, 95120 California, Sanhousey, Almondwood Way 781 (72) Inventor Ashok Kay Kapoor United States , 94303 Amarillo, Palo Alto, California 1056 (72) Inventor Thomas Marron America United States, 95051 California, Santa Clara, Wood Duck Avenue 963

Claims (25)

[Claims] 1. (a) a semiconductor wafer; (b) an operating line made of a conductive material formed on the semiconductor wafer for electrically connecting circuit elements on the semiconductor wafer; and (c) the above. A circuit chip comprising one or more additional lines formed on a semiconductor wafer and provided adjacent to the operation line, the line comprising a conductive material, the one or more additional lines being provided. A circuit chip, characterized in that the additional lines and the operating lines each have a surface area of said electrically conductive material which is at least equal to a predetermined amount. 2. The circuit chip according to claim 1, further comprising a plurality of operation lines formed on the semiconductor chip. 3. The circuit chip according to claim 2, wherein at least one of the plurality of operation lines is a Lonely line. 4. The circuit chip according to claim 3, wherein the one or more additional lines are provided within a predetermined range from the Lonely line. 5. An integrated circuit structure formed on a semiconductor wafer, the integrated circuit structure comprising: (a) a plurality of conductive materials for electrically connecting circuit elements of the integrated circuit structure. An operating line, and (b) one or more additional lines on the semiconductor wafer formed from the conductive material, the plurality of operating lines and one or more additional lines comprising:
An integrated circuit structure comprising a surface area of said conductive material that is at least equal to a predetermined amount. 6. A method for laying out a circuit, the method comprising: (a) determining a surface area of a layer of conductive material used in the layout of the circuit; and (b) in the step (a). Comparing the determined surface area with a first predetermined value, and (c) determining a distance between the first motion line and the second motion line, wherein the first motion line or the second motion line is Determining whether it is a Lonely line,
(D) comparing the distance with a second predetermined value;
(E) if the distance is greater than a second predetermined value,
A method comprising the step of providing a dummy line at a predetermined distance from the lonely line. 7. An integrated circuit structure formed on a semiconductor wafer, the structure comprising: (a) a conductive material formed on the semiconductor wafer for electrically connecting circuit elements of the integrated circuit structure. A plurality of operation lines made of a conductive material, (b) one or more dummy lines formed on the semiconductor wafer made of the conductive material, and (c) an operation line and the dummy lines and the operation An insulating layer formed between a line and a dummy line, wherein the one or more dummy lines are positioned on the semiconductor wafer with respect to the operating line and chemically and mechanically polished to provide a surface of the structure. The structure is characterized in that it enables the flattening of the surface and simultaneously prevents the formation of low spots on the flattened surface. 8. The structure of claim 7, wherein the conductive material is selected from the group consisting of metals, conductive metal compounds and doped polysilicon. 9. The structure according to claim 7, wherein the insulating layer comprises a silicon oxide film. 10. The structure according to claim 7, wherein the conductive material is tungsten and the insulating layer is a silicon oxide film. 11. Flattening an integrated circuit structure comprising a semiconductor wafer having a plurality of operating lines of conductive material and an insulating layer formed on and between the operating lines using chemical / mechanical polishing. A method of laying out a circuit for use in planarization, the method comprising: conducting on a wafer to allow homogeneous removal of material across the wafer during a planarization step using chemical / mechanical polishing. A method comprising forming a sufficient number of dummy lines made of a conductive material. 12. The method further comprises: determining a position on the wafer at which the operating line is separated by a distance greater than a predetermined amount; and forming the dummy line on the wafer adjacent to the position. The method of claim 11, comprising: 13. An integrated circuit structure formed on a semiconductor wafer, comprising: (a) an insulating layer formed on the wafer, and (b) at least one formed through the insulating layer.
One working contact hole and / or via, and (c) at least one dummy contact and / or via formed through the insulating layer, wherein the at least one working contact hole and / or via is: In order to prevent a non-homogeneous reduction of the etchant during the formation of the at least one working contact hole and / or via and the at least one dummy contact and / or via, the at least one working contact hole and ( Or) An integrated circuit structure, wherein a via is provided in the insulating layer. 14. The integrated circuit structure of claim 13, wherein the at least one working contact hole and / or via and the at least one dummy contact and / or via have substantially equal diameters. 15. The integrated circuit structure according to claim 13, wherein the insulating layer is made of a silicon oxide film. 16. A method for forming contact holes and / or vias in an insulating layer of an integrated circuit structure, the method comprising:
The method comprises: (a) forming an insulating layer on the integrated circuit structure; and (b) forming an etching mask on the insulating layer by etching the insulating layer through the opening of the mask. Forming a mask including a plurality of openings to form contact holes and / or vias in the insulating layer, (c) a respective amount of the area of the insulating layer exposed by the mask to be etched. Evaluating distribution, and (d) forming dummy vias in the insulating layer to add another opening in the mask to etch the exposed areas of the insulating layer more evenly. A method comprising: 17. The method of claim 16 further comprising the step of determining the size and density of such added dummy vias based on predetermined tolerance limits on the size of the etched areas. The method described. 18. An integrated circuit structure formed on a semiconductor wafer, comprising: (a) one or more metal layers formed on the semiconductor wafer; and (b) one or more metal layers formed on the one or more metal layers. One or more insulating layers formed on (c)
At least one operating via formed through the insulating layer for electrically connecting to the one or more metal layers; and (d) the one or more insulating layers through the one or more insulating layers. An integrated circuit structure comprising at least one dummy via formed to one or more metal layers below the above insulating layer, wherein: An integrated circuit structure, wherein the at least one dummy via is positioned in the one or more insulating layers to provide a homogeneous stress relief of stress in the one or more metal layers. 19. Each of said operating vias in said one or more insulating layers adjacent said operating vias to provide local stress relief in one or more metal layers adjacent said operating vias. One or more dummy vias are provided, which allow one or two through the operating vias.
19. The integrated circuit structure according to claim 18, wherein stress is applied to the upper surface of the insulating layer. 20. The one or more metal layers are made of a metal selected from the group consisting of aluminum, tungsten, titanium, gold, tantalum and niobium, and the insulating layer is made of a silicon oxide film. 20. The integrated circuit structure as claimed in claim 19. 21. One or more metal layers having one or more insulation layers, the one or more insulation layers being formed on the metal layer with at least one operating via. A homogeneous stress relief in said one or more metal layers below said one or more insulating layers with respect to said at least one operating via. At least one dummy via provided to provide
Alternatively, a method including a step of forming two or more insulating layers. 22. A step of providing one or more dummy vias adjacent to each of the operation vias, whereby metal of which stress is applied to the upper surface of one or more insulating layers through the operation vias. 22. The method of claim 21, wherein the expansion prevents surface non-uniformity. 23. A method of adjusting the distribution of lines of conductive material on the surface of an integrated circuit structure, the method allowing analysis of the density of lines spaced on the surface, the method comprising: A method comprising overlaying a grid on the surface to more accurately locate regions of irregular spacing density. 24. A method for adjusting the distribution of contact holes and / or vias through one or more insulating layers of an integrated circuit structure, the method comprising:
Allowing the analysis of contact hole and / or via density in the insulating layer above contact hole and / or
A method comprising overlaying a grid on the upper surface of the one or more insulating layers in order to more accurately identify the position of the region where the via spacing density is irregular. 25. A step of overlaying an image of the metal film on the upper surface of the one or more insulating layers to allow the provision of dummy vias extending through the one or more insulating layers to the metal layer. 25. The method of claim 24, wherein